AN BFU910F FE for Ku band Universal Single LNB applications. Document information. Keywords Abstract

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BFU910F FE for Ku band Universal Single LNB applications Rev. 1 8 December 2015 Application note Document information Info Keywords Abstract Content BFU910F, Frontend, Ku band, LNA, LNB This Application Note describes the reference design of a two stage LNA Frontend for Ku band Universal Single LNBs based on BFU910F. BFU910F in combination with LS9105 bias device, with its very good noise figure, high gain, low current, simplicity of the bias circuitry and small size, can provide a very competitive solution for Ku band LNB Frontend applications

Revision history Rev Date Description 1 20151208 First publication Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 2 of 28

1. Introduction 2. General description BFU910F is a discrete SiGe-C HBT. It is produced in QuBIC4mmW Gen9 which is NXP s newest BiCMOS platform process for high performance RF applications in the mmwave domain. The extrinsic base resistance has been decreased by several methods, most importantly by self-alignment of the extrinsic base connection to the emitter. As a result, lower base resistance, lower noise and higher cut off frequency have been achieved. The new process is robust and manufacturable and it results in improved noise performance without significantly adding to process complexity BFU910F has outstanding NF and gain performances at Ku band frequencies, achieved at relatively low bias current. Using these assets, BFU910F has been brought to market to replace GaAs phemts for Ku band LNA applications NE3503 from Renesas, one of the most popular phemt on the market, is being used as comparison reference for BFU910F throughout this document. 2.1 Basic concept LNBs are electronic devices mounted outdoor on the satellite dishes and used for satellite TV reception. Basically it is a receiver that ensures the required sensitivity level for the very weak input signals and down-converts the block of microwave frequencies (MW) to a lower block of intermediate frequencies (IF) simultaneously boosting the power level. Fig 1 below presents the constitutive elements of an LNB. These can be grouped into three major blocks generically named Probes, Frontend and DNC (down-converter). The Probes block incorporates all microwave / mechanical components of the receiving chain - feed-horn, waveguide and antenna probes responsible to pick-up the microwave signal from the dish and to bring it to the inputs of the LNB board. The Frontend block is a two input / single output / two stage amplification chain that ensures the sensitivity of the LNB. The DNC down-converts the microwave frequencies and boosts the power level. The Frontend (FE) is the core stage that quantifies the LNB noise performance change if GaAs phemts are replaced with NXP s BFU910F SiGe HBTs. From this perspective the most relevant parameters for the FE are the noise and the gain. The BFU910F Frontend reference design also introduces the new bias and control IC from LiSion, LS9105. With features fully in line with the concept of an HBT FE, it also contributes to the small size, low current and simplicity achievements of the design.. All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 3 of 28

Fig 1. LNB s constitutive blocks All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 4 of 28

2.2 System In LNB systems the FE has to compensate for the much higher NF of the DNC. Its gain is then a very important figure of merit. The system analysis in Fig 2 highlights the benefits of a higher gain device. The NF and gain inputs for the FE are simulation data: 0.7/23dB for NE3503 and 0.9/26dB for BFU910F The key point of the cascade noise figure analysis below is, in comparison with NE3503 FE, BFU910F FE ensures less NF degradation at LNB level: 0.05dB vs. 0.1dB. BFU910F FE ensures less NF degradation: 0.05dB in comparison with 0.1dB Fig 2. System analysis for BFU910F FE vs NE3503 FE LNBs All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 5 of 28

3. Objective The main objectives for the development of the BFU910F FE are: Create a reference design for a Ku band Universal Single LNB FE based on BFU910F Design the FE based on an LNB structure such that its layout and mechanical solutions can be easily translated into the higher level development of the LNB. Replace the I and L probes with 50Ω SMA connectors. Probes quality is not relevant to define the FE performance Incorporate LiSion s LS9105, the new bias and control IC specially produced to accommodate BJT FEs that do not require a negative bias supply This Application Note describes the reference design of the two stage LNA FE for Ku band Universal Single LNBs based on BFU910F, highlighting its benefits over the NE3503 phemt FE. 4. Requirements - ASTRA standard for Universal Single LNBs Astra s typical NF target for the LB / HB LNB is 1.1 respectively 1.3dB. Corresponding maximum values are 1.3 / 1.5dB Fig 3. Astra requirements for the Ku band Universal Single LNB All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 6 of 28

5. FE reference design using BFU910F 5.1 Block Diagram Fig 4. Block diagram for BFU910F FE with RF inputs on 50Ω SMA connectors 5.2 FE Schematic Fig 5. Schematic diagram for BFU910F FE with RF inputs on 50Ω SMA connectors All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 7 of 28

5.3 FE board layout 5.3.1 Printed circuit board details The PCB material used for the board of this FE is Rogers RO4003. The PC board consists of: 35um top metal layer, 0.5mm thickness low loss dielectric layer with εr = 3.38 and TanD=0.0024, and 35um bottom metal layer. Rogers RO4233 or Isola IS680-338 material can also be used. All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 8 of 28

5.3.2 Layout top layer view Fig 6. BFU910F FE layout top layer 5.3.3 Layout bottom layer view Fig 7. BFU910F FE layout bottom layer All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 9 of 28

5.4 Mechanics The FE top-lid and base bodies are AL 35mm x 30mm x 7mm. Their mechanical drawings and 3D view are in Fig 8, Fig 9, and Fig 10 respectively 5.4.1 Top-lid drawing Fig 8. Mechanical drawing for top-lid BFU910F FE 5.4.2 Base drawing Fig 9. Mechanical drawing for base BFU910F FE All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 10 of 28

5.4.3 FE mechanics 3D view Fig 10. FE mechanics 3D view 5.5 View and ports functions Fig 11. View and ports functions for BFU910F FE All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 11 of 28

Table 1. 5.6 BOM and assembly 5.6.1 BOM BOM for BFU910F FE Component Description Value Qty MFG /size C1, C2, C3, C6, C7 Capacitor 470pF / X7R 5 0402 C10, C11 Capacitor 100nF / X7R 2 0402 C4, C5 Capacitor 0.3pF 2 Murata GRM15 / 0402 C8, C9 Capacitor 100nF / Y5V 2 0603 R1, R2, R4 Resistor 100 3 0402 R3, R6 Resistor 10 2 0402 R7 Resistor 390 1 0402 R5 Resistor 270k 1 0402 R8 Resistor 27K 1 0402 R9 Resistor 100k 1 0402 Q1, Q2, Q3 MW RF transistor BFU910F 3 NXP / SOT343F IC1 LNB Bias/Ctr IC LS9105 1 LiSion / HTSOP-8 X1, X2 SMA RF connector bottom mounting 50 2 Giga-lane / PSF-S01 X3 SMA RF connector side mounting 50 1 Giga-lane / PSF-S01 X4 DC connector 1row / 3way 1 Molex/ PCB Printed circuit board RO4233 / RO4003 1 Rogers / 30mm x 30mm 5.6.2 Assembly FE Fig 12. Assembly drawing for BFU910F FE All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 12 of 28

6. Performance and measurement results 6.1 Summary results Table 2. Typical results measured on BFU910F FE Evaluation Board Operating frequency is 10.7 ~12.75GHz unless otherwise specified; Temp = 25 ºC Parameter Symbol Min Typ Max Unit Supply Voltage Vertical VccVer 10 13 14 V Supply Voltage Horizontal VccHor 16 18 20 V Supply Current Icc 14.5 15.5 16.5 ma Noise Figure NF [1] 0.9 1.1 db Power Gain Gp [2] 24.5 26 db Input Return Loss RLin 5 8 db Output Return Loss RLout 8 10 db Image rejection IMR 15 20 db Cross Polar rejection CPR 36 45 db Output third order intercept point OIP3 10 12 dbm [1] NF calibration uses Miteq AMF-3F as NF reference and Pre-Amp. Other professional amplifier can also be used. [2] Gain calibration does not include the Input / Output losses. All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 13 of 28

6.2 NF and Gain (NFG) NF FE BFU910F = 0.85dB, Gain FEBFU910F = 26.5dB / NF FE NE3503 = 0.65dB, Gain FEBFU910F = 23.5dB Fig 13. NFG comparison for FE BFU910F vs FE NE3503 All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 14 of 28

6.3 Gain, match and Image frequency rejection Gain FE BFU910F = 26dB, RLIN 8dB, RLOUT 10dB, IMR FEBFU910F 15dB Fig 14. Gain match and Image rejection for FE BFU910F, Ver and Hor inputs All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 15 of 28

6.4 NF and gain variation with temperature Similar NF variation (improvement) for BFU910F and NE3503 Fig 15. Low temperature behavior comparison for FE BFU910F vs. FE NE3503 All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 16 of 28

Similar NF variation (degradation) for BFU910F and NE3503 Fig 16. High temperature behavior comparison for FE BFU910F vs. FE NE3503 All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 17 of 28

6.5 Cross polar rejection Gain FE BFU910F = 26dB, CPR FEBFU910F = 45dB Fig 17. Cross polar rejection for FE BFU910F for Ver and Hor input All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 18 of 28

6.6 Linearity / OIP3 OIP3 = P f1+(p f1-p 2f1_f2)/2 = -7dBm + (-7 + 48)/2dB = 13.5dBm IIP3 = OIP3 Gain = 13.5dBm 26dB = -12.5dBm Fig 18. OIP3 for FE BFU910F 7. Equipment, setup and settings Table 3 below summarizes the list of equipment per measurement type, used to check the performances for the BFU910F FE Table 3. Equipment / measurement for BFU910F FE Equipment, type & feature Measurement NFG GMI Xpol OIP3 Temp Current FSU26: 26.5GHz SA with NF and PN option 1 x 1 x 1 x ZVA24: 24GHz 4 channel VNA 1 x 1x SMR20: 20GHz Signal Generator 2 x QL355TP: Dual Power Supply 1 x 1 x 1 x 1 x 1 x 1 x HP346A: 5dB ENR Noise Source 1 x 1 x VT4002: Temperature chamber 1 x All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 19 of 28

7.1 NF and gain (NFG) Fig 19. Noise Figure and Gain, measurement setup All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 20 of 28

7.2 Gain Match and Image rejection Fig 20. Gain Match and Image rejection, measurement setup All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 21 of 28

7.3 Cross polar rejection Fig 21. Cross polar rejection, measurement setup All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 22 of 28

7.4 Linearity / OIP3 Fig 22. OIP3, measurement setup All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 23 of 28

8. Conclusions The Universal Single LNB FE solution based on BFU910F, proposed and analyzed in this document, meets all requirements from ASTRA standard The Universal Single LNB FE based on BFU910F, in comparison with NE3503 FE, has slightly worse NF performance. However, due to its higher gain, the noise figure degradation at overall LNB level is negligible. BFU910F in combination with LS9105 bias device, with its very good noise, high gain, low current, simplicity of the bias circuitry and small size, can provide a very competitive solution for Ku band LNB FE applications. 9. Abbreviations / explanations Table 4. List of abbreviation within text Abbreviation FE LNA LNB DNC HBT SiGe SiGe-C Ku band NF NFG MW PN GMI CPR SA VNA SigGen ENR RF PCB BOM Stands for Frontend Low Noise Amplifier Low Noise Block Down Converter Heterojunction Bipolar Transistor Silicon Germanium Silicon Germanium - Carbon LNB / FE in the frequency band of 10.7 ~12.75GHz Noise Figure Noise Figure and gain Microwave (frequencies) Phase Noise Gain, match and Image frequency rejection Cross Polar rejection Spectrum Analyzer Vector Network Analyzer Signal Generator Excess Noise Ratio Radio frequency (block, frequency) Printed Circuit Board Bill of materials All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 24 of 28

10. Legal information 10.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 10.2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Evaluation products This product is provided on an as is and with all faults basis for evaluation purposes only. NXP Semiconductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of noninfringement, merchantability and fitness for a particular purpose. The entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. In no event shall NXP Semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. Notwithstanding any damages that customer might incur for any reason whatsoever (including without limitation, all damages referenced above and all direct or general damages), the entire liability of NXP Semiconductors, its affiliates and their suppliers and customer s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (US$5.00). The foregoing limitations, exclusions and disclaimers shall apply to the maximum extent permitted by applicable law, even if any remedy fails of its essential purpose. 10.3 Licenses Purchase of NXP <xxx> components <License statement text> 10.4 Patents Notice is herewith given that the subject device uses one or more of the following patents and that each of these patents may have corresponding patents in other jurisdictions. <Patent ID> owned by <Company name> 10.5 Trademarks Notice: All referenced brands, product names, service names and trademarks are property of their respective owners. <Name> is a trademark of NXP B.V. All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 25 of 28

11. List of figures Fig 1. LNB s constitutive blocks... 4 Fig 2. System analysis for BFU910F FE vs NE3503 FE LNBs... 5 Fig 3. Astra requirements for the Ku band Universal Single LNB... 6 Fig 4. Block diagram for BFU910F FE with RF inputs on 50Ω SMA connectors... 7 Fig 5. Schematic diagram for BFU910F FE with RF inputs on 50Ω SMA connectors... 7 Fig 6. BFU910F FE layout top layer... 9 Fig 7. BFU910F FE layout bottom layer... 9 Fig 8. Mechanical drawing for top-lid BFU910F FE... 10 Fig 9. Mechanical drawing for base BFU910F FE... 10 Fig 10. FE mechanics 3D view... 11 Fig 11. View and ports functions for BFU910F FE... 11 Fig 12. Assembly drawing for BFU910F FE... 12 Fig 13. NFG comparison for FE BFU910F vs FE NE3503... 14 Fig 14. Gain match and Image rejection for FE BFU910F, Ver and Hor inputs... 15 Fig 15. Low temperature behavior comparison for FE BFU910F vs. FE NE3503... 16 Fig 16. High temperature behavior comparison for FE BFU910F vs. FE NE3503... 17 Fig 17. Cross polar rejection for FE BFU910F for Ver and Hor input... 18 Fig 18. OIP3 for FE BFU910F... 19 Fig 19. Noise Figure and Gain, measurement setup... 20 Fig 20. Gain Match and Image rejection, measurement setup... 21 Fig 21. Cross polar rejection, measurement setup... 22 Fig 22. OIP3, measurement setup... 23 All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 26 of 28

12. List of tables Table 1. BOM for BFU910F FE... 12 Table 2. Typical results measured on BFU910F FE Evaluation Board... 13 Table 3. Equipment / measurement for BFU910F FE... 19 Table 4. List of abbreviation within text... 24 All information provided in this document is subject to legal disclaimers. NXP B.V. 2015. All rights reserved. Application note Rev. 1 8 December 2015 27 of 28

13. Contents 1. Introduction... 3 2. General description... 3 2.1 Basic concept... 3 2.2 System... 5 3. Objective... 6 4. Requirements - ASTRA standard for Universal Single LNBs... 6 5. FE reference design using BFU910F... 7 5.1 5.2 Block Diagram... 7 FE Schematic... 7 5.3 FE board layout... 8 5.3.1 5.3.2 Printed circuit board details... 8 Layout top layer view... 9 5.3.3 Layout bottom layer view... 9 5.4 5.4.1 Mechanics... 10 Top-lid drawing... 10 5.4.2 Base drawing... 10 5.4.3 FE mechanics 3D view... 11 5.5 View and ports functions... 11 5.6 BOM and assembly... 12 5.6.1 5.6.2 BOM... 12 Assembly FE... 12 6. Performance and measurement results... 13 6.1 6.2 Summary results... 13 NF and Gain (NFG)... 14 6.3 Gain, match and Image frequency rejection... 15 6.4 6.5 NF and gain variation with temperature... 16 Cross polar rejection... 18 6.6 Linearity / OIP3... 19 7. Equipment, setup and settings... 19 7.1 NF and gain (NFG)... 20 7.2 Gain Match and Image rejection... 21 7.3 7.4 Cross polar rejection... 22 Linearity / OIP3... 23 8. Conclusions... 24 9. Abbreviations / explanations... 24 10. Legal information... 25 10.1 Definitions... 25 10.2 Disclaimers... 25 10.3 10.4 Licenses... 25 Patents... 25 10.5 Trademarks... 25 11. Index... Error! Bookmark not defined. 12. List of figures... 26 13. List of tables... 27 14. Contents... 28 Please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'Legal information'. NXP B.V. 2015. All rights reserved. For more information, visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 December 2015 Document identifier: