A Microcode-based Memory BIST Implementing Modified March Algorithm

A Microcode-based Memory BIST Implementing Modified March Algorithm Dongkyu Youn, Taehyung Kim and Sungju Park Dept. of Computer Science & Engineering Hanyang University SaDong, Ansan, Kyunggi-Do, 425-791 Korea dkyoun@mslab.hanyang.ac.kr, parksj@mslab.hanyang.ac.kr { Abstract{ A new microcode-based BIST(Biult-In Self Test) circuitry for embedded memory components is proposed in this paper. The memory BIST implements march algorithms which are slightly modified by adopting DOF(Degree of Freedom) concept to detect ADOFs(Address Decoder Open Faults) on top of conventional stuck faults. Furthermore it is shown that the march BIST modified can capture a few NPSFs(Neighborhood Pattern Sensitive Faults) coupled with the Cellular Automata address generator and patterns. The microcode-based memory BIST proposed lends itself to performing different combinations of march and retention tests with less microcode storage than the other approaches. ò. Introduction{ It becomes highly important to test various kinds of defects rapidly and precisely to reduce the testing cost and to improve the memory quality especially under the SoC design environment. Memory defects can be modelled as stuck-at, coupling, transition, address decoder, and pattern-sensitive faults and it is known that the 80% of the failures are due to the leakage defects[1]. Among the different testing algorithms ranging from O( n ) to O(nlog(n)), BIST(Built-In Self Test) techniques with O( n ) to O(n) complexity algorithms are widely adopted for embedded memories[2]. Memory test patterns can be generated deterministically or randomly[3] through either a test equipment or a BIST circuitry. Test patterns generated randomly can detect not only modelled defects but non-modelled and timing defects[4-6], nevertheless deterministic march patterns are widely adopted for BIST and off-chip testing for their simplicity. A few hardwired memory BIST techniques have been developed[5-8] and recently some micro-coded memory BIST circuits are implemented for embedded memories[9-11]. In general micro-coded memory BIST has great flexibility in applying different combinations of test patterns for static and dynamic defects. Memory retention faults as well as conventional static faults are major targets with a register file or SRAM as a storage of the microcodes[9-11]. We introduce a different micro-coded BIST technique which aims to capture address decoder open faults in addition to conventional static faults. Furthermore a certain degree of neighborhood pattern sensitive faults are detected by cellular automata based address and pattern generators. The paper is organized as followings. After the introduction of the fault models and definitions in section ó, ADOFs and cellular automata for NPSF testing are described in section ô and õ respectively. A new micro-coded memory BIST is designed in section ö and the superiority over the conventional methods is addressed in section

followed by the conclusions. ó. Fault Models and Definitions{ Faults modelled from the memory defects can be summarized as followings[2,5,12,13]. 1) Stuck-at-Fault(SF) : Either a cell or a line is stuck to logical 0 or 1. 2) Transition Fault(TF) : 01(or 10) transition is impossible on a cell or a line. 3) Coupling Fault(CF) : When a cell is written to 01(or 10), the content of the other cell is changed. CF is generalized to k-coupling fault when k-1 cells are changed and furthermore classified into Inversion or Idempotent coupling faults upon the content changed. 4) Address Decoder Fault(ADF) : No cell will be accessed with a certain address, or multiple cells are accessed simultaneously, or a certain cell can be accessed with multiple addresses. 5) Address Decoder Open Faults(ADOF) : CMOS address decoder open faults are caused by open defects in the CMOS logic gates of the memory address decoders and, due to their sequential behavior, cannot be mapped to faults of the memory array itself. 6) Retention Faults(RF) : A cell fails to retain its logic value after some time. This fault is caused by a broken pull-up resistor. 7) Neighborhood Pattern Sensitive Fault(NPSF) : a typical neighborhood pattern sensitive faults preventing the base cell from being transited to certain value is called as static NPSF, and an NPSF is named as dynamic when a transition on the neighborhood cells triggers the transition on the base cell. This paper will focus on capturing dynamic defects like (6) and (7) as well as static faults like 1) - 5). ô. Address decoder open faults with modified 10N March 10N March test algorithm detecting stuck-at, transition, coupling, and ADF can be described as followings. M M arch Elem ent 0 r M 1 M 3 M 4 M 5 ( w 0 ) ( r 0 w 1 ) üµ ( r 0 w 1 ) ( r 1 w 0 ) ( Address Sequence operator Algorithm 1. 10N MARCH(C-) test. 0 ) {March element (r0, w1)} For cell := 0 to n-1 do begin read A[cell]; {Expected value = 0} write 1 to A[cell]; end; {March element (r1, w0)} For cell := 0 to n-1 do begin read A[cell]; {Expected value = 1} write 0 to A[cell]; end; Algorithm 2. March Test Element {(r0,w1), (r1,w0)}.

where each symbols,, w0, w1, r0, and r1 are defined as : / : Increase/decrease memory address w 0/1 : Write 0 / 1 value in each memory cell r 0/1 : Read 0 / 1 value from each memory cell For example 01 rising and 10 falling transition faults are detected by the M3, M4, M2 and M3 march elements. Besides the above 4 different types of classical static faults there exist a non-classical CMOS ADOF which is not detected by conventional march algorithms[4-6]. Suppose there exists an CMOS open defect on the address decoder as figure 1. Surely the defect causes a failure driving two wordlines at once. However in order to detect CMOS open faults the march algorithms must be augmented to generate three consecutive march elements by changing the order in which the memory addresses are generated[5,6]. The paper[5] has introduced the degree of freedom concept in the address generation of march algorithms and the LFSR(Linear Feedback Shift Register) replaces the up-down address counter for march BIST. This paper tries to further enhance the detection boundary to pattern sensitive faults by using Cellular Automata based address generator and random patterns. Figure 1. Address decoder and P-channel open defect. õ. NPSFs with Cellular Automata Address Generator LHCA(Linear Hybrid Cellular Automata) is implemented by combining transition matrix and LFSR of LCA(Linear Cellular Automata)[12,13]. The next state of a certain cell is dependent upon the current states of the cell itself and neighboring cells. Due to its superior randomness than LFSRs, CA is widely adopted for logic BISTs and cryptography. For the testing of neighborhood pattern sensitive faults, complicated deterministic test patterns can be applied by off-chip tester but it costs too high for the BIST implementation. This paper is focused to capture a certain amount of NPSFs in addition to conventional memory faults including CMOS ADOFs, thus we decide to make use of random address generator. It can be observed that if the target cells consecutively tested are located further apart the NPSF coverage can be more improved[2]. We design a LHCA combining rule 90 and 150 to generate maximum number of

patterns, and then realize that LHCA produces more randomized address patterns than an LFSR as can be seen from the figure 3. The odd/even numbered bits are connected to column/row address select bits respectively and the cell number shows the order in which the cell is visited. The shaded cells imply that neighboring celled are visited consecutively, thus the more the shaded cells the less the NPSFs may be detected by random address and random data memory BIST. As a random pattern generator, instead of conventional LHCA, we have implemented randomly inversed LHCA which is guaranteed to generate 2 K independent patterns but some patterns are randomly inversed, hence hopely results in better NPSF coverage. The simulation results are shown in table 1 and surprisingly enough the method based on LHCA address generator with randomly inversed test patterns shows highest NPSF coverage than other methods. In table 1, NI stands for non-inversed and RI stands for randomly-inversed random patterns. col row 0 1 2 3 4 5 6 7 0 1 35 37 50 2 39 42 52 1 34 10 45 28 53 62 31 61 2 49 6 18 25 43 32 59 60 3 36 57 12 7 16 47 58 30 4 41 11 4 23 3 54 17 44 5 51 29 8 26 22 20 24 27 6 38 46 13 19 56 14 5 9 7 64 15 55 21 40 63 48 33 Figure 2. Address sequence of complete CA in 8X8 memory. col row 0 1 2 3 4 5 6 7 0 1 39 37 52 2 35 42 50 1 64 63 55 33 40 15 48 21 2 38 14 13 9 56 46 5 19 3 34 62 45 61 53 10 31 28 4 41 54 4 44 3 57 17 23 5 36 47 12 30 16 11 58 7 6 49 32 18 60 43 6 59 25 7 51 20 8 27 22 29 24 26 Figure 3. Address sequence of complete LFSR in 8X8 memory. Table 1. Add. gen. Fault coverage of static NPSF in 8X8 memory using RI-LFSR16 as test data. Complete LFSR Complete CA Test cycles NI RI NI RI 10 cycles 15.28 14.06 16.23 15.71 20 cycles 25.17 24.91 25.35 27.08 30 cycles 30.21 34.11 29.86 36.89 40 cycles 35.33 42.36 36.02 46.61 50 cycles 39.32 48.09 40.02 52.52 60 cycles 44.10 53.99 43.49 57.53 70 cycles 47.92 59.29 46.18 63.02 80 cycles 50.95 62.41 47.66 66.15 90 cycles 53.73 65.62 49.83 69.79 100 cycles 55.90 68.23 51.22 72.31 150 cycles 62.33 76.30 55.47 83.16 200 cycles 65.02 78.91 57.12 87.15 250 cycles 66.32 80.64 58.07 88.45

ö. Microcode-Based BIST Controller Memory BIST consists of address generator, test pattern generator, and BIST control logic. The BIST controller can be implemented by either hardwired logic or microcode, and this paper proposes an efficient micro-coded controller. Microcodes have been stored in SRAM[10] but another test logic for the SRAM is required. Fully scannable register file instead of the SRAM was proposed in [11], but the area overhead exceeds the SRAM. The defects targeted by both techniques are data retention and conventional static faults. The first objective of our approach is to enhance the detection boundary by capturing CMOS ADOFs and NPSFs additionally. Address generators are implemented by complete cellular automata to capture CMOS ADOFs and additionally randomly inversed random patterns are applied for the partial detection of NPSFs. The second goal is to minimize the microcode storage by using a ROM and a small register file. The ROM contains core march elements with self-checking bits, and the small scannable register file only keeps the sequence order of march elements stored in the ROM. Figure 4 shows the micro-coded memory BIST whose major blocks are storage units, instruction decoder, up-down LHCA, instruction up-down counter, and comparator. Detailed explanation for each blocks can be summarized as follows: Figure 4. Microcode-based BIST. z Instruction up_down counter Instruction address of the ROM is selected by this log (X)+1 bit binary up_down counter. Initialized by test_enable signal and terminated by sending Test_end signal after executing the last instruction. z Instruction decoder By taking the instruction condition bits and LHCA terminal signals, it generates the up-down address and hold/enable signals.

z Storage unit (ROM) Conventional march test algorithms are stored in this 610 bits ROM. z Up-down LHCA This address generator is initialized by the test_enable signal and operated by the instruction up-down LHCA signal and LHCA hold/enable signals. LHCA terminal signal is launched upon the last address generation. z Comparator Error signal is produced by comparing the test data and RAM output data. The microcodes associated with each march operations and the corresponding control signals are described in figure 5. Figure 5. March test procedure and microcodes.. Experimental Results Our micro-coded memory BIST circuitry was designed onto a synchronous single port RAM using Synopsys Design Analyzer. The design is verified through the simulation as shown in figure 6, and it can be seen that (r0,w1) operation is repeated for each memory cells upon the instruction up_down counter. Table 2 presents the size of a ROM required if each march test is performed independently. MARCH C+ algorithm adding two Delay elements to MARCH C-, such as Delay;(r0,w1); Delay; (r1), is applied to detect retention faults. Among the march algorithms, we only store the MARCH A algorithm into the 50 bits ROM and different march testings are performed by giving the sequence number of the march operations into the 214 bits register file, and it is noticed that our technique requires only about one third of the other micro-code storages as shown in table 3.

Figure 6. Simulation result. Table 2. Microcode storages required by different march algorithms. Test Algorithm Complexity ROM Size (wordbit) MATS 4n 4 6 MATS+ 5n 5 6 MATS++ 6n 6 6 MARCH X 6n 6 6 MARCH Y 8n 8 6 MARCH C- 10n 10 6 MARCH C+ 15n 15 6 MARCH A 15n 15 6 Table 3. Comparison of microcode storages. Method Microcode Storage Size(bits) Our method SRAM (or Register file) ROM 156, Register file 214 174 SRAM 3214 448 ø. Conclusions An efficient microcode-based memory BIST technique is introduced in this paper. In addition to conventional static and retention faults, CMOS address decoder open faults and some of neighborhood pattern sensitive faults are detected with cellular automata based address generator. Compared with currently known microcode-based BIST techniques, our design requires only one third of those microcode storages. It is strongly believed that our BIST can be widely used for the embedded memory testing especially under the SoC design environment due to the superior flexibility and extendibility in applying different combination of memory test algorithms.

Acknowledgment This research has been supported in part by KOrea Science and Engineering Foundation (under contract 2000-1-30200-002-3). References{ [1] S. Oh, et. al., "Automatic Failure Analysis System For High Density DRAM," IEEE International Test Conference, pp.526-530, 1994. [2] A. J. Van de Goor, "Testing Semiconductor Memories," Theory and practice, John Wiley and sons, Chichester, UK, 1991. [3] P. H. Bardell and W. H. McAnney, "Self-Test of Random Access Memories," Proceedings of International Test Conference, 1985, pp. 352-355 [4] D. Niggemeyer, M. Redeker, and J. Otterstedt, "Integration of Non-classical Faults in standard March Tests," Records of the IEEE Intl. WorkShop on Memory Technology, Design and Testing 1997, pp.27-32, San Jose, USA [5] J. Otterstedt, D. Niggemeyer, & T.W. Williams, "Detection of CMOS Address Decoder Open Faults with March and Pseudo Random Memory Tests, ITC conf., Oct. 1998, pp.53-62. [6] M. Sachdev, "Open Defects in CMOS RAM Address Decoders," IEEE Design & Test of Comp., vol. 14, no. 2, pp.26-33, 1997. [7] P. H. Bardell, W. H. McAnney, and J. Savir, "Built-In Test for VLSI : Pseudorandom Techniques," Wiley Interscience, 1987. [8] M. Franklin, K.K. Saluja and K.Kinoshita, "A Built-In Self Test Algorithm for Row/Column Pattern Sensitive Faults in RAM's," IEEE Journal of Solid State Circuits, vol.25, no.2, pp. 514-524, April 1990. [9] H. Koike, T. Takeshima, and M. Takada, "A BIST Sheme Using Microprogram ROM for Large Capacity Memories," Proc. International Test Conference, pp 815-822, 1990. [10] I. Schanstra, D. Lukita, A. J. Van de Goor, K. Veelenturf, and P. j. van Wijnen, "Semiconductor Manufacturing Process Monitoring Using BIST for Embedded Memories," Proc. International Test Conference, pp 872-881, 1998. [11] K. Zarrineh, S.J Upadhyaya, "On programmable memory built-in self test architectures," Design, Automation and Test in Europe Conference, pp 708-713, 1999 [12] P. H. Bardell, "Analysis of Celluar Automata Used as Pseudorandom Pattern Generators," Proceedings of International Test Conference, 1990, pp. 762-768 [13] K. Cattell, S. Zhang, M. Serra, and J, C. Muzio, "2-by-n Hybrid Cellular Automata with Regular Configuration : Theory and Application," IEEE Trans. on Computers, vol. 48, Mar. 1999, pp. 285-295.