Digital Driving Method for Low Frame Frequency and 256 Gray Scales in Liquid Crystal on Silicon Panels

JOURNAL OF DISPLAY TECHNOLOGY, VOL. 8, NO. 12, DECEMBER 2012 723 Digital Driving Method for Low Frame Frequency and 256 Gray Scales in Liquid Crystal on Silicon Panels Jin-Seong Kang, Student Member, IEEE, and Oh-Kyong Kwon, Member, IEEE Abstract A liquid crystal on silicon (LCoS) panel for projector applications is developed using a new digital driving method to increase the gray scale of the projected image without increasing the driving frequency. The LCoS panel, which has a wide video graphics array (WVGA) resolution, is fabricated using 0.18 m CMOS process technology with an area of 9600 m 5800 m. The projection system is successfully demonstrated using the fabricated LCoS panel and the proposed digital driving method. The measured results of the projection system show that the proposed driving method achieves an 8-bit gray scale at a driving frequency of 75.6 MHz, which is less than 13.7% of the frequency in previously reported methods such as frame rate control and pulse width modulation. Index Terms Digital driving method, liquid crystal on silicon (LCoS), projector, SRAM type pixel. I. INTRODUCTION R ECENTLY, the development of new light sources, such as light-emitting diode (LED) and laser diode (LD), makes the development of a beam projector for mobile applications, referred to as a pico-projector, possible [1]. Pico-projectors are classified according to the display device in the projector such as digital light processing (DLP) [2], high temperature poly-crystalline silicon (HTPS) liquid crystal display (LCD) [3], liquid crystal on silicon (LCoS) [4], and spatial optical modulator (SOM) [5]. DLP using micro-electromechanical systems (MEMS) technology produces a high quality image due to the high light efficiency and fast response time. However, DLP has two serious issues. First, the mechanical motion of the MEMS in a DLP is easily interrupted by external shock. Second, the DLP fabrication process is expensive because of the complex fabrication processes of MEMS devices. The production process of HTPS LCDs is cheaper than that of DLP. However, as the pixel size in an HTPS LCD decreases, the aperture ratio is dramatically reduced because the transparent area is blocked by a poly-crystalline silicon thin-film transistor and storage capacitor. The decrement of the aperture ratio increases the screen Manuscript received August 03, 2012; revised August 30, 2012; accepted September 18, 2012. Date of publication November 16, 2012; date of current version November 20, 2012. The authors are with the Division of Electrical and Computer Engineering, Hanyang University, Seongdong-gu, Seoul, 133-791, Korea (e-mail: watersw@hanyang.ac.kr1; okwon@hanyang.ac.kr). Digital Object Identifier 10.1109/JDT.2012.2220335 door effect [6] which causes visual artifacts in the projected image. LCoS using a single crystalline silicon wafer has advantages over both DLP and HTPS LCD technologies including high image quality and low cost [7]. LCoS devices have been integrated in consumer products for many years, primarily in largesized beam projectors [8]. A pico-projector embedded in mobile devices uses only a single panel unlike a large projector which uses three panels, one each for red, green, and blue. A single-panel full color projector uses a field sequential color (FSC) driving method [9], [10]. However, the analog driving method used in a large projector is not suitable for use with the FSC method, which requires a short image refresh time for the prevention of color break-up [11] and flicker. Additionally, the pixel size of a pico-projector should be small. An analog driving method has a long programming time and large pixel size due to the high voltage devices used for the analog switches [10], [12]. In order to overcome these drawbacks, many studies concerning digital driving methods such as frame rate control (FRC) and pulse width modulation (PWM) have been conducted for the FSC method [13]. However, FRC and PWM have the drawback of a high speed driving frequency. The driving frequency of FRC and PWM doubles for every 1-bit increment in the amount of image data. Therefore, we propose a new digital driving method for a high gray scale pico-projection LCoS display without increasing the driving frequency. In the following section, we discuss the conventional and proposed digital driving methods. Section III describes the architecture and operating principle of the LCoS panel. The experimental results of the LCoS projection system are analyzed in Section IV. Finally, we conclude this paper in Section V. II. DIGITAL DRIVING METHODS A. Problems With Previous Digital Driving Methods In order to generate a gray scale in a digital driving method, in which a pixel can be expressed as either white or black, FRC and PWM have been proposed as temporal dithering methods [14], [15]. The FRC method divides a frame into several sub-frames with an equal timing period and expresses the gray scale by controlling the white and black values in each sub-frame. Fig. 1(a) and (b) shows the timing diagrams of the FRC method when the gray scale is 5 and 8 bit, respectively. To produce an N-bit gray scale, the FRC method requires sub-frames. Then, one sub-frame time of the 8-bit gray scale is 1551-319X/$31.00 2012 IEEE

724 JOURNAL OF DISPLAY TECHNOLOGY, VOL. 8, NO. 12, DECEMBER 2012 Fig. 1. Timing diagrams of the digital driving method using FRC with: (a) 5-bit gray scale and (b) 8-bit gray scale. Fig. 2. Timing diagrams of a digital driving method using PWM with: (a) 5-bit gray scale and (b) 8-bit gray scale. reduced to one-eighth of that of the 5-bit gray scale, as shown in Fig. 1. The PWM method divides a frame into binary weighted subframes. The number of sub-frames using the PWM method is smaller than that of the FRC method with the same gray scale. Fig. 2(a) and (b) shows the timing diagrams of the PWM method when the gray scale is 5 and 8 bit, respectively. However, the PWM method requires the same operating frequency as the FRC method because the shortest addressing time is limited by the sub-frame of the least significant bit (LSB). The driving frequency using the PWM method also doubles for every 1-bit increment of the amount of image data. In addition, the PWM method has dynamic false contours that appear on a moving image which become significant when the moving speed of the object in the image increases or when the light emission period of a pixel increases [16]. For example, when the gray level of the image changes from 127 to 128 in an 8-bit video image, the human eye perceives an incorrect gray level of 255. The dynamic false contour can be reduced by applying FRC to some of the upper bits. Fig. 3. Timing diagrams of a single frame time and an enlarged diagram of the period from the 31st sub-frame to the final sub-frame of the proposed digital driving method with: (a) 6-bit gray scale; b) 7-bit gray scale; and (c) 8-bit gray scale. B. Proposed Digital Driving Method Fig. 3(a) (c) shows timing diagrams of the proposed digital driving method with 6-, 7-, and 8-bit gray scales, respectively. To increase a 1-bit gray scale, only one sub-frame is added and the reset signal starts scanning at the halfway point of the subframe time. Because a pixel is black when the reset is high, the effective luminance time of the 32nd sub-frame is reduced by one-half of the sub-frame time.

KANG AND KWON: DIGITAL DRIVING METHOD FOR LCoS PANELS 725 Fig. 4. Block diagram of the proposed LCoS panel. To increase the gray scale by 2-bit using the proposed method, 2 sub-frames were added, as shown in Fig. 3(b). To achieve a luminance time that is one-quarter of the 33rd sub-frame time, the reset signal starts scanning at the quarter-way point of the subframe time. In the same way, the proposed method achieves an 8-bit gray scale using only 34 sub-frames, as shown in Fig. 3(c). In the fabricated LCoS panel, the single frame time for each color is 2 ms when the frame frequency is 360 Hz and the light-off time between sequential colors is 0.7 ms. The one subframetimeis7.84 s with an 8-bit gray scale using the conventional FRC method, which requires 255 sub-frames. Therefore, the one line time is 16.3 ns as a result of 480 scan lines and the clock frequency for the data driver is 552 MHz because the data driver needs 9 clocks to shift the data in one line time, as showninsectioniii.however,byapplyingtheproposeddigital driving method, the one sub-frame time is 57.1 sforan 8-bit gray scale because the proposed method requires only 35 sub-frames. Therefore, the one line time is 119 ns and clock frequency for the data driver is 75.6 MHz for an 8-bit gray scale. Additionally, the proposed method requires only 13% of the data required with an 8-bit FRC because the amount of data is directly proportional to the number of sub-frames in the digital driving method. Also, the proposed method can be applied to the PWM driving method in which a few sub-frames are increased for the LSB. III. LCOS PANEL IMPLEMENTATIONS Fig. 4 shows the block diagram of the proposed LCoS panel. The proposed panel is composed of a LVDS receiver, a gate driver, data drivers for the even and odd channels, a reset driver, and a pixel array. The LVDS receiver is a serial-to-parallel converter, which creates an internal clock (CLK), 48-bit data, and control signals such as gate data, reset start, mask, and load signals. The data driver is divided into driving blocks for even and odd channels of the pixel array. The gate driver generates gate scanning signals using a shift register and a gate start signal. The reset driver generates reset signals using a shift register and a reset start signal. The conventional LCoS panel using the FRC or PWM method is composed of an interface circuit,adatadriver,agate driver, and a pixel array. To implement the proposed method, we added the reset driver to control the luminance time with a reset switch, SW2, as shown in Fig. 8. This driving method is the first reported method with a relatively low driving frequency. A. LVDS Receiver In the proposed LCoS panel, the speed of the data transmission between the driving board and the panel should be 4.84 Gbps to transfer video data because the frame frequency, the number of sub-frames in a single frame, and resolution format are 360 Hz, 35, and WVGA (800 480), respectively. Moreover, the LCoS panel requires a compact form factor. Therefore, LVDS is an effective method for reducing the number of pads in the compact LCoS panel. Therefore, we adopted an 8-pair LVDS interface for the high speed data transmission and each LVDS interface has a data transmission speed of 605 Mbps between the driving board and panel.

726 JOURNAL OF DISPLAY TECHNOLOGY, VOL. 8, NO. 12, DECEMBER 2012 Fig. 7. Block diagram of the gate driver. Fig. 5. Data mapping of the LVDS interface. Fig. 8. Schematic diagram of a pixel circuit. Fig. 6. Block diagram of the data driver. Because there is no standard mapping at the LVDS interface for pico-projectors, we designed the data mapping shown in Fig. 5. We used eight pairs, Ch0 Ch7, for the video image data, one pair for the clock signal, and one pair for the control signal. B. Data Driver As shown in Fig. 4, the data driver is divided into two parts in order to make effective usage of the panel area. The one part drives the odd channels and the other part drives the even channels. Each data driver is composed of a 24 bits register with 18 stages for shifting operation, a 24 bits register with 18 stages for the holding operation, level shifters, and output buffers, as shown in Fig. 6. The shift register operates every rising and falling edge of the CLK with a frequency of 75.6 MHz. The holding registers store data of the shift register according to the load signal. C. Gate Driver and Reset Driver Fig. 7 shows the block diagram of the gate driver or reset driver that is composed of a shift register, a mask circuit, a level shifter, and an output buffer. The difference between the gate driver and reset driver is the start signal in which the gate driver uses a gate start and the reset driver uses a reset start. The load that is used for holding the register in the data driver is used as the clock signal for the shift register in the gate driver. The mask circuit makes a non-overlapped signal between the output signals using the mask signal. The start signal for the gate driver is enabled when every sub-frame begins and the start signal for the reset driver is enabled at one-half of the 32th sub-frame time, one-fourth of the 33th sub-frame, and one-eighth of the 34th sub-frame. The proposed digital driving method controls the effective emission time using the reset signals with the same frequency of the gate driver such that the proposed LCoS does not increase the driving frequency even though the gray scale increases. D. Pixel Array Fig. 8 shows the schematic diagram of a unit pixel circuit composed of a latch and switches. When the gate signal is high, a datum is programmed to the latch in pixels. The latch stores the programmed datum when the gate signal is low. The operation to reset the signal is analogous to the operation of the gate signal except for the mirror voltage,. When the reset signal becomes high, becomes, resulting in a black projected image.

KANG AND KWON: DIGITAL DRIVING METHOD FOR LCoS PANELS 727 Fig. 10. Measured response time of LC. Fig. 9. (a) Block diagram of the panel and driving board. (b) Photographs of the panel and driving board. (c) Demonstration of the proposed LCoS panel. IV. EXPERIMENTAL RESULTS AND DISCUSSIONS Fig. 9(a) shows the block diagram of the panel and driving board using the proposed method. The video processor in Fig. 9(a) receives video image data of various formats and changes the received image data to the image data with a digital RGB format and WVGA resolution. SDRAM is used to store the frame image data to implement the FSC method. The display controller plays a role in the data rearranger, memory controller, input output interface, LED controller, and timing generator. Fig. 9(b) shows a photograph of the LCoS panel and the driving board. The panel was fabricated with 0.18 mcmos process technology with dimensions of 9600 m 5800 m. The driving board consists of a video processor, a display controller, and SDRAM. Fig. 9(c) shows a demonstration of the proposed LCoS panel. The performance of the fabricated LCoS panel was evaluated by measuring the luminance in a dark room. Fig. 10 shows the response characteristics of LC when LCoS displays a green image. In Fig. 10, Line 1 is the signal indicating a frame time and Line 2 is the voltage converted from the luminance of LCoS by illuminance meter. In the measurement system, the addressing time of LCoS and converting delay of illuminance meter is 200 sand100, respectively. As the measured results show, the rising time and falling time of LC is 2.0 ms and 2.3 ms, respectively. Considering the addressing time and converting delay, the effective rising time and falling time of LC is 1.8 and 2.1 ms, respectively. Response time, which is the sum of the rising time and falling time, is 3.9 ms. The response time should be smaller than single frame time for each color to prevent color break up. We are studying to reduce the response time by controlling cell gap, driving voltage and pretilt angle. Fig. 11(a) (c) shows the measurement results of the normalized luminance with 5-, 6-, and 8-bit gray scale systems, respectively. Fig. 11(a) shows the results of the conventional FRC method, and Fig. 11(b) and (c) shows the results of the proposed digital driving method. In Fig. 11(a), the maximum errors of the integral nonlinearity (INL) and the differential nonlinearity (DNL) are 4.8 LSB and 2.4 LSB with the 5-bit gray scale, respectively. In Fig. 11(b), the maximum errors of the INL and DNL are 8.86 LSB and 2.5 LSB with the 6-bit gray scale, respectively. In Fig. 11(c), the maximum errors of the INL and DNL are 24.33 LSB and 3.8 LSB with the 8-bit gray scale, respectively. The proposed digital driving method increases the gray scale using interpolation of the gray levels of the 5-bit FRC method. Therefore, the measured luminance results using the proposed method in Fig. 11(b) and (c) show similar results to those shown in Fig. 11(a). The INL maximum error increases as the number of the gray scale increases due to the 1 LSB reduction in the step size. The DNL maximum error increment is smaller than that of the INL because interpolation is used for the gray scale extension. Generally, a thermometer-coded FRC has good gray scale results which are inherently monotonic and independent from the LC response time. However, it is difficult to make an IC with the present CMOS technology because FRC requires a very high data rate [17]. PWM is the most widely used form of the digital driving method. However, the finite response time of LC produces a serious non-monotonic problem at a certain number of gray levels [17]. This error depends on how many sets of rising and falling edges are in a sub-frame. The proposed digital driving method with an 8-bit gray scale divides digital data into two parts. One part consists of upper 5-bit data which changes the thermometer code and drives the

728 JOURNAL OF DISPLAY TECHNOLOGY, VOL. 8, NO. 12, DECEMBER 2012 Fig. 12. Simulated reflectance index of LC. Fig. 13. Projected images using the proposed LCoS panel. Fig. 11. Normalized luminance results with: (a) 5-bit gray scale; (b) 6-bit gray scale; and (c) 8-bit gray scale. FRC and the other is driven by the pseudo PWM. The sub-frame time using the proposed pseudo PWM has the same time of the sub-frame of the 5-bit FRC, but the effective emission time is controlled by the reset signal. Therefore, the proposed digital driving method can express the 8-bit gray scale without a nonmonotonic gray scale, as shown in Fig. 11. Fig. 12 shows simulated reflectance index of LC according to the wavelength. As shown in Fig. 12, reflectance index of LC has nonlinear characteristics such as threshold voltage and saturation characteristics. Reflectance value is determined by root mean square (RMS) voltage between two electrodes of LC in digital driving method and is proportional to luminescence of LCoS. To linearize relation between voltage and luminescence as much as possible, we use RMS voltage between two electrodes of LC from 2 V to 6 V. Fig. 13 shows projected images using the proposed digital driving method. V. CONCLUSION We propose a new digital driving method for a pico-projector using LCoS. The proposed LCoS panel with an 8-bit gray scale and WVGA resolution was fabricated using 0.18 mcmos process technology. The proposed digital driving method increases the gray scale of a projected image without an increase of the operational frequency. The projection system was successfully demonstrated using the fabricated LCoS panel with the proposed digital driving method. The measured results of the projection system show that the proposed driving method achieves an 8-bit gray scale at a driving frequency of 75.6 MHz,

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ISCE 97, Dec. 1997, pp. 55 58. [15] S. G. Narasimhan, S. J. Koppal, and S. Yamazaki, Temporal dithering of illumination for fast active vision, in Eur. Conf. Comput. Vision, Oct. 2008, vol. 4, pp. 830 844. [16] T. Yamaguchi, T. Masuda, A. Kohgami, and S. Mikoshiba, Degradation of moving-image quality in PDPS: Dynamic false contours, J. Soc. Inf. Display, vol. 4, pp. 263 270, Dec. 1996. [17] K. Guttag, Digital microdisplay backplane with bit serial SIMD processing, in Proc. Int. Display Workshops, Dec. 2004, pp. 1655 1658. Jin-Seong Kang (S 11) received the B.S. and M.S. degrees in electrical and computer engineering from HanyangUniversity,Seoul,Korea,in2004andin 2006, respectively, and is currently working toward the Ph. D. degree at the same university. His research interests include driving methods and driving circuits for flat panel displays. Mr. Kang was awarded the Silkroad Award from the International Solid State Circuits Conference in 2006. Oh-Kyong Kwon (S 83 M 88) received the B.S. degree in electronic engineering from Hanyang University, Seoul, Korea, in 1978, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Palo Alto, CA, in 1986 and 1988, respectively. From 1987 to 1992, he was with the Semiconductor Process and Design Center, Texas Instruments Inc., Dallas, TX, where he was engaged in the development of multi-chip module (MCM) technologies and smart power integrated circuit technologies for automotive and flat panel display applications. In 1992, he joined Hanyang University, Seoul, Korea, as an assistant professor in the Department of Electronic Engineering and is now a professor in the Division of Electrical and Computer Engineering at Hanyang University. Since 2011, he has served as the Provost and the Senior Vice-President of Hanyang University. His research interests include interconnect and electrical noise modeling for high-speed system-level integration, wafer-scale chip-size packages, smart power integrated circuit technologies, mixed mode signal circuit design, imager, analog front-end circuit design for bio-medical instruments, and the driving methods and circuits for flat panel displays. He has authored and co-authored over 263 international journal and conference papers in addition to 106 U.S. patents.