ROEVER COLLEGE OF ENGINEERING & TECHNOLOGY ELAMBALUR, PERAMBALUR-621220 DEPARTMENT OF ELECTRICAL AND ELECTRONICS ENGINEERING DIGITAL LOGIC CIRCUITS UNIT-1 BOOLEAN ALGEBRA AND COMBINATIONAL CIRCUITS 1. Construct OR gate using only NAND gates? 2. Define multiplexer? 3. State De Morgan s theorems 4. Implement half adder using Gates 5. Draw the Truth table and logic circuit of half adder 6. What is priority encoder? 7. What is the difference between half adder and full adder? 8. Write down the truth table of a full subtractor 9. What is prime implicant? 10. Distinguish between a decoder and Demux. 1. Design a BCD to excess 3 code converter using minimum number of NAND gates. 2. Simplify the following using tabulation method Y(w,x,y,z) = m(1,2,3,5,9,12,14,15) + d (4,8,11) 3. (i) Implement the following Boolean function using 8:1 mux a. F(A,B,C,D) = A B D + A C D + B C D + A C D b. (ii)design a decimal adder to add two decimal digits c. (i)prove that F=A.B+A.B is exclusiveor operation and it equals (A.B).A.(A.B).B d. (ii)prove that for constructing XOR from NANDs we need four NAND gates. 4. Simplify the Boolean function using Kmap F(w,x,y,z)=Σ(1,3,7,11,15) which has the don t care conditions d(w,x,y,z)=σ(0,2,5). UNIT II SYNCHRONOUS SEQUENTIAL CIRCUITS 1. Draw truth table for JK flip flop. 2. How many flip flops are required to design mod 25 counter? 3. What is race around condition in Flipflops? 4. Convert SR flipflop to D flipflop. 5. What is the Difference between a Mealy machine and a Moore machine? 6. Give the characteristic equation and state diagram of JK flipflop. 7. Give the characteristic equation and state diagram of SR flipflop. 8. What is lockout? How it is avoided? 9. What are synchronous sequential circuits? 10. What is a state?
1. Derive the state table and state diagram for the sequential circuit shown in Figure. 2. Design a synchronous sequential circuit whose state diagram is shown in Figure 13. The type of flip-flop to be use is J-K. 3. Design a counter specified by the state diagram using T flip-flops.
4. (i)realize SR flip-flop using NOR gates and explain its operation. (8) (ii) Convert a SR flip-flop into JK flip-flop. (8) 5. Design a BCD Up / Down counter using S R flip-flops. 6. Explain the working of JK flip- flop. What is race around condition? How is it overcome? Explain these concepts with relevant timing diagrams. UNIT III ASYNCHRONOUS SEQUENCTIAL CIRCUIT 1. What is the difference between flow table and transition table? 2. Sketch the block diagram of an Asynchronous sequential circuit. 3. Distinguish between Fundamental mode and Pulse mode operation of asynchronous sequential circuit 4. What is the difference between Asynchronous and synchronous sequential circuits 5. What is critical race? 6. State the hazards in Asynchronous sequential circuits 7. What is ASM chart? 8. What do you understand by the term merging? 9. What is the need of state reduction in sequential circuit design? 10. What is State Assignment? 11. Design a gated latch circuit with two inputs, G (gate) and D (data), and one output Q. The gated latch is a memory element that accepts the value of D when G = 1 and retains this value after G goes to 0. Once G = 0, a change in D does not change the value of the output Q. 12. (i)explain about Hazards (ii)give hazard free realization for the following Boolean function. F (A, B, C) =m (1, 5, 6, 7) 13. Design an asynchronous sequential logic circuit for state transition diagram shown in figure 14. Consider the following asynchronous sequential circuit and draw maps and transition table, and state table.
15. Design an asynchronous sequential circuit that has two inputs X1 and X1 and one output Z. When X1=0, the output Z is 0. The first change in X2 that occurs while X1 is 1 will cause output Z to be 1. The output Z will remain 1 until X1 returns to 0. 16. Design a pulse mode circuit having two input lines X1 and X2 and one output line Z. The circuit should produce an output pulse to coincide with the last input pulse in the sequencex1, X2, X2. No other input sequence should produce an output pulse. 17. (i)with suitable design example, explain ASM Chart (ii)when do you get the critical and non-critical races? How will you obtain race free conditions? (10) UNIT IV PROGRAMMABLE LOGIC DEVICES, MEMORY AND LOGIC FAMILIES 1. What is the difference between PROM and EPROM? 2. What ar e the advantages of CMOS? 3. What are the advantages of PLAs? 4. List the configurable elements in the FPGA architecture. 5. What is a PLA? 6. Name the types of ROM. 7. Define fan in and fan out characteristics of digital logic families. 8. What is FPGA? 9. Distinguish between PLA and PAL. 10. What is the difference between TTL and ECL? 1. (i)describe CMOS inverter and state advantages of CMOS. (ii)explain the following for an ADC
(i) Input stage. (ii) Resolution. (ii) Accuracy. (iv) Quantization error. 2. (i)what are the characteristics of digital ICs used to compute their performance? (ii)what is the necessity of Interfacing in digital ICs and what are the points to be kept in view, while interfacing between TTL gate and CMOS gate?. 3. Draw the logic diagram of 16-bit ROM Array and explain its principle of operation. 4. What is Tri-state logic and explain Tri-state logic inverter with the help of a circuit diagram.give its Truth Table. 5. (i)a combinational logic circuit is defined by the following function. f1(a,b,c) = Σ(0, 1, 6, 7), f2(a, b, e) = Σ(2, 3, 5,7)Implement the circuit with a PAL having three inputs, product terms and two outputs. (ii) Describe the concept and working of FPGA. 6. i)implement the following two Boolean function with a PLA F1(A,B,C) =Σ(0,1,2,4), F2(A,B,C) = Σ(0,5,6,7) (ii)describe the characteristic of all type of memories UNIT V VHDL 1. Write HDL behavior model of D flipflop. 2. What is the need for VHDL? 3. List the Different types of operators supported by VHDL. 4. What are the various modeling techniques in HDL? 5. Write HDL for half adder. 6. Define testbench. 7. Write a behavioral description of 2 to 1 line multiplexer 8. What is need of subprogram? 9. What are ASM? 10. Write the VHDL code for AND gate 1. (i)write the HDL for two to one line multiplexer with data flow description and behavioral description. (ii)write HDL for four bit adder. 2. (i)construct a VHDL module for a JK flipflop.(8) (ii) Express how arithmetic and logic operations are expressed using RTL.(8) 3. (i)explain the design procedure of RTL using VHDL. (10) (ii)write a note on VHDL test benches. (6) 4. Construct a VHDL module for a 4*4 RAM 5. Expalin the block diagram of a typical processor unit with control signals and Arithmetic unit 6. Write a VHDL code for a mealy machine 7. Construct a VHDL module for a nbit counter