EE26: igital esign, Spring 28 4/8/8 EE 26: Introduction to igital esign ounters and Registers Yao Zheng epartment of Electrical Engineering University of Hawaiʻi at Mānoa Agenda ounters Introduction: ounters Asynchronous (Ripple) ounters Asynchronous ounters with MO number < 2 n Asynchronous own ounters ascading Asynchronous ounters Synchronous (Parallel) ounters Up/own Synchronous ounters esigning Synchronous ounters ecoding A ounter ounters with Parallel Load Registers Introduction: Registers v Simple Registers v Registers with Parallel Load Using Registers to implement Sequential ircuits Shift Registers v Serial In/Serial Out Shift Registers v Serial In/Parallel Out Shift Registers v Parallel In/Serial Out Shift Registers v Parallel In/Parallel Out Shift Registers idirectional Shift Registers An Application Serial Addition Shift Register ounters v Ring ounters v ohnson ounters Random-Access Memory (RAM) Agenda Introduction: ounters ounters are circuits that cycle through a specified number of states. Two types of counters: v synchronous (parallel) counters v asynchronous (ripple) counters Ripple counters allow some flip-flop outputs to be used as a source of clock for other flipflops. Synchronous counters apply the same clock to all flip-flops. Asynchronous (Ripple) ounters Asynchronous counters: the flip-flops do not change states at exactly the same time as they do not have a common clock pulse. Also known as ripple counters, as the input clock pulse ripples through the counter cumulative delay is a drawback. n flip-flops a MO (modulus) 2 n counter. (Note: A MO-x counter cycles through x states.) Output of the last flip-flop (MS) divides the input clock frequency by the MO number of the counter, hence a counter is also a frequency divider. Asynchronous (Ripple) ounters Example: 2-bit ripple binary counter. Output of one flip-flop is connected to the clock input of the next more-significant flip-flop. L L 2 HIGH 3 4 FF FF Timing diagram... hapter : ounters and Registers
EE26: igital esign, Spring 28 4/8/8 Asynchronous (Ripple) ounters Example: 3-bit ripple binary counter. HIGH L FF FF FF2 2 Asynchronous (Ripple) ounters Propagation delays in an asynchronous (ripple-clocked) binary counter. If the accumulated delay is greater than the clock pulse, some counter states may be misrepresented! L 2 3 4 5 6 7 8 L 2 3 4 2 Recycles back to 2 t PLH (L to ) t PHL (L to ) t PLH ( to ) t PHL (L to ) t PHL ( to ) t PLH ( to 2) Asynchronous (Ripple) ounters Example: 4-bit ripple binary counter (negative-edge triggered). HIGH L L 2 3 FF FF FF2 2 FF3 2 3 4 5 6 7 8 9 2 3 4 5 6 3 Asyn. ounters with MO no. < 2 n States may be skipped resulting in a truncated sequence. Technique: force counter to recycle before going through all of the states in the binary sequence. Example: Given the following circuit, determine the counting sequence (and hence the modulus no.) All, inputs are (HIGH). A L LR L LR L LR Asyn. ounters with MO no. < 2 n Example (cont d): All, inputs are (HIGH). A L LR L LR L LR Asyn. ounters with MO no. < 2 n Example (cont d): ounting sequence of circuit (in A order). lock A NAN Output 2 3 4 5 6 7 8 9 2 lock A NAN Output 2 3 4 5 6 7 8 9 2 MO-6 counter produced by clearing (a MO-8 binary counter) when count of six () occurs. Temporary state ounter is a MO-6 counter. hapter : ounters and Registers 2
EE26: igital esign, Spring 28 4/8/8 Asyn. ounters with MO no. < 2 n Exercise: How to construct an asynchronous MO-5 counter? MO-7 counter? MO-2 counter? uestion: The following is a MO-? counter? F LR E LR LR A LR LR LR Asyn. ounters with MO no. < 2 n ecade counters (or counters) are counters with states (modulus-) in their sequence. They are commonly used in daily life (e.g.: utility meters, odometers, etc.). esign an asynchronous decade counter. HIGH A (A.)' E F All = =. L LR LR LR LR Asyn. ounters with MO no. < 2 n Asynchronous decade/ counter (cont d). HIGH A (A.)' L LR LR LR LR Asynchronous own ounters So far we are dealing with up counters. own counters, on the other hand, count downward from a maximum value to zero, and repeat. Example: A 3-bit binary (MO-2 3 ) down counter. lock A NAN output 2 3 4 5 6 7 8 9 L L ' ' ' ' 2 ' 2 ' 3-bit binary up counter 3-bit binary down counter Asynchronous own ounters Example: Ax 3-bit binary (MO-8) down counter. L L ' 2 ' 3 2 ' 4 5 6 2 7 8 ascading Asynchronous ounters Larger asynchronous (ripple) counter can be constructed by cascading smaller ripple counters. onnect last-stage output of one counter to the clock input of next counter so as to achieve highermodulus operation. Example: A modulus-32 ripple counter constructed from a modulus-4 counter and a modulus-8 counter. L ' ' Modulus-4 counter ' 2 ' 3 ' Modulus-8 counter 4 hapter : ounters and Registers 3
EE26: igital esign, Spring 28 4/8/8 ascading Asynchronous ounters Example: A 6-bit binary counter (counts from to 63) constructed from two 3-bit counters. ount pulse A A A 2 A 3 A 4 A 5 3-bit binary counter A5 A4 A3 A2 A A : : : : : : : : : 3-bit binary counter ascading Asynchronous ounters If counter is a not a binary counter, requires additional output. Example: A modulus- counter using two decade counters. freq/ TENecade TENecade counter T counter T L 3 2 3 2 freq T = when counter recycles to freq/ Synchronous (Parallel) ounters Synchronous (parallel) counters: the flip-flops are clocked at the same time by a common clock pulse. We can design these counters using the sequential logic design process (covered in Lecture #2). Example: 2-bit synchronous binary counter (using T flip-flops, or flip-flops with identical, inputs). Synchronous (Parallel) ounters Example: 2-bit synchronous binary counter (using T flip-flops, or flip-flops with identical, inputs). Present Next Flip-flop state state inputs A A A + A + TA TA TA = A TA = Present Next Flip-flop state state inputs A A A + A + TA TA L A ' A ' Synchronous (Parallel) ounters Example: 3-bit synchronous binary counter (using T flip-flops, or flip-flops with identical, inputs). Present Next Flip-flop state state inputs A2 A A A2 + A + A + TA2 TA TA A A A Synchronous (Parallel) ounters Example: 3-bit synchronous binary counter (cont d). TA 2 = A.A TA = A TA = A 2 A A P A2 A2 A2 A TA2 = A.A A A TA = A TA = hapter : ounters and Registers 4
EE26: igital esign, Spring 28 4/8/8 Synchronous (Parallel) ounters Note that in a binary counter, the n th bit (shown underlined) is always complemented whenever or Hence, X n is complemented whenever X n- X n-2... X X =. As a result, if T flip-flops are used, then TX n = X n-. X n-2..... X. X Synchronous (Parallel) ounters Example: 4-bit synchronous binary counter. TA 3 = A 2. A. A TA 2 = A. A TA = A TA = L A ' A ' A.A A2.A.A A 2 ' A 3 ' Synchronous (Parallel) ounters Example: Synchronous decade/ counter. lock pulse 3 2 Initially 2 3 4 5 6 7 8 9 (recycle) T = T = 3 '. T 2 =. T 3 = 2.. + 3. Synchronous (Parallel) ounters Example: Synchronous decade/ counter (cont d). T = T = 3 '. T 2 =. T 3 = 2.. + 3. T ' T ' T 2 T 3 ' ' L Up/own Synchronous ounters Up/down synchronous counter: a bidirectional counter that is capable of counting either up or down. An input (control) line Up/own (or simply Up) specifies the direction of counting. v Up/own = ount upward v Up/own = ount downward Up/own Synchronous ounters Example: A 3-bit up/down synchronous binary counter. lock pulse Up 2 own 2 3 4 5 6 7 T = T = (.Up) + ( '.Up' ) T 2 = (..Up ) + ( '. '. Up' ) Up counter T = T = T 2 =. own counter T = T = T 2 =. hapter : ounters and Registers 5
EE26: igital esign, Spring 28 4/8/8 Up/own Synchronous ounters Example: A 3-bit up/down synchronous binary counter (cont d). T = T = (.Up) + ( '.Up' ) T 2 = (..Up ) + ( '. '. Up' ) Up L T ' T ' T ' 2 esigning Synchronous ounters overed in Lecture #2. Example: A 3-bit Gray code counter (using flip-flops). Present Next Flip-flop state state inputs 2 2 + + + 2 2 X X X X X X X X X X X X X X X X X X X X X X X X esigning Synchronous ounters 3-bit Gray code counter: flip-flop inputs. 2 X X X X 2 =. ' 2 X X X X 2 = '. ' 2 X X X X = 2 '. 2 X X X X = 2. 2 X X X X = 2. + 2 '. ' = ( 2 Å )' 2 X X X X = 2. ' + 2 '. = 2 Å esigning Synchronous ounters 3-bit Gray code counter: logic diagram. L 2 =. ' = 2'. = ( 2 Å )' 2 = '. ' = 2. = 2 Å ' ' ' ' ' 2 2 ' ecoding A ounter ecoding a counter involves determining which state in the sequence the counter is in. ifferentiate between active-high and active-low decoding. Active-HIGH decoding: output HIGH if the counter is in the state concerned. Active-LOW decoding: output LOW if the counter is in the state concerned. ecoding A ounter Example: MO-8 ripple counter (active-high decoding). ' ' ' ' A lock 2 3 4 5 6 7 8 9. HIGH only on count of A = HIGH only on count of A = HIGH only on count of A = HIGH only on count of A = hapter : ounters and Registers 6
EE26: igital esign, Spring 28 4/8/8 ecoding A ounter Example: To detect that a MO-8 counter is in state () or state (). ' ' ' ' lock 2 3 4 5 6 7 8 9 HIGH only on count of A = or A = Example: To detect that a MO-8 counter is in the odd states (states, 3, 5 or 7), simply use. lock 2 3 4 5 6 7 8 9 HIGH only on count of odd states ounters with Parallel Load ounters could be augmented with parallel load capability for the following purposes: vto start at a different state vto count a different sequence vas more sophisticated register with increment/decrement functionality. ounters with Parallel Load ifferent ways of getting a MO-6 counter: A 4 A 3 A 2 A A 4 A 3 A 2 A ounters with Parallel Load 4-bit counter with parallel load. Load Inputs = I 4 I 3 I 2 I ount = lear = P (a) inary states,,2,3,4,5. lear I 4 I 3 I 2 I ount = Load = P Inputs have no effect (b) inary states,,2,3,4,5. lear P Load ount Function X X X lear to X No change X Load inputs Next state A 4 A 3 A 2 A A 4 A 3 A 2 A arry-out Load I 4 I 3 I 2 I ount = lear = P Load I 4 I 3 I 2 I ount = lear = P (c) inary states,,2,3,4,5. (d) inary states 3,4,5,6,7,8. Introduction: Registers An n-bit register has a group of n flip-flops and some logic gates and is capable of storing n bits of information. The flip-flops store the information while the gates control when and how new information is transferred into the register. Some functions of register: v retrieve data from register v store/load new data into register (serial or parallel) v shift the data within register (left or right) Simple Registers No external gates. Example: A 4-bit register. A new 4-bit data is loaded every clock cycle. P A 3 A 2 A A I 3 I 2 I I hapter : ounters and Registers 7
EE26: igital esign, Spring 28 4/8/8 Registers With Parallel Load Instead of loading the register at every clock pulse, we may want to control when to load. Loading a register: transfer new information into the register. Requires a load control input. Parallel loading: all bits are loaded simultaneously. Registers With Parallel Load Load'.A + Load. I Load A I A I A 2 I 2 A 3 I 3 L LEAR Using Registers to implement Sequential ircuits A sequential circuit may consist of a register (memory) and a combinational circuit. lock Register Inputs Next-state value ombinational circuit Outputs The external inputs and present states of the register determine the next states of the register and the external outputs, through the combinational circuit. The combinational circuit may be implemented by any of the methods covered in MSI components and Programmable Logic evices. Using Registers to implement Sequential ircuits Example : A + = S m(4,6) = A.x' A 2+ = S m(,2,5,6) = A 2.x' + A 2 '.x = A 2 Å x y = S m(3,7) = A 2.x Present Next state Input State Output A A2 x A + A2 + y A.x' A 2 Åx x A A 2 y Using Registers to implement Sequential ircuits Example 2: Repeat example, but use a ROM. Address Outputs 2 3 2 3 ROM truth table x A A 2 8 x 3 ROM y Shift Registers Another function of a register, besides storage, is to provide for data movements. Each stage (flip-flop) in a shift register represents one bit of storage, and the shifting capability of a register permits the movement of data from stage to stage within the register, or into or out of the register upon application of clock pulses. hapter : ounters and Registers 8
EE26: igital esign, Spring 28 4/8/8 Shift Registers asic data movement in shift registers (four bits are used for illustration). ata in ata out (a) Serial in/shift right/serial out ata in ata in ata out ata in (b) Serial in/shift left/serial out ata in Serial In/Serial Out Shift Registers Accepts data serially one bit at a time and also produces output serially. Serial data input 2 3 Serial data output ata out (c) Parallel in/serial out ata out (d) Serial in/parallel out ata out (e) Parallel in / parallel out L (f) Rotate right (g) Rotate left Serial In/Serial Out Shift Registers Application: Serial transfer of data from one register to another. lock Shift control lock SI Shift register A P SO SI Shift register SO Serial In/Serial Out Shift Registers Serial-transfer example. Timing Pulse Shift register A Shift register Serial output of Initial value After T After T2 After T3 After T4 Shift control P Wordtime T T 2 T 3 T 4 Serial In/Parallel Out Shift Registers Accepts data serially. Outputs of all stages are available simultaneously. Parallel In/Serial Out Shift Registers its are entered simultaneously, but output is serial. ata input ata input SHIFT/LOA 2 3 L 2 3 ata input L SRG 4 Logic symbol Serial data 2 3 out 2 3 L SHIFT. + SHIFT'. hapter : ounters and Registers 9
EE26: igital esign, Spring 28 4/8/8 Parallel In/Serial Out Shift Registers its are entered simultaneously, but output is serial. ata in Parallel In/Parallel Out Shift Registers Simultaneous input and output of all data bits. Parallel data inputs 2 3 2 3 SHIFT/LOA L SRG 4 Serial data out Logic symbol L 2 3 Parallel data outputs idirectional Shift Registers ata can be shifted either left or right, using a control line RIGHT/LEFT (or simply RIGHT) to indicate the direction. idirectional Shift Registers 4-bit bidirectional shift register with parallel load. Parallel outputs A 4 A 3 A 2 A RIGHT/LEFT lear Serial data in L RIGHT. + RIGHT'. 2 L 2 3 s 4x s MUX 3 2 Serial input for shift-right 4x MUX 3 2 4x MUX 3 2 I 4 I 3 I 2 I 4x MUX 3 2 Serial input for shift-left Parallel inputs idirectional Shift Registers 4-bit bidirectional shift register with parallel load. Mode ontrol s s Register Operation No change Shift right Shift left Parallel load An Application Serial Addition Most operations in digital computers are done in parallel. Serial operations are slower but require less equipment. A serial adder is shown below. A A +. Shift-right P External input SI SI Shift-register A Shift-register SO SO x y FA S z lear hapter : ounters and Registers
EE26: igital esign, Spring 28 4/8/8 An Application Serial Addition A = ; =. A + = is stored in A after 4 clock pulses. Initial: A: : Step : + + S =, = Step 2: + + S =, = Step 3: + + S =, = A: : x A: : x x A: : x x x : : : : Shift Register ounters Shift register counter: a shift register with the serial output connected back to the serial input. They are classified as counters because they give a specified sequence of states. Two common types: the ohnson counter and the Ring counter. Step 4: + + S =, = A: : x x x x : Ring ounters One flip-flop (stage) for each state in the sequence. The output of the last stage is connected to the input of the first stage. An n-bit ring counter cycles through n states. No decoding gates are required, as there is an output that corresponds to every state the counter is in. Ring ounters Example: A 6-bit (MO-6) ring counter. PRE LR L 2 3 4 5 lock 2 3 4 5 2 3 4 5 ohnson ounters The complement of the output of the last stage is connected back to the input of the first stage. Also called the twisted-ring counter. Require fewer flip-flops than ring counters but more flip-flops than binary counters. An n-bit ohnson counter cycles through 2n states. Require more decoding circuitry than ring counter but less than binary counters. ohnson ounters Example: A 4-bit (MO-8) ohnson counter. LR L lock 2 3 2 3 4 5 6 7 2 ' 3' hapter : ounters and Registers
EE26: igital esign, Spring 28 4/8/8 ohnson ounters ecoding logic for a 4-bit ohnson counter. lock A ecoding.' A.' 2.' 3.' 4 A. 5. 6 '. 7 '. ' ' State 6 State 7 ' A ' ' ' A State State State 2 State 3 State 4 State 5 A memory unit stores binary information in groups of bits called words. The data consists of n lines (for n-bit words). ata input lines provide the information to be stored (written) into the memory, while data output lines carry the information out (read) from the memory. The address consists of k lines which specify which word (among the 2 k words available) to be selected for reading or writing. The control lines Read and Write (usually combined into a single control line Read/Write) specifies the direction of transfer of the data. lock diagram of a memory unit: ontent of a 24 x 6-bit memory: n data input lines n Memory address binary decimal Memory content k address lines Read/Write k Memory unit 2 k words n bits per word n n data output lines : : 2 : : 2 22 23 : : The Write operation: v Transfers the address of the desired word to the address lines v Transfers the data bits (the word) to be stored in memory to the data input lines v Activates the Write control line (set Read/Write to ) The Read operation: v Transfers the address of the desired word to the address lines v Activates the Read control line (set Read/Write to ) The Read/Write operation: Memory Enable Read/Write Memory Operation X None Write to selected word Read from selected word Two types of RAM: Static and dynamic. Static RAMs use flip-flops as the memory cells. ynamic RAMs use capacitor charges to represent data. Though simpler in circuitry, they have to be constantly refreshed. hapter : ounters and Registers 2
EE26: igital esign, Spring 28 4/8/8 A single memory cell of the static RAM has the following logic and block diagrams. Logic construction of a 4 x 3 RAM (with decoder and OR gates): Select R Select Input S Output Input Output Read/Write Logic diagram Read/Write lock diagram An array of RAM chips: memory chips are combined to form larger memory. A x 8-bit RAM chip: Input data Address hip select Read/write RAM x 8 8 ATA (8) 8 (8) Output data ARS () S RW lock diagram of a x 8 RAM chip Lines Read/write Address 2x4 decoder S S 4 x 8 RAM. Lines 9 2 3 Input data 8 lines 23 ATA (8) (8) ARS () S x 8 RW 24 247 ATA (8) (8) ARS () S x 8 RW 248 37 ATA (8) (8) ARS () S x 8 RW 372 495 ATA (8) (8) ARS () S x 8 RW Output data hapter : ounters and Registers 3