April 2013 Introduction Reference esign R1162 Low Voltage ifferential Signaling (LVS) is an electrical signaling system that can run at very high speeds over inexpensive twisted-pair copper cables. It delivers high data rates while consuming significantly less power than competing technologies. Since its introduction, it has become popular in very high speed networks and computer buses. Source synchronous interfaces consisting of multiple data bits and clocks have become a common method for moving image data within electronic systems. A prevalent standard is the 7:1 LVS interface (employed in Channel Link, Flat Link, and Camera Link), which has become a common standard in many electronic products including consumer devices, industrial control, medical, and automotive telematics. In many of these applications, the practice of using low-cost FPGAs for image processing has become quite common. This document provides a brief description of an LVS Transmitter and its implementation. The design is implemented in VHL. The Lattice icecube2 Place and Route tool integrated with the Synopsys Synplify Pro synthesis tool is used for the implementation of the design. The design can be targeted to other ice40 FPGA product family devices. Figure 1 shows the System Block iagram for the LVS Transmitter. Features LVS Signaling on Flip Flops Configurable LVS data channels (1 to 4) Verilog RTL, testbench and ModelSim script for simulation System Block iagram Figure 1. System Block iagram p[3:0] Application Processor [27:0] ice CM as LVS Transmitter n[3:0] LVS Application o_lvdsclkn 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. www.latticesemi.com 1 rd1162_01.0
Functional Block iagram Figure 2. Functional Block iagram LVS O/P p[3] n[3] [27:0] LVS O/P LVS O/P LVS O/P p[2] n[2] p[1] n[1] p[0] n[0] 3.5x Clock domain LVS O/P o_lvdsclkn The FIFO output data (7-bit each for 4 channels) is fed to four instances of 7:1 serializers. The serializer module serializes the 7-bit parallel data to a single LVS ata bit and transmits this single data channel along with the LVS Clock. Usage of high speed flops as shown in Figure 4, reduces the output clock rate by 50%, that is 3.5 times instead of 7 times the input clock rate. Each 7:1 serializer produces 2 outputs for the LVS output stage. Each LVS output on the ice65 FPGA consists of 2 PIO pins and an external resistor compensation network to generate LVS signals. One output from the serializer (ATA_0) is clocked out on the rising edge of the 3.5x clock while the other output (ATA_180) is clocked out on the falling edge. These 2 PIO pins form a complimentary LVS pair, with one PIO pin (TXOUT_P) generating the non-inverting output while the other pin (TXOUT_N) generating the inverted output of the LVS differential pair. 2
Figure 3. LVS ifferential Pair Using F/Fs Clocked on rising edge ata_0 ata from Serializer MUX Non-Inverted ata PA External resistor network generates LVS electrical signals Rs=150 ohms TXOUT_P ata_180 Clocked on falling edge PIO LVS pair Rs=140 ohms MUX Inverted ata PA Rs=150 ohms TXOUT_N Clock from PLL, multiplied by 3.5x Clock_3P5X PIO 3
Timing iagram Figure 4. Timing iagram Latency=5.5 [27:21] 0 4 8 [20:14] [13:07] 1 2 5 6 9 10 [06:00] 3 7 11 [3] 0 [2] 1 [1] 2 [0] 3 ata from the LVS lines are MSB 4
Simulation Waveforms Figure 5. Simulation Waveforms Signal escription Table 1. Signal escription Signal Width Type escription 1 Input Pixel clock for LVS display 1 Input Active High System Reset i_3p5pllclk 1 Input 3.5x of pixel clock for LVS isplay 28 Input FIFO output data, with the read clock same as SERES lock signal. Only when this signal is high, the 1 Output LVS_Tx module is ready to accept input data 1 Output Read enable signal to FIFO p 4 Output LVS non-inverted data output n 4 Output LVS inverted data output 1 Output LVS non-inverted clock output o_lvdsclkn 1 Output LVS inverted clock output 5
Usage Example Single Channel LVS Tx Figure 6 shows the top level block diagram of an LVS isplay used with the LVS Transmitter. Both the input pixel clock () and 3.5x clock (i_3p5xpllclock) must be generated from the PLL in the ata generator. Figure 6. Top Level iagram of LVS isplay Used with the LVS Transmitter RGB ata and control signal generator PLL [27:0] ice CM as LVS Transmitter Pair3 Pair2 Pair1 Pair0 o_lvdsclkn LVS isplay Figure 7 shows the generation of the control signals HSYNC, VSYNC, EN and 18-bit RGB data to the LVS display. The display resolution in this case is 1024 x 600. The LC control signals are generated based on the predetermined porch timing values of the display. Figure 7. LVS isplay Timing Generation o_lvds_vsync o_lvds_hsync valid_line efault lines=13 Active lines=600 lines Total lines=638 lines o_lvds_hsync o_lvds_pclk o_lvds_red o_lvds_green o_lvds_blue o_lvds_den default=90 Active pixels=1025 Total pixels=2025 6
Configurable parameters NUM_CHANNELS : This parameter configures the number of LVS data channels required. The values can range from 1 to 4 Initialization Condition When '' is HIGH, all the output LVS signals will be low. Operation Sequence 1. e-assert the signal 2. Wait until the signal goes high, indicating that the LVS Tx is ready to accept the input data 3. signal is used to read FIFO 4. Start writing the 28-bit RGB data and control signals as per the LVS LC specifications to the LVS Tx on the positive edge of to the UT as shown in Figure 5. 5. There is a latency of 5.5 cycles of for the first serial data output, and there afterwards the serial data is available in pipelined fashion for the LVS isplay as shown in Figure 5. Implementation This design is implemented in VHL. When using this design in a different device, density, speed or grade, performance and utilization may vary. Table 2. Performance and Resource Utilization Family Language Utilization (LUTs) f MAX (MHz) I/Os Architectural Resources ice40 1 VHL 123 >50 41 (21/160)PLBs 1. Performance and utilization characteristics are generated using ice40lp1k-cm121 with icecube2 design software. References ice40 Family Handbook Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com Revision History ate Version Change Summary April 2013 01.0 Initial release. 7