All Devices Discontinued!

GAL 26V2 Device Datasheet September 200 All Devices Discontinued! Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet The original datasheet pages have not been modified and do not reflect those changes Please refer to the table below for reference PCN and current product status Product Line Ordering Part Number Product Status Reference PCN GAL26V2C-0LP GAL26V2 GAL26V2C-5LP GAL26V2C-20LP GAL26V2C-0LP GAL26V2C-5LP GAL26V2C-20LP GAL26V2C-7LJ Discontinued PCN#06-07 GAL26V2C-0LJ GAL26V2C-5LJ GAL26V2C-20LJ GAL26V2C-0LJ GAL26V2C-5LJ PCN#3-0 GAL26V2C-20LJ 5555 NE Moore Ct Hillsboro, Oregon 9724-642 Phone (503) 26-000 FAX (503) 26-347 nternet: http://wwwlatticesemicom

/ Select devices have been discontinued See Ordering nformation section for product status GAL26V2 High Performance E 2 CMOS PLD Generic Array Logic TM FEATURES HGH PERFORMANCE E 2 CMOS TECHNOLOGY 75 ns Maximum Propagation Delay Fmax = 42 MHz 45 ns Maximum from Clock nput to Data Output TTL Compatible 6 ma Outputs UltraMOS Advanced CMOS Technology LOW POWER CMOS 90 ma Typical cc E 2 CELL TECHNOLOGY Reconfigurable Logic Reprogrammable Cells 00% Tested/Guaranteed 00% Yields High Speed Electrical Erasure (<00ms) 20 Year Data Retention TWELVE OUTPUT LOGC MACROCELLS Maximum Flexibility for Complex Logic Designs PRELOAD AND POWER-ON RESET OF REGSTERS 00% Functional Testability APPLCATONS NCLUDE: DMA Control State Machine Control High Speed Graphics Processing Standard Logic Speed Upgrade ELECTRONC SGNATURE FOR DENTFCATON DESCRPTON The GAL26V2, at 75ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E 2 ) floating gate technology to provide the highest performance available of any 26V2 device on the market E 2 technology offers high speed (<00ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user The GAL26V2 is fully function/fuse map/parametric compatible with other 26V2 devices Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture As a result, LATTCE is able to guarantee 00% field programmability and functionality of all GAL products LATTCE also guarantees 00 erase/rewrite cycles FUNCTONAL BLOCK DAGRAM / PACKAGE DAGRAMS VCC NPUT NPUT NPUT/ 2 NPUT NPUT NPUT NPUT NPUT NPUT NPUT NPUT NPUT 5 7 9 /2 PLCC 4 2 2 26 GAL26V2 Top View PROGRAMMABLE AND-ARRAY (50X52) ALL DEVCES 2 4 6 9 25 23 2 GND PRESET OLMC 0 0 2 4 6 6 4 2 0 RESET OLMC OLMC 2 OLMC 3 OLMC 4 OLMC 5 OLMC 6 OLMC 7 OLMC OLMC 9 OLMC 0 OLMC / /2 Vcc 2 7 DP GAL 26V2 DSCONTNUED 2 4 5 NPUT GND Copyright 2000 Lattice Semiconductor Corp GAL, E 2 CMOS and UltraMOS are registered trademarks of Lattice Semiconductor Corp Generic Array Logic is a trademark of Lattice Semiconductor Corp The specifications herein are subject to change without notice LATTCE SEMCONDUCTOR CORP, 5555 NE Moore Ct, Hillsboro, Oregon 9724 USA November 2000 Tel (503) 26-000 or -00-LATTCE; FAX (503) 26-556

Select devices have been discontinued See Ordering nformation section for product status Specifications GAL26V2 GAL26V2 ORDERNG NFORMATON Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # 75 6 4 5 30 GAL26V2C-7LJ ndustrial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # 0 7 7 50 GAL26V2C-0LP 2-Pin Plastic DP Discontinued per PCN #06-07 Contact Rochester Electronics for available inventory PART NUMBER DESCRPTON GAL26V2C L = Low Power Device Name Speed (ns) Power 50 GAL26V2C-0LJ 2-Lead PLCC 5 0 50 GAL26V2C-5LP 2-Pin Plastic DP 50 GAL26V2C-5LJ 2-Lead PLCC 20 2 2 50 GAL26V2C-20LP 2-Pin Plastic DP 50 GAL26V2C-20LJ 2-Lead PLCC XXXXXXXX _ XX X X X 2-Lead PLCC 0 7 7 30 GAL26V2C-0LP 2-Pin Plastic DP 30 GAL26V2C-0LJ 2-Lead PLCC 5 0 05 GAL26V2C-5LP 2-Pin Plastic DP 05 GAL26V2C-5LJ 2-Lead PLCC 20 2 2 05 GAL26V2C-20LP 2-Pin Plastic DP 05 GAL26V2C-20LJ 2-Lead PLCC Package Package ALL DEVCES Grade Package Blank = Commercial = ndustrial DSCONTNUED P = Plastic DP J = PLCC 2

Select devices have been discontinued See Ordering nformation section for product status Specifications GAL26V2 OUTPUT LOGC MACROCELL (OLMC) The GAL26V2 has a variable number of product terms per OLMC Of the ten available OLMCs, four OLMCs have access to eight product terms (pins 5, 6, 26 and 27), two have ten product terms (pins 7 and 25), two have twelve product terms (pins and 24), two have fourteen product terms (pins 9 and 23), and two OLMCs have sixteen product terms (pins 20 and 22) n addition to the product terms available for logic, each OLMC has an additional product-term dedicated to output enable control / 2 D 2 TO MUX AR SP 4 TO MUX GAL26V2 OUTPUT LOGC MACROCELL (OLMC) OUTPUT LOGC MACROCELL CONFGURATONS Each of the Macrocells of the GAL26V2 has two primary functional modes: registered, and combinatorial /O The modes and the output polarity are set by four architecture bits (S0, S, S2 and S3), which are normally controlled by the logic compiler Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page REGSTERED MODE n registered mode the output pin associated with an individual OLMC is driven by the output of that OLMC s D-type flip-flop Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low) Output tri-state control is available as an individual product-term for each OLMC, and can therefore be defined by a logic equation There are two options for the feedback of the registered mode - - internal / feedback and /O pin feedback The D flip-flop s / output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array Similarly the /O pin feedback with both true and complement input to the AND array The resulting polarity depends on the input polarity selection as well as the registered /O output polarity configuration The output polarity of each OLMC can be individually programmed to be true or inverting, in either combinatorial or registered mode This allows each output to be individually configured as either active high or active low n the registered mode configuration the clock source for the register can be selected The two clock options, and 2, originate from input pin and pin4 respectively The GAL26V2 has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP) These two product terms are common to all registered OLMCs The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted NOTE: The AR and SP product terms will force the output of the flip-flop into the same state regardless of the polarity of the output Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen COMBNATORAL MODE n combinatorial mode the pin associated with an individual OLMC is driven by the output of the sum term gate Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low) Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either on (dedicated output), off (dedicated input), or productterm driven (dynamic /O) ALL DEVCES n combinatorial mode there are also two options for the feedback The first feedback option into the AND array is from the /O pin side of the output buffer Both polarities (true and inverted) of the pin are fed back into the AND array The second option is to drive the feedback from / of the buried register This option provides the combinatorial output with the ability to register the feedback of the same combinatorial output DSCONTNUED 3

Select devices have been discontinued See Ordering nformation section for product status Specifications GAL26V2 REGSTERED MODE S0 = 0 S = 0 S3 = ACTVE LOW REGSTERED OUTPUT WTH BURED FEEDBACK S2 = Selects S2 = 0 Selects 2 ACTVE LOW REGSTERED OUTPUT WTH /O FEEDBACK S0 = 0 S = 0 S3 = 0 / 2 D D AR SP AR SP 2ALL DEVCES / S2 = Selects S2 = 0 Selects 2 ACTVE HGH REGSTERED OUTPUT WTH BURED FEEDBACK S0 = S = 0 S3 = S2 = Selects S2 = 0 Selects 2 ACTVE HGH REGSTERED OUTPUT WTH /O FEEDBACK S0 = S = 0 S3 = 0 / 2 / 2 D D AR SP DSCONTNUED AR SP S2 = Selects S2 = 0 Selects 2 4

Select devices have been discontinued See Ordering nformation section for product status Specifications GAL26V2 COMBNATORAL MODE ACTVE LOW COMBNATORAL OUTPUT WTH /O FEEDBACK S0 = 0 S = S3 = S2 = Selects S2 = 0 Selects 2 ACTVE LOW COMBNATORAL OUTPUT WTH BURED REGSTER FEEDBACK S0 = 0 S = S3 = 0 S2 = Selects S2 = 0 Selects 2 ACTVE HGH COMBNATORAL OUTPUT WTH /O FEEDBACK S0 = S = S3 = S2 = Selects S2 = 0 Selects 2 ALL DEVCES / 2 D AR SP DSCONTNUED ACTVE HGH COMBNATORAL OUTPUT WTH BURED REGSTER FEEDBACK S0 = S = S3 = 0 / 2 D AR SP S2 = Selects S2 = 0 Selects 2 5

Select devices have been discontinued See Ordering nformation section for product status Specifications GAL26V2 GAL26V2 LOGC DAGRAM / JEDEC FUSEMAP 0 4 2 6 20 24 2 32 36 40 44 4 2 3 4 5 6 7 VCC 0000 0052 046 0520 0936 09 50 560 24 2236 2964 306 34 ASYNCH RESET ALL DEVCES OLMC 27 S0-700 S-72 S2-724 S3-736 OLMC 26 S0-70 S-73 S2-725 S3-737 OLMC 25 S0-702 S-74 S2-726 S3-73 OLMC 24 S0-703 S-75 S2-727 S3-739 OLMC 23 S0-704 S-76 S2-72 S3-740 OLMC 22 S0-705 S-77 S2-729 S3-74 DSCONTNUED 0 4 2 6 20 24 2 32 36 40 44 4 2 AR SP 2 27 26 25 24 23 22 2 6

Select devices have been discontinued See Ordering nformation section for product status Specifications GAL26V2 GAL26V2 LOGC DAGRAM / JEDEC FUSEMAP (CONT) 0 4 2 6 20 24 2 32 36 40 44 4 2 AR SP 9 0 2 3 4 3900 4732 474 552 5564 636 6 6760 62 722 720 7696 774 ALL DEVCES 0 4 2 6 20 24 2 32 36 40 44 4 B0 B L S M S B3 B4 B5 B6 B7 74 749 B B Electronic Signature 790 79 SYNCH PRESET OLMC 20 S0-706 S-7 S2-730 S3-742 OLMC 9 S0-707 S-79 S2-73 S3-743 OLMC S0-70 S-720 S2-732 S3-744 OLMC 7 S0-709 S-72 S2-733 S3-745 OLMC 6 S0-70 S-722 S2-734 S3-746 OLMC 5 S0-7 S-723 S2-735 S3-747 DSCONTNUED 20 9 7 6 5 7

Select devices have been discontinued See Ordering nformation section for product status Specifications GAL26V2C ABSOLUTE MAXMUM RATNGS () RECOMMENDED OPERATNG COND Supply voltage V CC -05 to +7V nput voltage applied -25 to V CC +0V Off-state output voltage applied -25 to V CC +0V Storage Temperature -65 to 50 C Ambient Temperature with Power Applied -55 to 25 C Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications) DC ELECTRCAL CHARACTERSTCS Commercial Devices: Ambient Temperature (T A ) 0 to +75 C Supply voltage (V CC ) with Respect to Ground +475 to +525V ndustrial Devices: Ambient Temperature (T A ) 40 to 5 C Supply voltage (V CC ) with Respect to Ground +45 to +55V Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDTON MN TYP 4 MAX UNTS VL nput Low Voltage Vss 05 0 V VH nput High Voltage 20 Vcc+ V L nput or /O Low Leakage Current 0V VN VL (MAX) 0 μa H nput or /O High Leakage Current 35V VN VCC 0 μa VOL Output Low Voltage OL = MAX Vin = VL or VH 05 V VOH Output High Voltage OH = MAX Vin = VL or VH 24 V OL Low Level Output Current 6 ma OH High Level Output Current 32 ma OS 2 Output Short Circuit Current VCC = 5V VOUT = 05V T A = 25 C 30 30 ma COMMERCAL CC 3 Operating Power VL = 05V VH = 30V ftoggle = 5MHz -7/-0 90 30 ma NDUSTRAL ALL DEVCES Supply Current Outputs Open -5/-20 75 05 ma CC 3 Operating Power VL = 05V VH = 30V ftoggle = 5MHz -0/-5/-20 0 50 ma Supply Current DSCONTNUED Outputs Open ) The leakage current is due to the internal pull-up on all pins See nput Buffer section for more information 2) One output at a time for a maximum duration of one second Vout = 05V was selected to avoid test problems caused by tester ground degradation Guaranteed but not 00% tested 3) cc specified for a ten-bit binary counter pattern 4) Typical values are at Vcc = 5V and TA = 25 C

Select devices have been discontinued See Ordering nformation section for product status Specifications GAL26V2C Commercial AC SWTCHNG CHARACTERSTCS PARAM Over Recommended Operating Conditions TEST -7-0 -5 DESCRPTON COND MN MAX MN MAX MN MAX -20 UNTS MN MAX tpd A nput or /O to Combinatorial Output 75 0 5 20 ns tco A Clock to Output Delay 45 7 2 ns tcf 2 Clock to Feedback Delay 2 25 25 0 ns tsu Setup Time, nput or Fdbk before Clk 6 7 0 2 ns tsu2 Synch Preset before Clk 55 65 0 2 ns th Hold Time, nput or Feedback after Clock 0 0 0 0 ns A Maximum Clock Frequency with 952 74 555 46 MHz External Feedback, /(tsu + tco) fmax 3 A Maximum Clock Frequency with 250 052 00 454 MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with 42 25 33 625 MHz No Feedback twh Clock Pulse Duration, High 35 4 6 ns twl Clock Pulse Duration, Low 35 4 6 ns ten B nput or /O to Output Enabled 75 0 5 20 ns tdis C nput or /O to Output Disabled 75 0 5 20 ns tar A nput or /O to Asynch Reset of Register 9 3 20 20 ns tarw Asynchronous Reset Pulse Duration 6 0 5 ns tarr Asynch Reset to Clock Recovery Time 5 0 5 ns tspr Synch Preset to Clock Recovery Time 5 0 2 ns ) Refer to Switching Test Conditions section 2) Calculated from fmax with internal feedback Refer to fmax Description section 3) Refer to fmax Description section CAPACTANCE (T A = 25 C, f = 0 MHz) SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance pf V CC = 50V, V = 20V C /O /O Capacitance pf V CC = 50V, V /O = 20V *Guaranteed but not 00% tested ALL DEVCES DSCONTNUED 9

Select devices have been discontinued See Ordering nformation section for product status Specifications GAL26V2C Commercial AC SWTCHNG CHARACTERSTCS PARAM Over Recommended Operating Conditions TEST -0 DESCRPTON COND MN MAX tpd A nput or /O to Combinatorial Output 0 5 20 ns tco A Clock to Output Delay 7 2 ns tcf 2 Clock to Feedback Delay 25 25 0 ns tsu Setup Time, nput or Fdbk before Clk 7 0 2 ns tsu2 Synch Preset before Clk 65 0 2 ns th Hold Time, nput or Feedback after Clock 0 0 0 ns A Maximum Clock Frequency with 74 555 46 MHz External Feedback, /(tsu + tco) fmax 3 A Maximum Clock Frequency with 052 00 454 MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with 250 33 625 MHz No Feedback twh Clock Pulse Duration, High 4 6 ns twl Clock Pulse Duration, Low 4 6 ns ten B nput or /O to Output Enabled 0 5 20 ns tdis C nput or /O to Output Disabled 0 5 20 ns tar A nput or /O to Asynch Reset of Register 3 20 20 ns tarw Asynchronous Reset Pulse Duration 0 5 ns tarr Asynch Reset to Clock Recovery Time 0 5 ns tspr Synch Preset to Clock Recovery Time 0 2 ns ) Refer to Switching Test Conditions section 2) Calculated from fmax with internal feedback Refer to fmax Description section 3) Refer to fmax Description section CAPACTANCE (T A = 25 C, f = 0 MHz) SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance pf V CC = 50V, V = 20V C /O /O Capacitance pf V CC = 50V, V /O = 20V *Guaranteed but not 00% tested ALL DEVCES -5-20 UNTS MN MAX MN MAX DSCONTNUED 0

Select devices have been discontinued See Ordering nformation section for product status Specifications GAL26V2 SWTCHNG WAVEFORMS NPUT or /O FEEDBACK COMBNATORAL OUTPUT NPUT or /O FEEDBACK OUTPUT REGSTERED OUTPUT NPUT or /O FEEDBACK DRVNG AR tdis VALD NPUT tpd Combinatorial Output ten nput or /O to Output Enable/Disable tw h Clock Width tarw tar tw l tarr NPUT or /O FEEDBACK REGSTERED OUTPUT REGSTERED FEEDBACK NPUT or /O FEEDBACK DRVNG SP REGSTERED OUTPUT VALD NPUT ts u / fm ax (external fdbk) Registered Output tc f tsu th tc o / fmax (internal fdbk) fmax with Feedback ALL DEVCES DSCONTNUED tsu Synchronous Preset tco th tspr Asynchronous Reset

Select devices have been discontinued See Ordering nformation section for product status Specifications GAL26V2 fmax DESCRPTONS SWTCHNG TEST CONDTONS nput Pulse Levels GND to 30V nput Rise and Fall Times 2ns 0% 90% nput Timing Reference Levels 5V Output Timing Reference Levels 5V Output Load LOGC ARRAY t su REGSTER See Figure 3-state levels are measured 05V from steady-state active level Output Load Conditions (see figure) Test Condition R R2 CL A 300Ω 390Ω 50pF B Active High 390Ω 50pF Active Low 300Ω 390Ω 50pF C Active High 390Ω 5pF Active Low 300Ω 390Ω 5pF t co fmax with External Feedback /(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco LOGC ARRAY REGSTER fmax With No Feedback Note: fmax with no feedback may be less than /twh + twl This is to allow for a clock duty cycle of other than 50% LOGC ARRAY tcf t pd REGSTER fmax with nternal Feedback /(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = /fmax - tsu) The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above For example, the timing from clock to a combinatorial output is equal to tcf + tpd ALL DEVCES FROM OUTPUT (O/) UNDER TEST +5V C * L TEST PONT DSCONTNUED R 2 *C L NCLUDES TEST FXTURE AND PROBE CAPACTANCE R 2

Select devices have been discontinued See Ordering nformation section for product status Specifications GAL26V2 ELECTRONC SGNATURE OUTPUT REGSTER PRELOAD An electronic signature is provided in every GAL26V2 device t contains 64 bits of reprogrammable memory that can contain user-defined data Some uses include user D codes, revision numbers, or inventory control The signature data is always available to the user independent of the state of the security cell SECURTY CELL A security cell is provided in every GAL26V2 device to prevent unauthorized copying of the array patterns Once programmed, this cell prevents further read access to the functional bits in the device This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed The Electronic Signature is always available to the user, regardless of the state of this control cell LATCH-UP PROTECTON DEVCES GAL26V2 devices are designed with an on-board charge pump to negatively bias the substrate The negative bias minimizes the potential for latch-up caused by negative input undershoots Additionally, outputs are designed with n-channel pull-ups instead of the traditional p-channel pull-ups in order to eliminate latch-up due to output overshoots DEVCE PROGRAMMNG GAL devices are programmed using a Lattice-approved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section) Complete programming of the device takes only a few seconds Erasing of the device is transparent to the user, and is done automatically as part of the programming cycleȧll When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc) To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (ie, illegal) state into the registers Then the machine can be sequenced and the outputs tested for correct next state conditions The GAL26V2 device includes circuitry that allows each registered output to be synchronously set either high or low Thus, any present state condition can be forced for test sequencing f necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically NPUT BUFFERS GAL26V2 devices are designed with TTL level compatible input buffers These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices DSCONTNUED 3

Select devices have been discontinued See Ordering nformation section for product status Specifications GAL26V2 POWER-UP RESET Circuitry within the GAL26V2 provides a reset signal to all registers during power-up All internal registers will have their outputs set low after a specified time (tpr, μs MAX) As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins This feature can greatly simplify state machine design by providing a known state on power-up The timing diagram for power-up is shown below Because of the asynchronous nature of system power-up, some conditions must be met to guarantee a valid power-up reset of the GAL26V2 First, the VCC rise must be monotonic Second, the clock input must be at static TTL level as shown in the diagram during power up The registers will reset within a maximum of tpr time As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met The clock must also meet the minimum pulse width requirements NPUT/OUTPUT EUVALENT SCHEMATCS PN PN Vcc ESD Protection Circuit ESD Protection Circuit nput Vcc Vcc Vcc NTERNAL REGSTER - OUTPUT ACTVE LOW OUTPUT REGSTER ACTVE HGH OUTPUT REGSTER Output Data Output Data 40 V Feedback Tri-State Control ALL DEVCES Vcc tpr Output Active Pull-up Circuit Vref Feedback (To nput Buffer) nternal Register Reset to Logic "0" Device Pin Reset to Logic "" Device Pin Reset to Logic "0" DSCONTNUED PN PN 4

Select devices have been discontinued See Ordering nformation section for product status Specifications GAL26V2 TYPCAL AC AND DC CHARACTERSTC DAGRAMS Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc 2 2 2 Normalized Tpd Normalized Tpd 09 0 450 475 500 525 550 3 2 09 0 07 Supply Voltage (V) Normalized Tpd vs Temp Temperature (deg C) Normalized Tco Normalized Tco 09 0 3 2 09 0 07 450 475 500 525 550 Supply Voltage (V) Normalized Tco vs Temp Normalized Tsu 09 0 450 475 500 525 550 Supply Voltage (V) -55-25 0 25 50 75 00 25-55 -25 0 25 50 75 00 25-55 -25 0 25 50 75 00 25 Delta Tpd (ns) Delta Tpd (ns) 0-025 -05-075 2 0 6 4 2 0-2 - Delta Tpd vs # of Outputs Switching 2 3 4 5 6 7 9 0 2 Number of Outputs Switching Delta Tpd vs Output Loading RSE FALL Temperature (deg C) Delta Tco (ns) Delta Tco (ns) 0-025 -05 Normalized Tsu 4 3 2 09 0 07 Delta Tco vs # of Outputs Switching ALL DEVCES -075-2 3 4 5 6 7 9 0 2 Number of Outputs Switching Delta Tco vs Output Loading 2 0 RSE FALL 6 4 2 0-2 0 50 00 50 200 250 300 0 50 00 50 200 250 300 Output Loading (pf) Output Loading (pf) Normalized Tsu vs Temp Temperature (deg C) DSCONTNUED 5

Select devices have been discontinued See Ordering nformation section for product status Specifications GAL26V2 TYPCAL AC AND DC CHARACTERSTC DAGRAMS Vol vs ol Voh vs oh Voh vs oh 3 5 4 Normalized cc Vol (V) Delta cc (ma) 25 2 5 05 0 000 2000 4000 6000 000 0000 3 2 09 0 07 0 6 4 2 0 ol (ma) Normalized cc vs Vcc 450 475 500 525 550 Supply Voltage (V) Delta cc vs Vin ( input) 000 050 00 50 200 250 300 350 400 Vin (V) Voh (V) Normalized cc ik (ma) 4 3 2 0 3 2 09 0 07 0 0 20 30 000 000 2000 3000 4000 5000 6000 oh(ma) Normalized cc vs Temp -55-25 0 25 50 75 00 25 Temperature (deg C) nput Clamp (Vik) ALL DEVCES 40 50 60-200 -50-00 -050 000 Vik (V) Voh (V) Normalized cc 375 35 325 3 50 40 30 20 0 00 090 00 000 00 200 300 400 oh(ma) Normalized cc vs Freq 0 25 50 75 00 Frequency (MHz) DSCONTNUED 6