August 12, 1999 Lucent ORCA OR2C15A-2S208 FPGA Circuit Analysis Table of Contents List of Figures...Page 1 Device Summary Sheet...Page 4 Introduction...Page 6 PLC Architecture...Tab 1 Programmable Function Unit...Tab 2 PLC Routing Resources...Tab 3 Programmable I/O Cell...Tab 4 PIC Routing Resources...Tab 5 ORCA Internal Oscillator...Tab 6 Signal Naming Conventions...Tab 7 Signal Cross-Reference...Tab 8 For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call a Sales Representative at Chipworks. Telephone (613) 829-0414 Facsimile (613) 829-0515 Rev F2.2
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Lucent OR2C15A-2S208 ORCA FPGA Page 1 List of Figures 0.1.1 Package Markings 0.1.2 Package X-Ray 0.1.3 Pin Configuration 0.1.4 Die Markings 0.2.0 Die Photograph 0.2.1 Annotated Die Photograph 0.2.2 Die Architecture 0.3.0 Programmable Logic Cell Architecture 0.4.0 Programmable I/O Cell Architecture 1.0.0 Top Level Diagram 1.1.0 PLC Architecture 1.2.0 PIC Architecture 2.0.0 Programmable Function Unit 2.0.1 16x2 Synchronous Dual Port Memory 2.0.2 LUT : Look-up Table 2.1.0 16x1 SRAM 2.1.1 SRAM Cell 2.2.0 Read Address Decoder 2.3.0 Write Address Decoder 2.3.1 Write Address Decoder I 2.3.2 Write Address Decoder II 2.3.3 Write Address Decoder III 2.4.0 PFU 4x1 Multiplier 2.5.0 Multiplier Control 2.6.0 Address Switch 2.7.1 Write Enable 2.7.2 Write Pulse Generator 2.7.3 Write Port Enable Latch 2.7.4 Write Data Register 2.7.5 Address Register 2.8.0 Program Control Logic 2.9.0 PFU Latches/Flip-Flops 2.9.1 Latch/Flip-Flop 2.9.2 FEMUX: Front End MUX 2.10.0 PFU Output MUX 2.11.1 Clock Polarity 2.11.2 C0/CIN MUX 2.11.3 SSPM/SDPM Clocks 2.11.4 Latch/FF Clocks 2.12.0 CL: Configuration Latch
Lucent OR2C15A-2S208 ORCA FPGA Page 2 PLC Routing Resources 3.0.1 Input CIP 3.1.0 Auxiliary Routing Resources 3.2.0 Input Routing Resources 3.2.1 Input MUX 3.3.0 Output Routing Resources 3.4.0 C0-RR : C0 Routing Resources 3.5.0 CMUX: CIN and COUT Routing Resource MUX 3.6.0 Clock R-nodes 3.7.0 VCK: Vertical Clock Input Routing Resources 3.8.0 HCK: Horizontal Clock Input Routing Resources 3.9.0 PLC_BIDI 3.9.1 BIDI: 3-Statable Bidirectional Buffer 3.10.0 TRI Input R-nodes 3.11.0 Address Buffer 4.0.0 Programmable I/O Cell 4.1.0 PIC Input Buffer 4.2.0 Output Buffer 4.3.0 Boundary Scan Cell 4.3.2 Flip-Flop I 4.3.3 Flip-Flop II 4.4.0 Boundary Scan MUX I 4.5.0 Boundary Scan MUX II PIC Routing Resources 5.1.0 PIC BIDI 5.1.1 PIC_BIDI: 3-Statable Bidirectional Buffer 5.2.0 3-State Enable Signal MUX 5.3.0 LLDRV: Long Line Driver 5.4.0 PIC-OUT MUX 5.5.0 IN-Buffer 5.6.0 PIC x1 R-nodes 5.7.0 PIC-Clock R-nodes 6.0.0 ORCA Internal Oscillator 6.1.0 Internal Oscillator 6.1.1 Oscillator 6.1.2 Divider of 2 6.1.3 Oscillator Reset 6.1.4 D Flip-Flop 1 6.2.0 Frequency Divider 6.2.1 D Flip-Flop 2 6.3.0 Internal Oscillator MUX
Lucent OR2C15A-2S208 ORCA FPGA Page 3 6.4.0 Oscillator R-nodes A.1.0 Symbol Conventions A.2.0 Symbol Definitions - 1 A.2.1 Symbol Definitions - 2 A.2.2 Symbol Definitions - 3 A.3.0 Logic Gate Size Notation A.4.0 Transistor Size Notation A.5.0 Capacitor Size Notation A.6.0 FPGA Symbol Definitions - 1 A.6.1 FPGA Symbol Definitions - 2 A.6.2 FPGA Symbol Definitions - 3 A.6.3 FPGA Symbol Definitions - 4 A.6.4 FPGA Symbol Definitions - 5 A.6.5 FPGA Symbol Definitions - 6 A.6.6 FPGA Symbol Definitions - 7 A.6.7 FPGA Symbol Definitions - 8 A.6.8 FPGA Symbol Definitions - 9