Timing Pulses. Important element of laboratory electronics. Pulses can control logical sequences with precise timing.

Similar documents
Chapter 4: One-Shots, Counters, and Clocks

Digital Circuits I and II Nov. 17, 1999

Digital Fundamentals: A Systems Approach

Introduction. NAND Gate Latch. Digital Logic Design 1 FLIP-FLOP. Digital Logic Design 1

Logic Gates, Timers, Flip-Flops & Counters. Subhasish Chandra Assistant Professor Department of Physics Institute of Forensic Science, Nagpur

Flip-Flops and Related Devices. Wen-Hung Liao, Ph.D. 4/11/2001

Digital Fundamentals: A Systems Approach

PRE J. Figure 25.1a J-K flip-flop with Asynchronous Preset and Clear inputs

Solar Power for Small Hall

ASYNCHRONOUS COUNTER CIRCUITS

Counters

RS flip-flop using NOR gate

Chapter 6. Flip-Flops and Simple Flip-Flop Applications

Sequential Digital Design. Laboratory Manual. Experiment #7. Counters

DIGITAL CIRCUIT COMBINATORIAL LOGIC

The University of Texas at Dallas Department of Computer Science CS 4141: Digital Systems Lab

Lecture 8: Sequential Logic

Unit 11. Latches and Flip-Flops

Asynchronous (Ripple) Counters

(CSC-3501) Lecture 7 (07 Feb 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement

Experiment # 9. Clock generator circuits & Counters. Digital Design LAB

Digital Systems Laboratory 3 Counters & Registers Time 4 hours

YEDITEPE UNIVERSITY DEPARTMENT OF COMPUTER ENGINEERING. EXPERIMENT VIII: FLIP-FLOPS, COUNTERS 2014 Fall

CHAPTER 1 LATCHES & FLIP-FLOPS

RS flip-flop using NOR gate

Chapter 5 Flip-Flops and Related Devices

Laboratory 1 - Introduction to Digital Electronics and Lab Equipment (Logic Analyzers, Digital Oscilloscope, and FPGA-based Labkit)

Logic. Andrew Mark Allen March 4, 2012

DEPARTMENT OF ELECTRICAL &ELECTRONICS ENGINEERING DIGITAL DESIGN

Sri Vidya College of Engineering And Technology. Virudhunagar Department of Electrical and Electronics Engineering

EKT 121/4 ELEKTRONIK DIGIT 1

SEQUENTIAL LOGIC. Satish Chandra Assistant Professor Department of Physics P P N College, Kanpur

Combinational vs Sequential

Today 3/8/11 Lecture 8 Sequential Logic, Clocks, and Displays

DIGITAL ELECTRONICS MCQs

Other Flip-Flops. Lecture 27 1

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Sequential Circuits

PGT104 Digital Electronics. PGT104 Digital Electronics

5: Sequential Logic Latches & Flip-flops

Figure 30.1a Timing diagram of the divide by 60 minutes/seconds counter

Notes on Digital Circuits

CHAPTER 6 COUNTERS & REGISTERS

Topics of Discussion

Fig1-1 2-bit asynchronous counter

Computer Science 324 Computer Architecture Mount Holyoke College Fall Topic Notes: Sequential Circuits

Report on 4-bit Counter design Report- 1, 2. Report on D- Flipflop. Course project for ECE533

The NOR latch is similar to the NAND latch

MUHAMMAD NAEEM LATIF MCS 3 RD SEMESTER KHANEWAL

Review of Flip-Flop. Divya Aggarwal. Student, Department of Physics and Astro-Physics, University of Delhi, New Delhi. their state.

Logic Design. Flip Flops, Registers and Counters

LATCHES & FLIP-FLOP. Chapter 7

Unit-5 Sequential Circuits - 1

Counter dan Register

Universal Asynchronous Receiver- Transmitter (UART)

Sequential Logic and Clocked Circuits

Laboratory Exercise 7

CPE 200L LABORATORY 3: SEQUENTIAL LOGIC CIRCUITS UNIVERSITY OF NEVADA, LAS VEGAS GOALS: BACKGROUND: SR FLIP-FLOP/LATCH

10.1 Sequential logic circuits are a type of logic circuit where the output of the circuit depends not only on

CSE Latches and Flip-flops Dr. Izadi. NOR gate property: A B Z Cross coupled NOR gates: S M S R Q M

CSCB58 - Lab 4. Prelab /3 Part I (in-lab) /1 Part II (in-lab) /1 Part III (in-lab) /2 TOTAL /8

Registers and Counters

Experiment 8 Introduction to Latches and Flip-Flops and registers

2. Counter Stages or Bits output bits least significant bit (LSB) most significant bit (MSB) 3. Frequency Division 4. Asynchronous Counters

PHYSICS 5620 LAB 9 Basic Digital Circuits and Flip-Flops

INC 253 Digital and electronics laboratory I

More on Flip-Flops Digital Design and Computer Architecture: ARM Edition 2015 Chapter 3 <98> 98

VeriLab. An introductory lab for using Verilog in digital design (first draft) VeriLab

The outputs are formed by a combinational logic function of the inputs to the circuit or the values stored in the flip-flops (or both).

3 Flip-Flops. The latch is a logic block that has 2 stable states (0) or (1). The RS latch can be forced to hold a 1 when the Set line is asserted.

Clocks. Sequential Logic. A clock is a free-running signal with a cycle time.

2.6 Reset Design Strategy

Registers and Counters

EMT 125 Digital Electronic Principles I CHAPTER 6 : FLIP-FLOP

EKT 121/4 ELEKTRONIK DIGIT 1

Chapter 4. Logic Design

Mission. Lab Project B

Digital Logic Design ENEE x. Lecture 19

EET2411 DIGITAL ELECTRONICS

ECB DIGITAL ELECTRONICS PROJECT BASED LEARNING PROJECT REPORT ON 7 SEGMENT DIGITAL STOP WATCH USING DECODER

TMEL53, DIGITALTEKNIK. INTRODUCTION TO SYNCHRONOUS CIRCUITS, FLIP-FLOPS and COUNTERS

[2 credit course- 3 hours per week]

Administrative issues. Sequential logic

A clock is a free-running signal with a cycle time. A clock may be either high or low, and alternates between the two states.

Chapter 9. Design of Counters

Rensselaer Polytechnic Institute Computer Hardware Design ECSE Report. Lab Three Xilinx Richards Controller and Logic Analyzer Laboratory

Analysis of Clocked Sequential Circuits

Engr354: Digital Logic Circuits

Digital Logic Design Sequential Circuits. Dr. Basem ElHalawany

Digital Systems Based on Principles and Applications of Electrical Engineering/Rizzoni (McGraw Hill

DIGITAL ELECTRONICS: LOGIC AND CLOCKS

EE 367 Lab Part 1: Sequential Logic

Digital Design, Kyung Hee Univ. Chapter 5. Synchronous Sequential Logic

FE REVIEW LOGIC. The AND gate. The OR gate A B AB A B A B 0 1 1

Rangkaian Sekuensial. Flip-flop

Software Engineering 2DA4. Slides 9: Asynchronous Sequential Circuits

Figure 1 shows a simple implementation of a clock switch, using an AND-OR type multiplexer logic.

Chapter 9 Counters. Clock Edge Output Q 2 Q 1 Q

CMSC 313 Preview Slides

UNIT-3: SEQUENTIAL LOGIC CIRCUITS

INTRODUCTION TO SEQUENTIAL CIRCUITS

Transcription:

Timing Pulses Important element of laboratory electronics Pulses can control logical sequences with precise timing. If your detector sees a charged particle or a photon, you might want to signal a clock to store the time at which it occurred. You could use the event to generate a standard pulse so that your clock always responds in the same way. Alternatively, you might need to reset your electronics after the event Clearly you want the reset pulse to arrive as soon as possible after the data has been processed This requires a precision time delay generator

Timing Pulses A simple type of delay generator 1. A D-type flip-flop flop receives a clock edge and goes from low to high at the output 2. The output charges up an RC circuit after going high. 3. The charged capacitor also serves as the clear input to the D flip-flop. 4. So, that after a fixed time (roughly RC) ) the flip-flop flop resets back to its initial state. 5. The net result is a single pulse that has a duration (or pulse width) determined by the combination of the resistor & capacitor This is called a monostable multivibrator or one-shot.

One-shot: D-type D flip-flop flop + 5V S or PRE Input D Q output clock Pulse Input Q [Texas Instruments 74LS74 flip-flop datasheet] R or CLR R C

One-shot: D-type D flip-flop flop + 5V S or PRE Input D Q output clock Pulse Input Q [Texas Instruments 74LS74 flip-flop datasheet] R or CLR R C

Characteristics: One-shot: 74LS123 2 clock inputs triggered by either a rising edge or a falling edge. 2 outputs (Q( & Q). A reset or clear input, instantly sets the output to a standard condition regardless of the current state or clock level. Can be confused a little by pulses in quick succession.

Characteristics: One-shot: 74LS123 2 clock inputs triggered by either a rising edge or a falling edge. 2 outputs (Q( & Q). A reset or clear input, instantly sets the output to a standard condition regardless of the current state or clock level. Can be confused a little by pulses in quick succession. armed output pulse

74LS123 usage C R + 5V [Texas Instruments 74LS123 datasheet]

Pulse Delay Generator A single one-shot will produce a variable delay pulse. 2 one-shots can be combined to produce a pulse of variable duration/width produced at variable delay after a trigger. Pulse Delay Generator very useful in a research lab.

Pulse Delay Generator A single one-shot will produce a variable duration/width pulse. 2 one-shots can be combined to produce a pulse of variable duration/width produced at variable delay after a trigger. Pulse Delay Generator very useful in a research lab. [image from www.thinksrs.com]

Setting the Pulse Width with

The Problem with One-Shots 1. One-shots are very useful in a research laboratory as pulse delay generator. 2. One-shots should be avoided in regular circuitry, because They are useful in asynchronous circuits for avoiding glitches and signal races It s very easy to put them all over your asynchronous circuit with all the pulse timing set just right. It is very hard to figure out how the circuit works just by looking at it (or even a circuit diagram). The pulse width depends on temperature (R, C, and chip). The pulse width depends on supply voltage.

Pulse Width vs. Temperature

Pulse Width vs. Supply Voltage

Counters 1 2 3 1. Frequency dividers. 2. Ripple counter. 3. Synchronous counter.

JK-type flip-flop flop Logic table for clock falling edge input J Q output J K Q n+1 clock input K C Q 0 1 0 1 0 0 1 1 Q n 0 1 Q n JK-type flip-flops are used in counters.

T-type flip-flop flop JK Logic table clock J K C Q Q output J 0 1 0 K 0 0 1 Q n+1 Q n 0 1 input 1 1 Q n input clock T C Q output T Logic table (clock falling edge) T 0 Q n+1 Q n Q 1 Q n T-type flip-flops are used in counters.

Counters in Verilog Counters in Verilog are easy just use always (synchronous). and a self-referential add 1 assignment.

Initializing a register

Initializing a register This section initializes the register to zero. (Code should not rely on this too much!)

if statement

Variable Registers Recommendation: check the Technology Map Viewer after compiling.

The function command (I)

The function command (II)