DESIGN AND ANALYSIS OF FLIP-FLOPS USING REVERSIBLE LOGIC

DESIGN AND ANALYSIS OF FLIP-FLOPS USING REVERSIBLE LOGIC R. Jayashree, Dept. of ECE, SRM University, Kattankulathur. jayshreesrec@gmail.com M. Kiran Kumar, Dept. of ECE, SRM University, Kattankulathur. Kiransun5@gmail.com Prof. Dr. J. Selvakumar, Dept. of ECE, SRM University, Kattankulathur Selva2802@gmail.com Abstract - In recent year s reversible logic has been considered as an important issue for designing low power digital circuits. This has led many researches to take reversible logic very seriously in building important circuits related to low power CMOS design, optical information processing, DNA computing. The main purposes of designing reversible logic are to decrease the number of gates, garbage outputs, and power consumption. Since the output of a sequential circuit depends not only on the present inputs but also on the past input conditions, the construction of sequential elements using reversible logic gates is quite complex than that of combinational circuits. In this paper, we have verified some of the reversible gates both using Cadence Virtuoso and H-Spice tools, we have also designed and simulated reversible logic based sequential elements such as D latch, D flip-flop, T flip-flop, RS flip-flop and compare them in terms of average power, number of garbage outputs and number of constant inputs. Keywords: Low Power CMOS design, Garbage Output, Constant Input, Reversible Logic, Reversible Flip-Flops. I. INTRODUCTION Traditional logic computation is irreversible since the outputs do not have enough information to reconstruct the inputs. In logic calculation, if there are p inputs and q outputs such that p > q, then at least (p-q) bits of information are lost. As an example, a logic gate with two inputs and one output destroys at least one bit of information during computation. Landauer s principle states that each bit of information that is disregarded results in dissipation of heat, regardless of underlying technology. The amount of dissipated heat is at least ktln2 joules for every bit of lost information, where k is the Boltzmann s constant and T is the absolute temperature. At room temperature, this amount becomes 2.9*10-21 Joules [1]. According to the problem of heat dissipation arises from, (1) technological deviation from ideality of switches and materials and (2) Landauer s principle. In 1973, Bennett showed that KTln2 energy would not dissipate from a system as long as the system allows the reproduction of the inputs from observed outputs [2]. The current technologies have addressed the first part of the problem by reducing the heat loss. However, information loss in irreversible computation, which is the second part of the problem, will cause a considerable amount of heat generation in the near future due to increasing density of circuits. Reversible logic is being considered as an alternative of traditional irreversible logic since reversible computing does not erase or lose any information. As a result, reversible logic has a theoretical potential to dissipate no energy. According to Frank, reversible logic can recover a fraction of energy that can reach up to 100%. As there is no limit in reducing the heat dissipation in reversible logic, the amount of dissipated heat will become 1 very close to zero with the development of hardware. Reversible logic is a vital part of quantum computing since quantum computation is reversible, and the physical reality of quantum logic can be illustrated by reversible logic. Reversible computing is also useful for other technologies including low power CMOS design, optical computing, nanotechnology, and bioinformatics. II. BASIC DEFINITIONS PERTAINING TO REVERSIBLE LOGIC A. Reversible Function The multiple output Boolean function F(x 1 ; x 2 ; x n ) of n boolean variables is called reversible, if: a. The number of outputs is equal to the number of inputs, b. Any output pattern has a unique pre-image [5]. B. Reversible Logic Gate Reversible gates are circuits in which number of outputs is equal to the number of inputs and there is a one-to-one correspondence between the vector of inputs and outputs. It not only helps us to determine the outputs from the inputs, but also helps us to uniquely recover the inputs from the outputs [5]. C. Ancilla Inputs/ Constant Inputs This refers to the number of inputs that are to be maintained constant at either 0 or 1 in order to synthesize the given logical function [5]. D. Garbage Outputs Additional inputs or outputs can be added so as to make the number of inputs and outputs equal whenever necessary. This also refers to the number of outputs which are not used in the synthesis of a given function. In certain cases these become mandatory to achieve reversibility [5]. 210

III. BASIC REVERSIBLE GATES There are many number of reversible logic gates that exist at present. Some of the important reversible logic gates are A. Not Gate The simplest Reversible gate is NOT gate and is a 1*1 gate. Fig. 4 Block diagram of Fredkin gate Fig. 1 Block diagram of NOT gate B. Feynman Gate The Feynman gate which is a 2*2 gate and is also called as Controlled NOT, is widely used for fan-out purposes. The inputs are (A, B) and outputs are P=A, Q= A XOR B [3]. Fig. 2 Block diagram of Feynman gate Fig. 5 Schematic representation of Fredkin gate using cadence D. Peres Gate Peres gate is a 3*3 gate having inputs (A, B, C) and outputs P = A; Q = A XOR B; R = AB XOR C [8]. Fig. 3 Schematic representation of Feynman gate using cadence C. Fredkin Gate Fredkin gate is a 3*3 gate with inputs (A, B, C) and outputs P=A, Q=A'B+AC, R=AB+A'C [3]. Fig. 6 Block diagram of Peres gate 211

Fig. 10 Block diagram of BME gate Fig. 7 Schematic representation of Peres gate using cadence E. Sayem Gate Sayem Gate is a 4*4 reversible gates built using reversible combination of Fredkin gate and Feynman gate [3]. Fig. 8 Block diagram of Sayem gate Fig. 11 Schematic representation of BME gate using cadence G. TSG Gate The TSG gate is a 4*4 reversible gate. The input vector is I (A, B, C, D) and the output vector is 0 (P, Q, R, S). The output is defined by P = A, Q = A'C' ^ B', R = (A'C' ^ B') ^ D and S =(A'C' ^ B').D ^ (AB ^ C). The proposed TSG gate is capable of implementing all Boolean functions and can also work singly as a reversible Full adder [3]. Fig. 9 Schematic representation of Sayem gate using cadence F. Bme Gate BME Gate is a 4*4 reversible logic gate. The input vector is I(A,B,C,D) and the output vector is O(P,Q,R,S) [8]. Fig. 12 Block diagram of TSG Gate 212

There are basically four main types of latches and flipflops: 1. SR flip-flop 2. D flip-flop 3. JK flip-flop and 4. T flip-flop The major differences in these flip-flop types are the number of inputs they have and how they change state. A. D Latch with Enable When the E input is asserted (E = 1), the Q output follows the D input. In this situation, the latch is said to be open and the path from the input D to the output Q is transparent. Hence the circuit is often referred to as a transparent latch. When E is de-asserted (E = 0), the latch is disabled or closed, and the Q output retains its last value independent of the D input. Fig.13 Schematic representation of TSG gate using cadence Fig. 15 Logic symbol for D latch B. Reversible D Latch (using Sayem Gate) As the objective of the work is to reduce number of gates and power, we have considered Sayem Gate to design D Latch as it is the most optimized structure discussed in Section II. Fig. 16 Proposed design of D latch with only Q output Fig. 14 Transistor Implementation of TSG Gate IV. LATCHES AND FLIP-FLOPS Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can store one bit of information. The main difference between latches and flipflops is that for latches, their outputs are constantly affected by their inputs as long as the enable signal is asserted. In other words, when they are enabled, their content changes immediately when their inputs change. Flip-flops, on the other hand, have their content change only either at the rising or falling edge of the enable signal. This enable signal is usually the controlling clock signal. After the rising or falling edge of the clock, the flip-flop content remains constant even if the input changes. 213

D. Reversible D Flip-Flop (using Fredkin and Feynman Gate) The design of the D Flip-Flop using Fredkin and Feynman gate is shown in Fig. 19. A Fredkin gate is used as a 2:1 mux and the Feynman gate is used for getting a fan-out of 2. Fig. 20 Reversible D Flip-flop ( Fredkin and Feynman Fig. 17 Reversible Schematic representation of D Latch (Sayem using cadence C. D Flip-Flop with Enable A commonly desired function in D flip-flops is the ability to hold the last value stored rather than load in a new value at the clock edge. This is accomplished by adding an enable input called EN or CE (clock enable) through a multiplexer as shown in Fig 6.4. When EN = 1, the primary D signal will pass to the D input of the flip-flop, thus updating the content of the flip-flop. When EN = 0, the bottom AND gate is enabled and so the current content of the flip-flop, Q, is passed back to the input, thus, keeping its current value. Notice that changes to the flip-flop value occur only at the rising edge of the clock. Fig. 21 Reversible D Flip-flop (Fredkin and Feynman using cadence E. Design of Reversible T Flip-Flop The T flip-flop has one input in addition to the clock. T stands for toggle for the obvious reason. When T is asserted (T = 1), the flip-flop state toggles back and forth, and when T is deasserted, the flip-flop keeps its current state. The T flip-flop can be constructed using a D flip-flop with the two outputs Q and Q' feedback to the D input through a multiplexer that is controlled by the T input Fig. 18 D Flip-Flop with Enable Fig. 22 Logic symbol for T flip-flop Fig. 19 Logic symbol for D Flip-flop F. Reversible Positive Edge Triggered T Flip-Flop (using Sayem gate and Feynman Gate) The reversible realization of T Flip-flop has two Sayem gates and one Feynman Gate. And it has two constant inputs and it produces three garbage outputs 214

Fig. 23 Schematic Representation of Positive Edge Triggered T flip-flop (Sayem and Feynman Fig. 26 Schematic representation of T Flip-flop (Fredkin and Feynman using cadence H. Design of Reversible RS Flip-Flop A RS-flip-flop is the simplest possible memory element. The inputs R and S are referred to as the Reset and Set inputs, respectively. An RS flip-flop can be constructed from NAND and NOR gates Fig. 24 Schematic representation of T Flip-flop (Sayem and Feynman using cadence G. Reversible Positive Edge Triggered T Flip-Flop (using Fredkin gate and Feynman Gate) We proposed the Master-Slave T Flip-Flop using reversible gates such as Fredkin and Feynman. We added a Feynman gate to get the desired functionality of T XOR Q. Fig. 27 Logic symbol for RS flip-flop I. RS Flip-Flop (using BME and Peres The RS Flip-Flop can be mapped with one BME and two Peres gate. The BME gate needs E, S, 1 and R inputs respectively in 1st, 2nd, 3rd and 4th input. Our design needs only 3 reversible logic gates with 4 garbage outputs. Fig. 25 Reversible positive edge triggered T flip-flop (Fredkin and Feynman 215

Table. 1 Comparison of Parameters CIRCUIT AVERAGE POWER NUMBER OF GARBAGE OUTPUTS NUMBER OF CONSTAN T INPUTS Fig. 28 Reversible RS flip-flop ( BME and Peres D LATCH (using Sayem D flip-flop (using Fredkin and Feynman T FLIPFLOP (using Sayem and Feynman T FLIPFLOP (using Fredkin and Feynman RS FLIPFLOP (using BME and peres 8.8981µw 3 1 10.403µw 2 1 19.095 µw 3 2 20.341 µw 3 2 21.227µw 4 3 B. Results Fig. 29 Reversible Schematic representation of RS Flip-flop (BME and Peres using cadence V. PERFORMANCE EVALUATION A. Simulation Model and Parameters The basic reversible gates and Flip-Flops are simulated using "CADENCE TOOL" and H SPICE. Table 1 discuss about the comparison of the some important parameters of Flip-Flops simulated in H SPICE. Fig. 30 Simulation result for D Latch and D Flip-Flop 216

Fig. 31 Simulation result for T Flip-Flop [2] C. Bennett, Logical reversibility of computation, IBM J. Research & Development, vol. 17, no. 6, pp. 525 532, Nov. 1973. [3] Prashant R. Yelekar and Prof. Sujata S. Chiwande Design of sequential circuit using reversible logic, IEEE- International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 [4] Sujata S. Chiwande, Shilpa S. Katre, Sushmita S. Dalvi, Jyoti C Kolte, Performance Analysis of Sequential Circuits using reversible logic, International Journal of Engineering Science and Innovative Technology (IJESIT) Volume 2, Issue 1, January 2013. [5] Raghava Garipelly, P.Madhu Kiran, A.Santhosh Kumar, A Review on Reversible Logic Gates and their Implementation, International Journal of Emerging Technology and Advanced Engineering Volume 3, Issue 3, March 2013 [6] V.Rajmohan, V.Ranganathan, "Design of counter using reversible logic", 2011 IEEE [7] B.Raghu kanth, B.Murali Krishna, M. Sridhar, V.G. Santhi Swaroop A DISTINGUISH BETWEEN REVERSIBLE AND CONVENTIONAL LOGIC GATES, International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 2, Issue 2,Mar-Apr 2012, pp.148-151 [8] Md. Belayet Ali, Md. Mosharof Hossin and Md. Eneyat Ullah, Design of Reversible Sequential Circuit Using Reversible Logic Synthesis, International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.4, December 2011 [9] WWW. wikipidea. org. Fig. 32 Simulation result for RS Flip-Flop VI. CONCLUSION In this paper, basic existing reversible gates are completely studied and their truth table is verified by simulation. Further, basic reversible sequential circuits like D latch, D flip-flop, T flip-flop and JK flip-flop are designed. These flip-flops are constructed using various existing reversible gates and these circuits are compared in terms of average power consumption, garbage outputs and constant inputs. VII. REFERENCES [1] R. Landauer, Irreversibility and heat generation in the computing process, IBM J. Research & Development, vol. 5, no. 3, pp. 183 191,July 1961. 217