High-Speed ADC Building Blocks in 90 nm CMOS Markus Grözing, Manfred Berroth, INT Erwin Gerhardt, Bernd Franz, Wolfgang Templ, ALCATEL Institute of Electrical and Optical Communications Engineering Institute of Electrical Prof. and Dr.-Ing. Optical Communications Manfred Berroth Engineering ALCATEL and Innovation Stuttgart SODC 2006, 05.09.2006 Markus Grözing / INT 1
Outline Motivation ADC concept Sample & hold circuit Comparator circuit Decision flip-flop Conclusion SODC 2006, 05.09.2006 Markus Grözing / INT 2
Motivation CMOS Chip Digital Equalizer Data N A SER LD TIA EQ + DES D N Data Clock LD Fiber PD CR Clock Electronic dispersion compensation for long-haul optical links: Digital maximum likelihood sequence estimation (MLSE) High-speed low-resolution ADC required Digital equalization for other serial links: backplanes multi-chip-modules DRAM memory bus etc. SODC 2006, 05.09.2006 Markus Grözing / INT 3
Interleaved ADC Concept input termin. 1 sample & hold circuit quantizer block decision block D D thermometer to binary logic 1 1 7 7 3 D & & & 10 GHz Delay 20 GHz clock 2 divider with 4-phase clock output Input: 40 Gbaud 4x Interleaving: Sample & Hold Quantization: Comparator Decision: Flip-Flop Output: 4x3x10 Gbit/s SODC 2006, 05.09.2006 Markus Grözing / INT 4
Sample & Hold Circuit: Schematics V in,d A=1 A=1 A=1 V out,d S&H Block diagram: CLK _CLK two cascaded track & hold circuits operating in master-slave mode Track & hold circuit schematic: differential NMOS transfer gate compensated by dummy FETs at input and output V in,d CLK _CLK V hold,d V DD V out,d W/2 W W/2 I 0 V SS SODC 2006, 05.09.2006 Markus Grözing / INT 5
Sample & Hold Circuit: Layout V in,d A=1 A=1 A=1 V out,d _V CLK I Bias V SS CLK _CLK _V in V out V in _V out V SS V CLK V SS SODC 2006, 05.09.2006 Markus Grözing / INT 6
Sample & Hold Circuit: Measured Output Eyes 40 Gbit/s, 10 GHz, PRBS 2 7-1 40 Gbit/s, 10 GHz, PRBS 2 31-1 50 Gbit/s, 12.5 GHz, PRBS 2 7-1 50 Gbit/s, 12.5 GHz, PRBS 2 31-1 SODC 2006, 05.09.2006 Markus Grözing / INT 7
Sample & Hold Circuit: Reconstruction Hold Voltage 0 ps 10 ps 15 ps 20 ps 30 ps T S SODC 2006, 05.09.2006 Markus Grözing / INT 8
Comparator Circuit: Schematics Comparator block diagram: V in,d A=1 V out,d input stage 5 gain stages output buffer V comp,d V DD V DD V out,d V out,d V in,d V in,d V comp,d I 0 I 0 V SS I 0 1 / 2 I 1 1 / 2 I 1 Comparator input stage schematic: two parallel differential pairs V peak V SS Comparator gain stage schematic: diff. pair + diff. pair capacitively degenerated SODC 2006, 05.09.2006 Markus Grözing / INT 9
Comparator Circuit: Layout I Bias V comp V Peak V in,d A=1 V out,d V comp,d _V in V out V in _V out _V comp V SS SODC 2006, 05.09.2006 Markus Grözing / INT 10
Comparator Circuit: Measured Slicing Characteristic 0.4 differential output voltage V out,d [V] 0.3 0.2 0.1 0-0.1-0.2-0.3-0,3 V -0,2 V -0,1 V 0,0 V 0,1 V 0,2 V 0,3 V V comp,d as parameter -0.4-0.4-0.2 0 0.2 0.4 differential input voltage V in,d [V] SODC 2006, 05.09.2006 Markus Grözing / INT 11
Comparator Circuit: Measured Output Transient differential output voltage [V] 0.1 0.0-0.1-0.2-0.3 with peaking without peaking Input voltage step (V in,d ): from -500 mv to 0 mv at V comp,d = 0 mv Settling time: (5% - 95%) -0.4 0 50 100 150 200 time [ps] w/o peak: 111 ps with peak: 43 ps SODC 2006, 05.09.2006 Markus Grözing / INT 12
Decision Flip-Flop: Schematics V D Q D Q in,d A=1 V out,d Flip-flop block diagram: CLK _CLK two preamp stages two D-latches two postamp stages output buffer D-latch schematic: V DD current source omitted individual dimensioning of master & slave latch V in,d CLK _CLK V out,d V SS SODC 2006, 05.09.2006 Markus Grözing / INT 13
Decision Flip-Flop: Layout _V CLK I Bias V D Q D Q in,d A=1 V out,d CLK _CLK _V in V out V in _V out V CLK V SS SODC 2006, 05.09.2006 Markus Grözing / INT 14
Decision Flip-Flop: Measured Phase Margin phase margin [degrees] 360 270 180 90 25 mv 200 mv 50 mv 100 mv 35 mv 400 mv 300 mv Single-ended input voltage swing as parameter f Toggle = f bit @ 5, 10 Gbit/s. f Toggle = ¼ f bit @ 20, 30, 40 Gbit/s 0 0 10 20 30 40 50 input bit rate [Gbit/s] Phase margin 10 GHz: 324 @ 200 mv 274 @ 50 mv SODC 2006, 05.09.2006 Markus Grözing / INT 15
Decision Flip-Flop: Output Eye @ 10 Gbit/s / 10 GHz SODC 2006, 05.09.2006 Markus Grözing / INT 16
Decision Flip-Flop: Output Eye @ 40 Gbit/s / 10 GHz SODC 2006, 05.09.2006 Markus Grözing / INT 17
Conclusion Scalable ADC building blocks in 90 nm CMOS without any spiral inductors: Sample & hold circuit with compensated transfer gate - input bandwidth > 30 GHz - 12,5 GHz operation with 50 Gbaud input signal Comparator circuit with active peaking - >10 Gbaud operation - 43 ps settling time (5%-to-95%) (w/o peaking: 111 ps) Decision flip-flop with pre- and post-amplifier - 10 GHz phase margin: 324 @ 200 mv / 274 @ 50 mv - 40 Gbaud / 10 GHz phase margin: 143 @ 400 mv 3 bit 40 Gs/s 90 nm CMOS ADC seems feasible SODC 2006, 05.09.2006 Markus Grözing / INT 18
References 1. J. Lee et al., A 5-b 10-Gsamples/s A/D converter for 10-Gb/s Optical Receivers, IEEE JSSC, vol. 39, no. 10, pp 1671-1679, October 2004. 2. H. Tagami et al., A 3-bit soft-decision IC for powerful forward error correction in 10-Gb/s optical communication Systems, IEEE JSSC, vol. 40, no. 8, pp. 1695-1705, April 2005. 3. W. Cheng et al., A 3b 40GS/s ADC-DAC in 0.12µm SiGe, ISSCC 2004, pp. 262-263, February 2004. 4. Ken Poulton et al., A 20GS/s ADC with a 1MB memory in 0.18µm CMOS, ISSCC 2003, pp. 318-319, February 2003. 5. J. C. Jensen, L. E. Larson, A 16-GHz ultra-high-speed Si-SiGe HBT comparator, IEEE JSSC, vol. 38, no. 9, pp 1584-1589, Sept. 2003. SODC 2006, 05.09.2006 Markus Grözing / INT 19