Cypress Semiconductor White Paper By Jemmey Huang and Eric Jia Executive Summary This whitepaper is a brief introduction to CY8C22x45, an enhanced product of CY8C21xxx PSoC family. Introduction CY8C22x45 is an enhanced product of CY8C21xxx PSoC family. This product targets the Capsense applications with the integration of non CapSense control. CY8C22x45 consists of multiple mixedsignal array with OnChip Controller devices designed to replace multiple traditional MCUbased system components with one, low cost singlechip programmable component. It includes configurable blocks of analog and digital logic and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, CY8C22x45 includes some optimized modules such as 10bit SAR ADC, dedicated CSD digital logic, and other features to suit the applications. CY8C22x45 is compatible with other PSoC devices architecture as illustrated in Figure 1 on page 2. It comprises of four main areas; Core, System Resources, Digital System, and Analog System. Configurable global bus resources allow all the device resources to combine into a complete custom system. Each CY8C22x45 PSoC device includes eight digital blocks and six analog blocks. Depending on the PSoC package, CY8C22x45 provides up to 38 general purpose IOs (GPIO) and 16K Flash memory and a 1K SRAM data memory. Document No. 00150047 Rev *A October 15, 2012 Page 1 of 8
CY8C22x45 Resource Description The PSoC Core The PSoC core is a powerful engine capable of supporting a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO. The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a 4 MIPS 8bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 21 vectors to simplify the programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 16 KB of Flash for program storage and 1K bytes of SRAM for data storage. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can be doubled to 48 MHz for use by the digital system. A low power 32 khz ILO (internal low speed oscillator) is provided for the sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 khz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystalaccurate 24 MHz system clock using a PLL. The clocks and programmable clock dividers (as a System Resource), provide the flexibility to integrate any timing requirement into the PSoC device. PSoC GP IOs provide connection to the CPU, digital and analog resources of the device. Each pin s drive mode is selected from the eight options, allowing great flexibility in external interfacing. Every pin is capable of generating a system interrupt on high level, low level, and change from last read. Figure 1. Block Diagram of CY8C22x45 PSoC Core Port 4 Port 3 Port 2 Port 1 Port 0 Global Digital Interconnect Global Analog Interconnect SRAM 1K Interrupt Controller SROM Flash 16K CPU Core (M8C) Sleep and Watchdog Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array DBC DBC DCC DCC ROW 0 ANALOG SYSTEM Analog Input Muxing Analog Ref = System Bus DBC DBC DCC DCC ROW 1 CSD Digital Resource Analog Block Array SCE SCE 10bit SAR ADC Digital Clocks POR and LVD MAC I 2 C System Resets SYSTEM RESOURCES Internal Voltage Ref. Document No. 00150047 Rev *A October 15, 2012 Page 2 of 8
Digital System The digital system is composed of up to eight digital PSoC blocks or two rows of digital resource. Each block is an 8bit resource that is used alone or combined with other blocks to form 8, 16, 24, and 32bit peripherals, which are called user module references. Compared with existing PSoC products digital blocks, the digital block in CY8C22x45 has matured to address the requirements of customer feedback. To reflect this change in, the new digital block for basic function is named DBC and the communication block is named DCC. Figure 2 shows the digital block diagram. The digital block adds another data path to implement the enhanced features in DBC and DCC such as synchronous triggering, kill function, and so on. However, the digital block is fully compatible with existing PSoC products, if no enhanced feature is used in the user module. Figure 2. Digital Block Diagram Clock Select 161 MUX CLK Re Sync Digital PSoC Block Data Path CLK F1 14 DMUX Primary Function Output, clock chaining to next block. RO[3:0] Data Select 161 MUX DATA F2 14 DMUX RO[3:0] Aux Data Select 41 MUX INT BC AUX_DATA Block Interrupt Broadcast Output Data Select 2 New added 161 2nd Data input MUX DS2 Configuration Registers FUNCTION[7:0] INPUT[7:0] OUTPUT[7:0] CR0[7:4] CR1[7:0] Digital blocks in CY8C22x45 can be configured similar to the digital user modules in the CY8C21xxx products without any modification. It also includes the new user modules with enhanced features. Enhanced PWM: DBC and DCC support the deadband in one digital block; they can also support the multishot function. Users can set up the pulse number. When the module is triggered, it generates the exact number of PWM pulses before going to stop status. The new data path is used as the trigger for PWM start, from external synchronous signal, internal comparator bus output, and other digital blocks. Shift Register: The ShiftReg is a simplified version circuit of PRS/CRC circuit. It is a pure delay line which delays the input by setting the clock count and then outputs the delay signal to the bus through the tristate gate after each flipflop. It supports the applications such as FSK modem. Variable Length SPI: Variable length SPI comprises of two DCC blocks which can be configured as arbitrary data length from 9 to 16 bit for SPI communication. Document No. 00150047 Rev *A October 15, 2012 Page 3 of 8
The Analog System The analog system is composed of a 10bit SAR ADC, a VDAC circuit, and six configurable typee analog blocks. The programmable 10bit SAR ADC is an optimized ADC that runs up to 250 Ksps with ±2 LSB precision. It also has a sample and hold circuit. Besides the basic ADC features, the SAR10 ADC has the synchronous trigger features that allows the external signal, digital block output, or internal comparator bus output signal to trigger the ADC. The analog block is identical to CY8C21xxx analog block except that CY8C22x45 analog block is capable of more flexible input/output configuration. The two additional CT blocks on column 2/3 are optimized for the comparator implementation in core PSoC applications. For more information refer the section Enhancing the Comparator. Figure 3 Analog System Block Diagram ANALOG SYSTEM Port 0 Analog Input Muxs Analog Ref Analog Block Array Analog Bus Right System Clock SCE SCE RSLatch Analog Bus Left Global Out To DB From DB 10bit SAR ADC VDAC Analog modules that exist in CY8C21xxx are supported by these analog blocks. Enhancing the Comparator Although the analog block IP is the same as CY8C21xxx, the input of analog blocks in CY8C22x45 is more flexible and the output signal processing has more choices. If the CT analog block in column 2/3 is configured as a comparator, then the comparator provides an input selection from P2.6 or P2.7 to positive input. The negative and positive input of Opamp can be connected to external signals simultaneously. Positive input is through P2.6 or P2.7 pin and negative through the analog input mux from port 0. The comparator also provides another input selection from voltage reference on the internal VDAC, so that the comparators can be configured as a hysteresis comparator with the RSlatch. A noise filter is cascaded at the comparator output and set as 1, 2, 4, or 8 clock width to filter out corresponding glitch. This noise filter can be disabled by firmware. Another feature of the comparator is the synchronous control function; firmware can set up the digital block to trigger the latch in this circuit. Only when the synchronous signal is enabled, the comparator output is latched to the latch output. This function is useful in motor control or power conversion applications, which require the comparator to align with PWM signal. Similar to CY8C21xxx, the comparator output bus on CY8C22x45 can be routed directly to the global output bus without buffering by digital block. Figure 4 shows the block diagram of the comparator in CY8C22x45. Document No. 00150047 Rev *A October 15, 2012 Page 4 of 8
Figure 4. Block Diagram of Comparator Block Inputs Port Inputs VBG Analog Mux Bus L VDAC PMux Noise Filter LAT Comp bus Block Inputs Port Inputs VBG Analog Mux Bus R VDAC NMux Sync Control Analog Column Clock Hysteretic Comparator Implementation Hysteresis is the difference in the threshold levels at which the comparator turns on and off. This is useful in noise sensitive applications. CY8C22x45 provides internal resource to configure a hysteresis comparator without any external hardware requirement. Figure 5 shows the block diagram of a hysteresis comparator inside CY8C22x45. Figure 5. Block Diagram of Hysteresis Comparator V2BG (VDAC_TRIM) VDAC Hysteresis Comparator Vdd RefIn P0.x CMP Col. 3 Global Out vrefoutr (VDAC5xCR0) vrefoutl CMP Col. 2 Reset RSLatch Global Out There is a RSLatch sharing between column 2 and column 3 comparators. This is combined with the CT on column 2/3 and the VDAC for a hysteresis comparator or as analog PWM applications. Figure 5 shows the block diagram of VDAC on the left. The input of VDAC can be Vdd or V2bg (two bandgap voltage). The V2bg is an adjustable input, which can be from 1.4 to 2.34 times of the bandgap. The VDAC has two outputs, VrefoutL and VrefoutR, which have 32 adjustable steps ranging from 1/32 to 1 Refin. In the hysteresis comparator block diagram, the negative input of the comparator on columns 2 and 3 are connected to the VDAC output. The signal input from the I/O pin is connected to the positive input of the comparators. And the comparators output controls the Set/Reset input of the RSLatch. Document No. 00150047 Rev *A October 15, 2012 Page 5 of 8
CSD Implementation CY8C22x45 can support CSA, CSR, and CSD, though it is optimized for CSD applications. The key elements to complete CSD function include: Switched analog bus connected to sensor capacitor and a integration cap The clock generator to switch the analog bus A current element to charge or discharge the analog bus A comparator to compare the potential of the analog bus with predecided voltage A counter to count numbers CY8C22x45 provides dedicated resources for CSD implementation and easity integration of control functions other than CapSense. The first resource is the internal IDAC. CY8C22x45 has two IDACs, which can be used to replace the external Rb resistor to charge the Cmod capacitor. The IDAC can support up to 640 ua source current to fit for most resistor setting range. The second resource has two dedicated clocks for CSD scanning application. This frees the system clock resource VC1, VC2, and VC3 for other core PSoC applications. One clock, CSD_CLK, is derived from SYSCLK, the divider has eight different selection range from 1 to 256. The other clock, CNT_CLK, is derived from CSD_CLK and can have 1, 2, 4, or 8 divider selections. The third resources are the dedicated timers and counters. In CY8C21xxx, because of the limitation of digital block resource, the hardware counter is only configured as 8 bit width. There is a 16 bit width extension counter called CSD_wADC_Result in firmware to maintain the 16 bit counter result. A lot of interrupt is generated for the update of the firmware counter that occupies a lot CPU MIPS. The CY8C22x45 has a dedicated 16 bit width counter/timer. Therefore, the CSD implementation does not occupy any digital block and the digital block can be used for other applications. The CSD logic block can be configured to either 16bit timer/prs and counter function or 16bit timer with capture function. The timer period or PRS polynomial are both configurable. The resources used in CY8C22x45 include CSD logic, analog columns, and interface, adjustable dualchannel IDAC, IO_MUX, 2 separate analog MUX buses, digital blocks, chip level clocks, chip level digital bus. The combination of them can form five different CSD structures. 1. Compatible mode In this mode settings of CY8C21xxx is used (please refer to CY8C21xxx CSD User Module datasheet) except using an external resistor connected to Vdd instead of Vss. This is because the charge transferring (CT) mode in CY8C22x45 is negative CT mode and in CY8C21xxx it is positive CT mode. Configuring the CSD in compatible mode is disadvantageous because the CSD user module occupies many digital block and global clock resource, and the CPU MIPS would be exhausted by the interrupt coming from CSD scanning. 2. Enhanced mode with column 2/3 CT block and IDAC. In enhanced mode, the CSD UM can be configured as dual channels scanning simultaneously. The CSD user module is called CSD2x. Figure 6 shows the block diagram of CSD configuration in CY8C22x45. Figure 6. Block Diagram of CSD User Module with IDAC CY8C22x45 IDAC 0 Timer / PRS CSD Logic Csense IOMux CMP Vref DFF Counter Cmod Document No. 00150047 Rev *A October 15, 2012 Page 6 of 8
In the block diagram, the clock to drive IO_MUX is fixed frequency clock (selectable), or PRS output to reduce EMI and noise effect. The Vref comes from Vbg or VDAC in CMP columns. No other digital block is required and no VC1/VC2/VC3 is used in this configuration. PSoC uses internal IDAC for capacitor charging; external Rb resistor is not used. During running, only one interrupt happens for each conversion, so the CPU MIPS is released for the noncapsense control. This configuration support simultaneous dualchannel CSD scanning, as CY8C22x45 provides two sets of identical resources for dualchannel CSD applications. The CSD2x has the advantage in high button counter applications such as microwave ovens. It reduces the total scanning time and has a quick response time, which provides better customer satisfaction. 3. Enhanced mode with column 2/3 CT block and external Rb resistor This is similar to configuration 2, except that an external pull up resistor Rb is used to replace the internal IDAC, so an extra GPIO pad is needed in this configuration. Figure 7 shows the block diagram of this configuration. 4. Enhanced mode with column 0/1 CT block and IDAC This is similar to configuration 2; the only difference is using column 0 and column 1 CT block. The voltage reference input can only come from Vbg. 5. Enhanced mode with column 0/1 CT block and external Rb resistor This is similar to configuration 3; the only difference is using column 0 and column 1 CT block. The voltage reference input can only come from Vbg. Figure 7. Block Diagram of CSD User Module with External Resistor Neon Timer / PRS CSD Logic Csense IOMux CMP Vref DFF Counter Vdd Cmod Rb GOO Additional System Resources Other useful features of CY8C22x45 include: RTC: In many home appliances, customers require a precise clock for time keeping such as a real time clock display on the panel. CY8C22x45 provides a hardware RTC module, which uses external 32.768 KHz crystal for clock resource and provides the second, minute, and hour information in BCD mode. DeltaSigma Modulator (DSM): DSM is a density signal generator. In a digital signal stream, density is the percentage of the signal kept in high status. The actual waveform of the signal is insignificant, only the percentage of high signal is important. The DSM has two parts: the density signal generator, which outputs the density bit stream according to the customer setting and the density doman multiplier. I2C: CY8C22x45 I2C hardware module supports both master and slave modes. A commendable feature of the I2C slave module is that it can support address receiving function. This means the I2C slave module receives the data only when its address matches the address on the bus. Document No. 00150047 Rev *A October 15, 2012 Page 7 of 8
Target Applications Neon focuses on three major applications: CapSense (CapSense plus main controller integration) in white goods, home applications and others. This is useful in high button count applications that require two CapSense channels scanning simultaneously to reduce the total scanning time. CapSense in laptops and high end multimedia button boards that require complex behavior, touchpad, and so on. Generic embedded control applications that require enhanced digital block and improved analog block resource. Summary The PSoC CY8C22x45 mixedsignal array is derived from the CY8C21xxx family. It provides resources to support applications that integrate both CapSense and non CapSense control. These resources include dedicated CSD logic, enhanced digital and analog blocks, RTC, and SAR10 ADC. All trademarks or registered trademarks referenced herein may be the property of their respective owners. Cypress Semiconductor 198 Champion Court San Jose, CA 951341709 Phone: 4089432600 Fax: 4089434730 http://www.cypress.com Cypress Semiconductor Corporation, 20082012. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in lifesupport systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in lifesupport systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, nonexclusive, nontransferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in lifesupport systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product in a lifesupport systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document No. 00150047 Rev *A October 15, 2012 Page 8 of 8