Silicon Drift Detectors for the NLC Rene Bellwied (Wayne State University) SD Tracking Meeting September 18th, 2003 Proposed layout for LC tracker Silicon Drift technology hardware progress & plans SVT in STAR Simulation update Summary and Outlook
Silicon detector option for LCD (small detector, high field B=5T) Central tracker: Five Layer Device based on Silicon Drift or Silicon Strip Wafers Radiation length / layer = 0.5 %, sigma_rphi = 7 µm, sigma_rz = 10 µm Layer Radii Half-lengths ----------- ------------ 20.00 cm 26.67 cm 46.25 cm 61.67 cm 72.50 cm 96.67 cm 98.75 cm 131.67 cm 125.00 cm 166.67 cm 56 m 2 Silicon, Wafer size: 10 by 10 cm, # of Wafers: 6000 (incl. spares) # of Channels: 4,404,480 channels
Silicon Drift Tracker (SDT) in UCLC Participants: Wayne State University (WSU) & Brookhaven National Laboratory (BNL) BNL Physics: V. Jain, F. Lanni, D. Lissauer BNL Instrumentation: W. Chen, Z. Li, V. Radeka WSU: R. Bellwied, D. Cinabro, M. Coscione, V.Rykov (KEK) + new postdoc Funding: 3-year NSF proposal (pending, positive review): 2003-2005 for a total of $450 K ($ 80, 170, 200 K). Previously we had limited NSF funding for two years. Hardware contribution per year (for BNL): $ 25, 50, 90 K Check out the web at: http://rhic15.physics.wayne.edu/~bellwied/nlc
in use in STAR (RHIC), in construction for ALICE (LHC) SDD s: 3-d measuring devices Features: Low anode capacitance = low noise 3d information with 1d readout Pixel-like by storing 2 nd dimension in SCA Low number of RDO channels based on charge sharing
Details of mask design Future: stiffer implanted resistors, no outside power supplies R.Bellwied, June 30, 2002
SVT in STAR 216 wafers (bi-directional drift) 3 barrels, r = 5, 10, 15 cm, 103,680 channels, 13,271,040 pixels Resolution: 8 micron and 17 micron respectively, two-track: 150 micron Radiation length: 1.4% per layer 0.3% silicon, 0.5% FEE (Front End Electronics), 0.6% cooling and support. Beryllium support structure. FEE placed adjacent to wafers. No driving capability in very high resistivity n-type NTD Silicon. Water cooling.
Typical projective clam-shell design Typical projective clam-shell design
STAR-SVT characteristics 216 wafers (bi-directional drift) = 432 hybrids 3 barrels, r = 5, 10, 15 cm, 103,680 channels, 13,271,040 pixels Pixel count determined by # of time buckets in Switched Capacitor Array Resolution: 8 micron and 17 micron respectively Very high resistivity NTD n-type Silicon with no driving capability. At least preamplification stage has to be on detector Radiation length: 1.4% per layer 0.3% silicon, 0.5% FEE (Front End Electronics), 0.6% cooling and support. Beryllium support structure. FEE placed beside wafers. Water cooling. Future: 5 barrels, 6000 wafers, 4,400,000 channels, 0.5% rad.length per layer resolution: 7 micron and 10 micron respectively.
achieved with one-dimensional readout with 250 µm pitch Typical SDD Resolution Bench measurements now confirmed by STAR beam time results! (Feb.03) Can be improved through: faster drift, stiffer resistor chain for voltage gradient, different anode pitch, and better starting material
3d resolution with relaxed 1d readout pitch Drift detectors are dynamic, i.e. during the drift the electron cloud undergoes diffusion and Coulomb repulsion. That means cloud expands in both dimension (time and anode dimension). There will always be charge sharing because of instant Coulomb repulsion, but the amplitude changes as a function of drift distance and drift velocity. There is an intricate connection between size of wafer, applied voltage, readout pitch, and cluster reconstruction). The optimized readout pitch for STAR was 250 micron for a < 20 micron resolution in both dimensions for a dynamic range from 1-40 MIP when 1500 V are applied to a 3 cm drift distance.
Difference between drift and strip in terms of channel count Estimates for the SDT are around 4.4 Million channels assuming readout pitch similar to SVT. You get 1.1 billion pixels. Pixels are all around 300 by 200 micron. The suggested strip detector would have around 1.4 Million channels with 33 micron pitch in x and no z segmentation. You get 1.4 Million pixels. Pixels are 33 by up to 1,670,000 micron. Cost is similar although going to these very long nonsegmented strips might make the strip detector slightly cheaper. Difference is 2d vs 3d. Do we need 3d?
STAR measurements (I) Position resolution before and after calibration 13µm 8 µm
STAR measurements (II) Global track----momentum resolution----primary track
What is next for STAR-SVT? Enhance low pt coverage by accessing primary and secondary particles from 40-200 MeV/c and 100-500 MeV/c, respectively Enable high pt extension of TPC physics by improving momentum resolution for 10-100 GeV/c particles Enable D-meson, B-meson and potentially pentaquark reconstruction through hadronic decay channel reconstruction via impact parameter cuts. (Measured impact parameter resolution in pp-collisions with SVT is 90 micron.
Proposed wafer R&D Present: 6 by 6 cm active area = max. 3 cm drift, 3 mm (inactive) guard area Max. HV=1500 V, max. drift time=5 µs anode pitch = 250 µm, cathode pitch = 150 µm Future: 10 by 10 cm active area (or more?) Max. HV=2000 V Anode pitch, cathode pitch have to be optimized to give better position resolution (more channels = more money) Stiffer resistor chain dissipates slightly more heat on detector, but requires no off detector HV support and allows a more linear drift in drift direction (better position resolution) Reduce wafer thickness from 280 micron to 150 micron.
Details of mask design Future: stiffer implanted resistors, no outside power supplies R.Bellwied, June 30, 2002
Proposed Frontend (FEE) R&D Present: bipolar PASA & CMOS-SCA ( 16 channel per die, 15 die for 240 channels on beryllia substrate ) Multiplexing on detector, 8-bit ADC off detector (3m) Future: 0.25 micron (DSM) radiation hard CMOS technology for all three stages in one single chip (PASA, SCA, 10-bit ADC) Example: ALICE-PASCAL Less power consumption and power cycling allows us to switch from liquid cooling to air cooling!
Proposed mechanical R&D Present: Be angled brackets with Beryllia hybrids mounted Future: carbon fiber staves with TAB electronics wraparounds
Capabilities & Industry contacts In house capabilities High quality clean room facilities for design and prototyping of wafers and electronics at BNL Instrumentation division High level CMOS engineering capabilities at BNL Instrumentation Sensor testing facilities at WSU, Ohio State, and UT Austin Dedicated electronics testing facilities at BNL Physics Dedicated mechanical assembly facilities (CMM & CNC devices) at BNL Physics plus expert machine shop at BNL Industry contacts Past production contracts with commercial drift detector vendors: SINTEF, CSEM, EUROSYS, CANBERRA Potential interests: MICRON, HAMAMATSU Carbon fiber machining capabilities in house and in US, France & Russia Potential interest in scientific collaboration in France and Italy (LHC- ALICE groups)
Hardware deliverables in present 3 year proposal 2003 hardware deliverables: new drift detector wafer layout according to R&D goals. Feasibility study of BNL stripixel technology vs. drift detectors. long ladder prototype with old drift wafers (mechanical feasibility) 2004 hardware deliverables: large batch of prototype detectors, test radiation damage in test beam and with sources. Beginning design of new frontend electronics 2005 hardware deliverables: complete design for CMOS DSM type frontend with reduced power consumption and potentially integrated ADC, test TAB bonding of frontend to detector prototype, produce large frontend prototype batch. Extensive test beam requirements for completed detector/fee combination by end of 2005.
Stripixels:alternative from BNL? Alternating Stripixel Detector (ASD) Interleaved Stripixel Detector (ISD) Pseudo-3d readout with speed and resolution comparable to double-side strip detector on single-sided technology (Zheng Li, BNL report, Nov.2000). Attractive for faster speed and easier to manufacture than double-sided strip
Simulation update: L vs. SD
Simulation update: hit occupancy on single wafer Using STAR detector layout and LC simulations (t-tbar to 6 jet events at root-s = 500 GeV incl. γ background according to T. Maruyama): Around 2000 γ/event leave hit in Silicon, corresponding to an occupancy of 13 hits/hybrid (0.5% occupancy) 51,200 pixels per hybrid, 20 pixels/hit Occupancy could be further reduced by factor 2 by using different SCA
Occupancies and tracking efficiencies with background For 100% hit efficiency: (97.3±0.10)% Almost identical to no background!
New simulations two track resolution Two hit resolving power κ = xv 1/2 / 2Dx 0 Input: two MIP hits High κ = good resolving power κ > 2 two tracks resolved κ > 1 two tracks resolved using deconvolution K depends on : Drift velocity Drift distance Sampling rate PASA impulse response
Two track resolution results
Two track resolution - Conclusions Conclusions: 2-track resolution without deconvolution: 600 micron in both dimensions 2-track resolution below drift distances of 2cm without deconvolution: 400 micron 2-track resolution with deconvolution via waveform analysis: 300 micron
New SVT publications Presentation at Vertex 2002 (H.Caines et al., http://www.phys.hawaii.edu/vprivate/caines.ppt) New NIM summary article (R. Bellwied et al., NIM A 499, 640 (2003))
Need for test-beam in 2004/2005 z z z z Use particle beams in the momentum range from 100 MeV/c to several GeV/c Measure single particle and two-track resolution Check noise and repetition rate for frontend Check settling time and power consumption for RDO power-off mode during bunches
Summary / Conclusions Silicon Drift is an interesting and rather new technology Proof of principle is the mass produced STAR-SVT (0.7 m 2 ). Next generation is the ALICE-ITD (~ 2m 2 ). Can we conceive of a 56 m 2 SDT? This technology gives you comparable 3d information for the same price than a strip detector will give you strictly 2d information. Do we need 3d? It is an interesting alternative that should be supported during the R&D phase and then a decision should be made on the basis of physics (and manpower, infrastructure, cost, feasibility).