International Journal of Modern Trends in Engineering and esearh www.ijmter.om e-iss o.:349-9745, Date: -4 July, 5 A eview on VLSI Implementation of Multiplierless FI Filter ased On Distriuted Arithmeti Komal Lineswala,ishit Vanawala, Prof. aesh Gajre 3 E.C ICT, C.G.P.I.T UaTarsadia University, omallineswala@gmail.om E.C ICT, C.G.P.I.T UaTarsadia University,nishitvanawala@gmail.om 3 E.C ICT, C.G.P.I.T UaTarsadia University, raesh.gajre@utu.a.in Astrat The main target for any design is to implement a digital system that has high speed, low power onsumption and has low hardware usage and memory requirement. So, a detailed review on one of the high speed and area effiient multiplierless tehnique for realizing FI filter ased on Distriuted Arithmeti DA is presented. Various arhitetures for implementing high order FI filter ased on DA whih maes minimum usage of hardware. And also arhiteture for high speed FI filter is reviewed whih attains maimum speed at a ost of some hardware. However, using DA results up to 5% redution in total oupied area ompared to diret FI filter implementation. Keywords- FI Filter; Distriuted Arithmeti DA; DA-Offset inary Code DA-OC; LUT less DA; FPGA. I. ITODUCTIO Over past several deades, the field of digital signal proessing DSP has een developed in an area of siene and tehnology. This development is due to signifiant advanes in digital omputer tehnology and integrated iruit fariation. The rapid development in IC tehnology, starting with medium sale integration MSI, and progressing to large sale integration LSI, and then to very large sale integration VLSI of eletroni iruits has spurred the development of powerful, smaller, faster, and heaper digital omputers and speial purpose digital hardware. Thus, Digital signal proessing DSP has reated a major impat in the areas of digital ommuniation, speeh and image proessing, adaptive filtering appliations, satellite ommuniation, wired and wireless ommuniation, multimedia systems, iomedial instrumentation []. FPGA are on the verge of revolutionizing DSP in the manner that digital signal proessors did several years ago. Many DSP algorithms that were uilt with ASICs or DSP proessors are now replaed y FPGA. However, FPGA have many features in ommon with ASICs, suh as redution in size, weight, and power dissipation, higher throughput, etter seurity against unauthorized opies, redued devie and inventory ost, and its advantages over ASICs are, suh as redution in development time, in-iruit reprogrammality and lower E osts. Compared to PDSPs, FPGA design typially eploits parallelism []... FI Filters One of the most signifiant omponents in many DSP systems are digital filters. Digital filter is a LTI system used to perform spetral shaping or frequeny seletive filtering suh as removing undesirale noise from desired signals, et. Finite Impulse response FI filter and Infinite impulse response II filter are the two types of digital filters. FI filter is mostly used in DSP system due to its linear phase response, simple implementation and staility. FI filter is one, whose impulse @IJMTE-5, All rights eserved 59
International Journal of Modern Trends in Engineering and esearh IJMTE Volume, Issue 7, [July-5] Speial Issue of ICTET 5 response is of finite duration and eventually reahes to zero, i.e., it has finite numers of non-zero terms. As there is no feeda of past output to form present output, it s also alled feed-forward networ. The general differene equation for a FI digital filter is: y n h n where, yn is the filter output at disrete time instane n, h is the th feed forward tap, or filter oeffiient, and n- is the filter input delayed y samples. The Σ denotes summation from = to - where n is the numer of feed forward taps in the FI filter. The diret implementation of tap FI filter requires Multiply and Aumulate MAC los. Here to ompute the output of filter, onvolution of impulse response and input sequene is taen whih means etensive use of multipliation operations and use of multiplier may eome epensive in terms of area and speed. Figure. -Tap FI Filter and its Classifiation. elated Wors As for K-tap FI filter K MAC los are required whih not only inreases design ost ut also inreases the ompleity. In [3], the onept of Distriuted Arithmeti DA was introdued to resolve the issues of onventional FI filter, whih is a multiplierless tehnique and ased on s omplement representation of data and novel it position reordering. In [4] very first detailed desription of DA was done in whih a new approah for implementing FI filter was proposed y storing possile outomes of intermediate arithmeti operations, and using them to ompute the output sample through series of repeated addition and shifting. This eliminated the use of multiplier and resulted in signifiant savings in terms of hardware ost and power onsumption. DA is so named as Distriuted Arithmeti eause it is not just re-arrangement of adders, multipliers or registers ut a new desription where fundamental operation of onvolution and multipliation are mied suh that arithmeti eomes distriuted through the struture [5]. In [6], a review on appliation of Distriuted Arithmeti to Digital Signal Proessing was given whih stated that DA is it serial operation that forms an inner produt of vetor pairs in a single step. Also other modifiation to DA arhiteture was also made. The main drawa of DA was also disussed, that is, the size of loo up tales LUT inreases eponentially with the order of filter. In [7], DA Offset inary Coding DA-OC was proposed whih redued the size of LUT. And in [8] a modified DA arhiteture was introdued whih replaed the use of LUT with multipleer/adder pair. @IJMTE-5, All rights eserved 6
International Journal of Modern Trends in Engineering and esearh IJMTE Volume, Issue 7, [July-5] Speial Issue of ICTET 5 This paper is organized as follows: Setion II desries theoretial aground of Distriuted Arithmeti and its asi it serial arhiteture. Different arhitetures for higher order FI filter are disussed in Setion III whih desries different tehniques to redue memory requirement. And in Setion IV arhiteture for high speed FI filter is disussed and performane analysis of all these arhiteture is presented in Setion V. II. DISTIUTED AITHMETIC DA is one of the most signifiant FPGA tehnology used for implementing FI filters. An FI filter of -length is desried as: y[ n] h n For onveniene, let n ow, let e -it s omplement inary numer saled suh that < given y:, Є {, }, where, denotes th it of is the sign it and is the Least Signifiant it LS. The term in the raet has possile ominations that an e omputed online using AM or preomputed so that they an e stored in OM. The it sequene of input an e used as address to the memory and operations suh as shifting and addition are performed on the output of LUT or OM and storing the result in aumulator. Figure. 4-Tap LUT ased Distriuted Arithmeti [] y[ n] h y[ n] h h So as to produe one filter output y[n], lo yles are required. The asi arhiteture of DA is shown aove. This arhiteture onsists of three main units that are input shift register unit, OM @IJMTE-5, All rights eserved 6
International Journal of Modern Trends in Engineering and esearh IJMTE Volume, Issue 7, [July-5] Speial Issue of ICTET 5 ased LUT unit, and aumulator/shift unit. The LUT ontains all possile omination sum of filter oeffiients, h suh that =,,,,-. The input shifter register unit stores the input sample. Firstly the input sample is given to parallel to serial onverter whih parallely loads the its of sample into it and outputs the it serially to the shift register unit. Here the shift register are arranged in a daisy hain form. Then after at every lo yle, the its from all shift register are shifted out starting from LS. These its from all shift registers are onatenated to form address line to selet orresponding omination of oeffiient sum. For signed DA sheme, the MS is used to distinguish etween positive and negative numers. CT is the sign it timing signal. In a lo period nown as sign it time all the MS s, that is, sign its from shift registers arrive simultaneously and during this sign it time, CT= otherwise CT=. III. DA ACHITECTUE FO HIGHE ODE FI FILTES 3.. Memory edued DA. ut the main drawa with the aove arhiteture is that as the order of filter inreases the size of LUT -words grows eponentially. So the redution of LUT or OM size is of prime importane. This inreased OM size prolem an e redued y using two methods: OM Deomposition and speial oding of OM ontent that is, using Offset inary Coding OC. 3... OM Deomposition. In this method [9], memory size an e redued y su-dividing LUT s into numer of LUT s alled LUT partition and then y using adder, all OM outputs are added. Thus, y using this method, memory size an e redued from words to P M words. 3... DA-Offset inary Code DA-OC. Jung Pil et al. [7] proposed a method for OM size redution in whih input is not represented in inary, ut instead represented in offset inary ode, that is, in -,. Figure 3. -Tap LUT or OM Deomposition [9] Figure 4. 4-Tap DA-OC[7] @IJMTE-5, All rights eserved 6
International Journal of Modern Trends in Engineering and esearh IJMTE Volume, Issue 7, [July-5] Speial Issue of ICTET 5 @IJMTE-5, All rights eserved 63 ewriting as: In s omplement representation, negative of is written as: where,, ] [ h n y Let, for h, h etra Thus, etra n y ] [ y using DA-OC method, OM size redues to -. In this arhiteture, XO gates are used as address deoder to selet orresponding oeffiient sum. However, two ontrol signals, S and S, are used where S= when = otherwise S= and S= when = otherwise S=. 3.. LUT less DA Arhiteture. H.Yoo et al. [8] notied from LUT in figure that values in lower half of LUT whose MS= are mirror image of the values of upper half of LUT whose MS= and h3 term. Therefore, LUT or OM size an e redued y fator of, that is, from words to - words with a : MUX and an adder. y performing same LUT redution proedure iteratively, LUT size an e redued dramatially y replaing LUT with numers of : MUX and full adders. For -tap FI filter, - numers of full adders are required where numer of MUXrequired is equal to numer of oeffiients. 3.3. Performane Analysis. H. Yoo et al. [8] made a performane analysis related to area oupied y single DA ase unit. However, the input shift register unit and adder/shifter units are not onsidered in analysis sine they are ommon for all strutures. represent word lengths of original LUT and represents ase unit size. It was notied that LUT less version required fewer logi elements LE and memory ompared to original LUT ased DA.
International Journal of Modern Trends in Engineering and esearh IJMTE Volume, Issue 7, [July-5] Speial Issue of ICTET 5 IV. DA ACHITECTUE FO HIGH SPEED FI FILTES If FI filter is implemented using it serial DA arhiteture then it will onsume lo yles to ompute one output. When it is proessed at a time, DA is alled AAT-DA serial DA and when its are proessed at a time, then DA is alled AAT-DA parallel DA and so on. FI filter an also e implemented using parallel version of DA arhiteture. With this arhiteture, only one lo yle is needed to ompute one output. If FI filter is implemented using it serial DA arhiteture then it will onsume lo yles to ompute one output. When it is proessed at a time, DA is alled AAT-DA serial DA and when its are proessed at a time, then DA is alled AAT-DA parallel DA and so on. FI filter an also e implemented using parallel version of DA arhiteture. With this arhiteture, only one lo yle is needed to ompute one output. The main advantage of using this arhiteture is that it an high speed ompared to serial DA. However, this arhiteture has twie throughput ompared to serial DA, ut numer of LUT required is also twie that used in serial DA. So, resoure usage is times more than that used in serial DA. Tale. Performane Analysis[8] Logi Funtions LUT ased DA Fig. DA-OC Fig. 4 LUTless DA Fig. 5 OM Deoder C, C, OM Data D,, D,, XO 8 : MUX 6 6 egister 6 Adder - 3 Adder/Su, Cin= Adder/Su, Cin= Adder/Su V. COCLUSIO Muh arhiteture for higher order and high speed FI filter implementation were reviewed. Thus from the analysis, hardware redution of LUT less version ours around 6 to 8 taps and thereafter redution rate grows signifiantly as filter size inreases. And higher speed an e ahieved at a little hardware ost. EFEECES []J.G.Proais, D.G.Manolais,Digital Signal Proessing:Priniples, Algorithms and Appliations, J:Prentie Hall, 996. []U.Meyer-aese,Digital Signal Proessing with Field Programmale Gate Arrays, Springer, 7. [3] A.Croisier, D.J.Estean, M.E.Levilion, and V.izo, "Digital Filter for PCM Enoded Signals," U.S. Patent 37773, Deemer 4,973. [4] A.Peled, and.liu, "A ew Hardware ealization of Digital Filters," IEEE Transations on Aoustis, Speeh Signal Proessing, pp. 456-46, Deemer 974. [5] C.Sidney urrus, "Digital Filter Struutres Desried y Distriuted Arithmeti," IEEE Transations on Ciruits and Systems, pp. 674-68, Deemer 977. [6] S.A.White, "Appliations of Distriuted Arithmeti to Digital Signal Proessing. A Tutorial eview," IEEE ASSP Magazine, pp.4-9, July 989. [7] J.P.Choi, S.Shin, and J.G.Chung, "Effiient OM Size edution for Distruuted Aruthmeti," IEEE Symposium on Ciruits and Systems ISCAS, pp. 6-64, May. [8] H.Yoo, and D.V.Anderson, "Hardware Effiient Distriuted Arithmeti for High Order Digital Filters," Pro. IEEE International Conferene on Aoustis, Speeh Signal Proessing ICASSP, pp. 5-8, Marh 5. @IJMTE-5, All rights eserved 64