SingMai Electronics PT51. Advanced Composite Video Interface: Decoder. User Manual. Revision rd November 2016

PT51 Advanced Composite Video Interface: Decoder User Manual Revision 1.1 23 rd November 216 Page 1 of 52

Revision History Date Revisions Version 7-5-216 First Draft..1 2-6-216 Added further video standards..2 Added NTSC/PAL decoding. AGC description added. Interconnection block diagram added. Modules and some ports renamed. SD demodulation filter added. Anti-aliasing filter for SD added. NTSC/PAL comb filter added. 5-7-216 Status registers updated..3 AFE schematic updated. AGC operation improved. Improved comb filter description. Text corrections. 12-7-216 18i standards added..4 Schematic port names updated. Text corrections. acvi description updated. 1-8-216 Subcarrier frequencies modified..5 acvi description updated. Separate proc-amp controls added for NTSC/PAL/HD standards. Phase comparator filter modified. 16-8-216 Verification chapter added..6 29-8-216 Automatic colour control (ACC) added..7 19-9-216 Automatic SD/HD format detection added..8 Changes/additions to the registers. NTSC-96H and PAL-96H standards added. acvi spectrum (Figure 3) corrected. Manual setting of burst gate positioning added. Manual setting of subcarrier frequency added. Added luma low pass filter (support for HD-CVI and HD-TVI). Sample rate converter added. acvi.5 description added. 12-1-216 Text corrections..9 Control registers modified. Auto cable compensation description updated. Data transfer chapter updated. Measure.v module added. FIFO.v module added. Schematics updated to the SM8 v.2 revision. 16-11-216 Remove FIFO. Remove SRC. acvi.5 removed. DDS clock generator added. Demodulation filter redesigned. 1. Page 2 of 52

Date Revisions Version AGC register controls added. Anti-aliasing filter added. Data transfer updated. Auto cable compensation updated. 23-11-216 Add phase detector gain control. 1.1 Page 3 of 52

Contents Revision History... 2 Contents...4 Tables...4 Figures... 5 1. Introduction...6 2. PT51 Module description... 7 3. Signal Interconnections...8 4. acvi Overview...12 5. Analogue Front End... 14 6. Synchronisation modes... 19 7. Technical Overview... 22 7.1 PT51_decoder.v... 22 7.2 Register_control.v... 22 7.3 AA_Filter.v... 23 7.4 Demod.v... 23 7.5 DemodLPF.v... 25 7.6 Delay.v... 27 7.7 Comb_filter.v...28 7.8 Remod.v...29 7.9 SPG.v...29 7.1 Procamp.v...31 7.11 Measure.v... 32 7.13 Data.v... 32 8. acvi Cable Compensation... 33 9. Data Transfers...36 1. Register interface...38 11. Register descriptions...39 12. Default register settings...45 13. PT51 Verification...47 14. Appendix A - VCXO Specification...5 Tables Table 1 PT51 Altera FPGA resource requirements...6 Table 2 PT51 Verilog file structure... 7 Table 3 PT51 Input/Output signals... 1 Table 4 acvi supported video formats....12 Table 5 PT51 and ADC sample rates.... 19 Table 6 PT51 Line and subcarrier frequencies... 24 Table 7 Register description....44 Table 8 Default register settings: acvi, 72p formats....45 Table 9 Default register settings: acvi, 18p/i formats....45 Table 1 Default register settings: SD formats....46 Table 11 acvi vertical sync components - 18p...49 Page 4 of 52

Figures Figure 1 PT51 Block symbol...8 Figure 2 PT51 IP core interconnections... 11 Figure 3 acvi Spectrum....13 Figure 4 acvi input levels... 14 Figure 5 AGC Control loop...15 Figure 6 AD8337 PGA gain response....15 Figure 7 Analogue Front End schematics....17 Figure 8 ADC schematics... 18 Figure 9 External VCO schematic...2 Figure 1 DDS Clock generation schematic....21 Figure 11 PT51 Block diagram... 22 Figure 12 Anti-aliasing filter.... 23 Figure 13 Chroma demodulator low pass filter (acvi operation)....26 Figure 14 Chroma demodulator low pass filter (NTSC/PAL)...26 Figure 15 Chroma demodulator low pass filter (96H)... 27 Figure 16 Luma low pass filter - default parameters... 27 Figure 17 Y Filter response (12MHz)...28 Figure 18 Comb filter luma LPF....29 Figure 19 Phase detector low pass filter response (HD standards)....3 Figure 2 Phase detector low pass filter response (SD standards)....3 Figure 21 Vertical sync recovery filter (HD standards)...31 Figure 22 Coaxial cable frequency response.... 33 Figure 23 Insertion test signal...34 Figure 24 acvi output, 3MHz sweep (Pre-emphasis = minimum)...34 Figure 25 acvi output, 3MHz sweep (Pre-emphasis = maximum).... 35 Figure 26 Data transfer protocol....36 Figure 27 PT51 Data insertion schematic.... 37 Figure 28 PT51 Register timing...38 Figure 29 18p/3Hz video waveform - vertical interval....47 Figure 3 acvi broad pulse - 18p/3Hz....47 Figure 31 acvi blanking, no burst - 18p/3Hz...48 Figure 32 acvi blanking with burst - 18p/3Hz....48 Figure 33 acvi 75% colour bars - 18p/3Hz...49 Figure 34 VCXO Specification - Page 1...5 Figure 35 VCXO Specification - Page 2....51 Figure 36 VCXO Specification - Page 3... 52 Page 5 of 52

1. Introduction PT51 is a video decoder IP (intellectual property) core compatible with the acvi Advanced Composite Video Interface format, and also with NTSC/PAL standards. acvi is a method to transmit HD video over long distances of existing coaxial or twisted-pair cable networks or allow the use of less expensive RG-59/UTP cable in long distance installations. The decoder IP accepts digital acvi/ntsc/pal encoded video at 1 bit resolution, which it decodes to a 2 bit YCbCr (4:2:2 format) output with separate horizontal and vertical synchronizing pulses and clock. PT51 supports the following HD acvi formats: 72p-25/3/5/59/6Hz, 18p- 24/25/29/3Hz, 18i-5/59/6Hz as well as NTSC-M/PAL and 96H video standards. The PT51 is also compatible with other analogue HD transmission formats. Control and status registers are written to and read from using a conventional 8 bit wide microprocessor interface. PT51 also supports the bidirectional transfer of data between acvi transmitter and receiver. The intellectual property block is provided as RTL compliant Verilog-21 source code for FPGAs from all vendors or for ASICs. Typical resource usage for an Altera FPGA is shown in Table 1 (as compiled for an EP4CE15 FPGA used on the SM8 PT51 evaluation board). Logic Cells Memory Bits M9K blocks 9x9 Multipliers 18x18 multipliers 12528 276598 53 56 21 276598 53 Table 1 PT51 Altera FPGA resource requirements An approximate equivalent for ASIC resource usage is 21 LCs (logic cell only compile for Altera FPGA) x 14 ~ 294k 2 input NAND gate equivalent. The memory is 26k of single port ROM and the balance is single port RAM. Page 6 of 52

2. PT51 Module description The PT51 acvi decoder IP core comprises 16 Verilog modules in a hierarchical structure (see Table 2). PT51_decoder.v Register_control.v AA_Filter.v Demod.v DemodLPF.v SPG.v Comb_filter Delay.v Remod.v Procamp.v Data.v Measure.v Table 2 PT51 Verilog file structure. SinCos_ ROM.v DDS_ROM.v ram_infer_generic.v ACC_Remod_LUT.v The top level file is PT51_decoder.v which, in turn, calls 15 of the other modules. Demod.v calls a third level file, SinCos_ROM.v, SPG.v calls DDS_ROM.v, Comb_filter.v calls ram_infer_generic.v and Remod.v calls ACC_Remod.LUT.v. Page 7 of 52

3. Signal Interconnections The PT51 signal interconnect diagram is shown in Figure 1. Figure 1 PT51 Block symbol. The signal descriptions are shown in Table 3, below. Signal Clock Clock2x DDS_clk Inputs Description The clock input from the voltage controlled oscillator (VCO) or Direct Digital Synthesisor (DDS) clock. See Table 5 for the required frequency for the various supported formats. Only the rising edge of this clock is used, so the mark space ratio is not critical. The 2x clock input from the VCO or DDS. See Table 5 for the required frequency for the various supported formats. The rising edge of this clock should be aligned with the rising edge of Clock. Clock input for the Direct Digital Synthesisor (DDS). Nominally 15MHz, it can be set to other values by changing the DDS seed value (Registers $4-$7). See Chapter 6. Page 8 of 52

RESETn CVBS_in[9:] A[6:] Din[] PT51_CSn PT51_WRn Signal Register_out[7..] Yout[9:] Cbout[9:] Crout[9:] Cmux Hout Vout Fout HBlank VBlank Gain_control VCO_PWM DDS_out[9:] Asynchronous active low reset signal. Asserting this input sets all the control registers to their default value and resets all registers. Input digital composite video from ADC. Data should be valid on the rising edge of the sample clock. This input should be straight binary (sync tip bottom ~ code, peak video white ~ code 123 ). Address bus input used to select the control register to be written to/read from. Control data input bus. Control chip select input, active low. Used in combination with the WRn input to control writing to the control registers. Active low write enable input. Used in combination with the CSn input to control writing to the control registers. Outputs Description Control output data bus. Outputs the control/status register data selected by the A[6:] bus. Y (luma) output from the encoder. The output is straight binary, blanking level is 64 1 and peak level nominally 96 1. The data output is valid at the rising edge of Clock. Yout[9] is the MSB. Cb (B-Y chroma) output from the encoder. The output is offset binary, blanking level is 512 1. The data output is valid at the rising edge of Clock when Cmux is high (37.125MHz data rate: 4:2:2 format). Cbout[9] is the MSB. Cr (R-Y chroma) output from the encoder. The output is offset binary, blanking level is 512 1. The data output is valid at the rising edge of Clock when Cmux is high (37.125MHz data rate: 4:2:2 format). Crout[9] is the MSB. Data valid output for Cb and Cr outputs. Cb and Cr data is valid on the rising edge of Clock when Cmux is high (4:2:2 data format). Cmux is 37.125MHz for acvi and 6.75MHz for NTSC/PAL. Horizontal sync output from decoder (active low). The falling edge of this output is the H timing reference (middle of analogue tri-level sync for HD or falling edge of bi-level sync for SD). Vertical sync output from decoder (active low). The falling edge of this output is Line 1 of the field. Frame sync output from decoder (low for field 1). Only valid during interlaced video formats. Horizontal blanking output from decoder. The duration of this pulse is the active video period of the standard (e.g. 128 pixels for 72p standards). Vertical blanking output from decoder. Pulse width modulated output for the control of the analogue input stage voltage controlled amplifier (AGC). See Chapter 5. Pulse width modulated output for the control of external voltage controlled oscillator frequency (VCO control voltage). See chapter 6. Nominal 27MHz sinewave output at 15MHz sample rate (DDS_clk rate). The output is a 1 bit signed number. (See Chapter 6). Page 9 of 52

Data_out acvi_test[1:] Data output to be inserted into the acvi signal for transmission from receiver to transmitter. See Chapter 9. Do not connect. The Verilog instantiation of PT51 is shown below: // Instantiate acvi decoder (PT51) Table 3 PT51 Input/Output signals PT51_decoder PT51_decoder_inst (.Clock(Clock_sig),.Clock2x(Clock2x_sig),.DDS_clk(DDS_clk_sig),.RESETn(RESETn_sig),.CVBS_in(CVBS_in_sig),.A(A_sig),.Din(Din_sig),.PT51_CSn(PT51_CSn_sig),.PT51_WRn(PT51_WRn_sig),.Register_out(Register_out_sig),.Yout(Yout_sig),.Cbout(Cbout_sig),.Crout(Crout_sig),.Cmux(Cmux_sig),.Hout(Hout_sig),.Vout(Vout_sig),.Fout(Fout_sig),.HBlank(HBlank_sig),.VBlank(VBlank_sig),.Gain_control(Gain_control_sig),.VCO_PWM(VCO_PWM_sig),.DDS_out(DDS_out_sig),.Data_out(Data_out_sig),.aCVi_test(aCVi_test_sig) ); // input Clock_sig // input Clock2x_sig // input DDS_clk_sig // input RESETn_sig // input [9:] CVBS_in_sig // input [6:] A_sig // input [] Din_sig // input PT51_CSn_sig // input PT51_WRn_sig // output [] Register_out_sig // output [9:] Yout_sig // output [9:] Cbout_sig // output [9:] Crout_sig // output Cmux_sig // output Hout_sig // output Vout_sig // output Fout_sig // output HBlank_sig // output VBlank_sig // output Gain_control_sig // output VCO_PWM_sig // output [9:] DDS_out_sig // output Data_out_sig // output [1:] acvi_test_sig Figure 2 shows the interconnections between the PT51 IP core and the voltage controlled oscillator and analogue front end/adc. The analogue front end/adc requirements are discussed in detail in chapter 5 and the clock generator in chapter 6. Page 1 of 52

Figure 2 PT51 IP core interconnections. Page 11 of 52

4. acvi Overview The following is a brief overview of the acvi interface. The basic concept of the acvi interface is to build on the proven and reliable transport method of NTSC, (the advantages of PAL v.v. multi-path reception is not relevant to a cable system so NTSC is used as the model). NTSC transmissions are capable of transmitting more than 1km across RG-59 cable but the bandwidth is limited to 5MHz. Because the cable system is a closed system, it is only necessary for the transmitter and receiver to understand each other and we can modify the basic NTSC method to suit HD transmissions. According to the SMPTE-296M specification, HD (74.25MHz sampling) video transmission requires a luma bandwidth of 3MHz and chroma bandwidth of 15MHz. To save on system costs acvi supports the 3MHz luma bandwidth but constrains the chroma bandwidth to 7.5MHz (4:1:1 sampling). The colour difference signals are modulated onto a carrier in quadrature so they effectively use the same bandwidth: the chroma subcarrier is ~24.75MHz.. The high frequency luma and the modulated chroma overlap above 12.4MHz but because of the line to line phase relationship of the chroma, may be separated using a line comb filter (and also because of the use of single chip image sensors, there is usually little high frequency content to cause image artifacts). The effective bandwidth of the complete signal is therefore approximately 12.3MHz (chroma upper sideband + filter roll off) + 24.75MHz or about 37MHz, setting a minimum sampling frequency of 2 x 37MHz or 74MHz. For convenience we choose 74.25MHz as a sampling frequency as this is related to the SMPTE272M standard; (see Figure 3). For transmission over 3m of RG-59 cable we can expect 18dB loss at higher frequencies (6.2dB/1m @ 5MHz). However the synchronizing signals are at a much lower frequency where the loss is only about 1-2dB so reliable rastering of the received signal should always be assured. The peak to peak video level of acvi is 1.26V (1% colour bars) which maintains compatibility with any legacy SD equipment on the network and also allows common low-power 3.3V drivers to be used. Table 4 lists the currently supported video formats for acvi. Format Pixels/line Line F SC /F H Subcarrier frequency ratio 72p/25Hz 396 18.75kHz 132.5 24.759375MHz 72p/3Hz 33 22.5kHz 11.5 24.76125MHz 72p/5Hz 198 37.5kHz 66.5 24.76875MHz 72p/59.94Hz 1 165 44.955kHz 55.5 24.74775226MHz 72p/6Hz 165 45.kHz 55.5 24.7725MHz 18p/24Hz 275 27.kHz 916.5 24.7455MHz 18p/25Hz 264 28.125kHz 88.5 24.764625MHz 18p/29.97Hz 1 22 33.716kHz 734.5 24.7389411MHz 18p/3Hz 22 33.75kHz 733.5 24.755625MHz 18i/5Hz 264 28.125kHz 88.5 24.764625MHz 18i/59.94Hz 1 22 33.716kHz 734.5 24.7389411MHz 18i/6Hz 22 33.75kHz 733.5 24.755625MHz 1 Input clock is 148.3516484MHz (else 148.5MHz). Table 4 acvi supported video formats. Page 12 of 52

Figure 3 acvi Spectrum. Page 13 of 52

5. Analogue Front End Figure 7 shows the analogue front end (AFE) for the PT51 evaluation board (SM8). The board can accept either twisted pair differential inputs (J1) or single ended coaxial inputs (J2). For the latter, the coaxial input has a pseudo-differential input, giving some degree of low frequency noise rejection (e.g. hum). Figure 4 acvi input levels The transmitter acvi voltage levels (for a 1% colour bar input) are shown in Figure 4. The sync, luma and colour modulation depth are similar to PAL which permits a common front end design to be utilized. The analogue front end is designed to accommodate a +3dB overhead on this signal to allow over-range inputs without clipping. U9 and U15 convert the (pseudo) differential inputs to a single ended output with a gain of x1 (U8 compensates for the 6dB attention through U15). U1 is a programmable gain amplifier that is controlled by the PWM input signal, Gain_control, which in turn is controlled by register $4 of the PT51 (manual gain) or by the automatic gain control (AGC) loop. The VGA loop is shown in Figure 5. The digital CVBS signal is low pass filtered in the SPG module to remove high frequency noise and chroma and the most negative video value (negative sync tip) and the back porch value are measured to give the sync pulse amplitude. The measured sync amplitude is compared with a reference value (the db sync amplitude) to produce a correction gain value. The filtering of the sync amplitude measurement, and the external analogue low pass filter, set the response time of the AGC loop. The gain response curve of the AD8337 is shown in Figure 6. Page 14 of 52

Figure 5 AGC Control loop. Figure 6 AD8337 PGA gain response. The gain correction is then converted to a PWM signal, which is low pass filtered externally to the PT51 (by R41 and C5) to convert it to an analogue control voltage. The AD8337 provides a +18dB control range. Note that the AGC relies on the maintaining of the correct sync to video ratio (3/7) and if this ratio is not maintained the video may not be compensated for correctly or may clip. The output of the PGA is then clamped to ensure the video signal is scaled through the ADC correctly under large variations in average picture level (APL). The bottom reference of the ADC is used as a reference to clamp the most negative part of the input signal, using an ideal diode formed by D5 and U11-B. The black level restoration is performed digitally in the PT51 decoder. Page 15 of 52

The clamped video is then digitized in a 1 bit ADC, U19, an AD9215, which is clocked at 74.25MHz for acvi and 27MHz for NTSC/PAL (see Figure 8). The output from the ADC is straight binary coded 1-bit digital CVBS video. To ease the requirements of an analogue anti-aliasing filter for NTSC/PAL operation, the ADC is over-sampled at 27MHz/36MHz. The PT51 low pass filters this in an anti-aliasing filter to remove out of band components and allowing the video input to be decimated to 13.5MHz, the clock frequency of the PT51 in NTSC/PAL mode. The anti-aliasing filter is bypassed in acvi mode. Page 16 of 52

Figure 7 Analogue Front End schematics. Page 17 of 52

Figure 8 ADC schematics. Page 18 of 52

6. Synchronisation modes The PT51 needs to produce a line locked output that is to say, a video output pixel must appear at the same point in time relative to the recovered horizontal sync pulse. Failure to do so will mean vertical edges will be jagged. To do this, it is necessary that the PT51 clocks can be moved in phase so that they align with the horizontal sync input edge. The clock rates for the supported video standards are shown in Table 5. Clock NTSC/PAL NTSC-96/PAL-96H acvi ADC clock 27MHz 36MHz 74.25MHz 1 PT51 Clock 13.5MHz 18MHz 74.25MHz 1 PT51 Clock2x 27MHz 36MHz 148.5MHz 2 Table 5 PT51 and ADC sample rates. 1 Clock frequency = 74.17582418MHz for 29.97Hz and 59.94Hz field rate standards. 2 Clock frequency = 148.3516484MHz for 29.97Hz and 59.94Hz field rate standards. The PT51 provides two methods to produce a line-locked clock: 1. The PT51 provides a VCO_PWM output which can be filtered to produce an analogue control voltage to control the frequency of a voltage controlled oscillator (VCO). 2. The PT51 provides a digitally generated sinewave which can be changed in frequency to produce a line locked clock. The digital sinewave is converted to analogue in a digital to analogue converter (DAC), filtered, and thresholded to provide a variable frequency clock. The PT51 SPG module extracts the horizontal sync signals from the composite CVBS inputs. The SPG module also divides the Clock input to produce a signal at the same approximate frequency as the horizontal line pulse. For example, for 72p/6Hz, dividing the 74.25MHz clock by 165 (the number of pixels/line according to the video standard) produces 45kHz, the line frequency of the 72p/6Hz standard. The SPG modules then compares the phase of this 45kHz signal and the recovered horizontal sync signal. The error in phase is then used to adjust the frequency of the Clock input such that the two falling edges of the signals align. When this occurs the horizontal input sync and the Clock will be in phase and we will have a line-locked output. In synchronizing mode 1 (VCO mode) the phase error word generated in the SPG module is converted to a pulse width modulated (PWM) which is converted to analogue voltage to control the frequency of the VCO. The external VCO circuit used in the PT51 evaluation board (SM8) is shown in figure 9. The PWM signal is low pass filtered (R11 and C32) and buffered (U7), to become the analogue control voltage to a VCXO (voltage controlled crystal oscillator). This nominal 27MHz oscillator is multiplied in a fractional PLL (U2) to 74.25MHz or 74.18MHz (to provide support for 29.97/59.94Hz formats). This clock is further divided to produce the 13.5MHz for the NTSC/PAL. It is also multiplied by 2x to produce the Clock2x input to the PT51. Page 19 of 52

Figure 9 External VCO schematic. A VCXO is used on the SM8 PT51 evaluation board; its specification may be found in Appendix A. However any oscillator may be used that meets the stability requirement. The pull range of VCXO is limited, which means that some out-of-range NTSC/PAL inputs cannot be locked to because we cannot adjust the frequency of the VCXO more than ±15ppm (±.15%). To accommodate all NTSC/PAL signal sources, including mechanically scanned sources such as VCR or laserdisc, a pull range of ±7% should be designed for. For the comb filter to separate the chroma and luma properly, and to reduce the jitter on the chroma vectors to less than 1 (the broadcast NTSC/PAL specification), the clock jitter should be less than 1/(4.4335MHz [PAL subcarrier frequency] x 36) = 626ps. This is the short term jitter, which for the comb filter requirement is 2/15.625kHz = 128µs (the aperture of the PAL comb filter is 2 horizontal lines/field): i.e. the short term (128µs) peak jitter of the VCO should be <.6ns. In synchronizing mode 2, the phase error word is added to a seed word which runs a 32 bit ratio counter. 27MHz DDS_seed Clock 32 DDS_clk 2 The DDS clock input is nominally 15MHz and the desired output frequency is 27MHz so the seed value is 27/15 x 2 32 = 77394113 1. The seed is programmable to accommodate different DDS_clk input frequencies. The top bits of the phase word address a sinewave look-up table and the output of this is the DDS_out waveform. The DDS-out nominal 27MHz sinewave is converted to analogue using a high speed DAC and the analogue output filtered to remove aliases. The resulting sinewave is then converted to a 27MHz clock using a comparator. The DDS schematic used on the SM8 evaluation board is shown in Figure 1. The 27MHz clock is then fed to the PLL to derive the Clock and Clock2x frequencies in the same way as the VCO mode. Page 2 of 52

Figure 1 DDS Clock generation schematic. Page 21 of 52

7. Technical Overview A simplified block diagram of the PT51 acvi decoder is shown in Figure 11. Figure 11 PT51 Block diagram. The acvi input from the ADC is straight binary coded at 1-bit resolution. The sample rates for the ADC and PT51 decoder are summarized in Table 5. Analogue clamping prior to the ADC ensures the most negative value of the input signal (the sync tips) are clamped to the negative reference of the ADC (code value ). The following is a brief description of each Verilog module. 7.1 PT51_decoder.v This is the top level module for the PT51. It provides the interconnection between all the other modules. 7.2 Register_control.v A conventional 8 bit microprocessor style control is used to write and read to the PT51 control registers. Details of the interface may be found in Chapter 1 and the register descriptions may be found in Chapter 11. Page 22 of 52

7.3 AA_Filter.v The SD video inputs are over-sampled (at 27MHz or 36MHz) to ease the requirements of any analogue anti-aliasing filter. For SD operation therefore, the ADC input is low pass filtered so it may be decimated to a 13.5MHz/18MHz sampling rate. The response of this filter for NTSC/PAL is shown in Figure 12. For acvi operation, this filter is bypassed. Inphase Filter Frequency Response 5 Magnitude in db -5-1 -15-2 -25-3 -35-4 2 4 6 Frequency in MHz 8 1 Figure 12 Anti-aliasing filter. 7.4 Demod.v A free-running subcarrier frequency is generated using a 32 bit ratio counter clocked from the input clock. ratio Fsc θsc subcarrier seed phase change per line pixels per line Clock frequency 36 2 32 The free-running frequency of the subcarrier depends on the colour standard; (see table 6). Format 72p/251 72p/31 72p/51 72p/592 72p/61 18p/241 18p/251 18p/292 18p/31 18i/51 18i/592 18i/61 Pixels/line 396 33 198 165 165 275 264 22 22 264 22 22 Line frequency 18.75kHz 22.5kHz 37.5kHz 44.955kHz 45.kHz 27.kHz 28.125kHz 33.716kHz 33.75kHz 28.125kHz 33.716kHz 33.75kHz FSC/FH ratio 132.5 11.5 66.5 55.5 55.5 916.5 88.5 734.5 733.5 88.5 734.5 733.5 Subcarrier 24.759375MHz 24.76125MHz 24.76875MHz 24.74775226MHz 24.7725MHz 24.7455MHz 24.764625MHz 24.7389411MHz 24.755625MHz 24.764625MHz 24.7389411MHz 24.755625MHz Seed value 555D9BACH 555F4356H 5565E22H 55693156H 55693156H 55515C88H 5561BED6H 555A4C56H 555A4C56H 5561BED6H 555A4C56H 555A4C56H Page 23 of 52

Format Pixels/line NTSC-M3 858 PAL3 864 NTSC-96H4 1144 PAL-96H4 1152 1 Clock frequency = 74.25MHz 2 Clock frequency = 74.17582418MHz 3 Clock frequency = 13.5MHz 4 Clock frequency = 18MHz Line frequency 15.734kHz 15.625kHz 15.734kHz 15.625kHz FSC/FH ratio 227.5 283.75 + (1/625) 227.5 283.75 + (1/625) Subcarrier 3.5795455MHz 4.43361875MHz 3.5795455MHz 4.43361875MHz Seed value 43EF83DH 54121596H 32E8BA39H 3FE53H Table 6 PT51 Line and subcarrier frequencies The top 11 bits of this ratio counter (the phase word) are used by the demodulator to generate the sine and cosine waveforms. For the demodulation to correctly operate the generated subcarrier must be frequency and phase locked to the CVBS video subcarrier which is done by measuring the amplitude of the demodulated and low pass filtered V output during the colour burst. If the frequency and phase of the free-running subcarrier and the colour burst are the same then this error will be zero. The reference for the BLO is the demodulated and filtered V output from the demodulator low pass filter; 32 samples of this waveform are taken during the burst pulse (16 for NTSC/PAL); the burst gate pulse from the SPG is used for this purpose. The seed word is modified using the phase error signal until the input colour burst and the ratio counter are phase locked. The NTSC/aCVi chroma signal is originally generated as follows: chroma U sin ωt V cos ωt When the burst lock loop (BLO) is in lock, the frequency and phase will be the same as when the signal was being modulated. Thus, multiplying the CVBS composite video by the sine and cosine of the same frequency and phase gives the following: U' U sin ωt V cos ωt sin ωt U' U sin2 ωt V sin ωt cos ωt 1 cos 2 ωt V U' U 2 2 sin ωt cos ωt 2 U' U U cos 2 ωt V sin 2 ωt 2 2 2 and for the V component: Page 24 of 52

V' U sin ωt V cos ωt cos ωt V' U sin ωt cos ωt V cos 2 ωt V' U 1 cos 2 ωt 2 sin ωt cos ωt V 2 2 V' U sin 2 ωt V V cos 2 ωt 2 2 2 The lower 9 bits of the 11-bit phase output from the BLO (burst locked oscillator) are used to address a sine and cosine lookup table (SinCos.v). These 9 bits comprise the phase angle, at subcarrier frequency, within a single quadrant and the top two bits are the quadrant this method saves memory by only requiring a single quadrant of sin and cos values to be stored in the LUT. The output of the Sin/Cos LUT is a 24 bit word; 12 bits cosine and 12 bits sine. The quadrant signs are used to manipulate the sine and cosine data such as to construct a full waveform. The reconstructed sine and cosine waveforms are then multiplied by the input CVBS composite video from the ADC. The output of the sine channel is the demodulated U signal and the cosine channel is the demodulated V output. One over-range bit allows for twice subcarrier frequency components (removed by the subsequent low pass filter). The amplitude of the chroma burst from the demodulation low pass filter is also measured and compared with the amplitude at nominal -db input levels. If the ACC is enabled (Control register 3, bit 2) the output of the demodulator is gain corrected (chroma automatic gain control). The chroma inputs to the remodulator are also compensated for to ensure the demodulator/remodulator gain = db and the chroma is correctly cancelled from the composite input. The chroma gain correction factor for the remodulator (a reciprocal function) is calculated using the ACC_Remod_LUT lookup table. 7.5 DemodLPF.v The output of the demodulator also comprises twice subcarrier frequencies. The output is therefore low pass filtered using a 47 tap filter, the response for which is shown in Figure 13 (for acvi standards at 74.25MHz clock frequency), Figure 14 (for NTSC/PAL standards at 13.5MHz clock frequency) and Figure 15 (for 96H operation at 18MHz clock frequency). The output of the filter is the clean simple demodulated U and V. Page 25 of 52

Inphase Filter Frequency Response Magnitude in db -1-2 -3-4 -5-6 4 8 12 Frequency in MHz 16 2 Figure 13 Chroma demodulator low pass filter (acvi operation). Inphase Filter Frequency Response 5-5 Magnitude in db -1-15 -2-25 -3-35 -4-45 -5-55 -6 1 2 3 Frequency in MHz 4 5 Figure 14 Chroma demodulator low pass filter (NTSC/PAL) Page 26 of 52

Inphase Filter Frequency Response 1 Magnitude in db -1-2 -3-4 -5-6 -7-8..5 1. 1.5 2. 2.5 Frequency in MHz 3. 3.5 4. Figure 15 Chroma demodulator low pass filter (96H) 7.6 Delay.v The CVBS input is passed through a programmable 23 tap FIR filter. The response of this filter for acvi inputs is shown in Figure 16. For other analogue HD standards, this filter acts as the low pass filter to separate the (non-overlapping) luma and chroma (see Figure 17). The filter response is selected using Control Register 2, bit 6. Quantized Inphase Filter Frequency Response 5 Magnitude in db -5-1 -15-2 -25-3 -35-4 -45 4 8 12 16 2 24 Frequency in MHz 28 32 36 Figure 16 Luma low pass filter - default parameters. Page 27 of 52 4

Inphase Filter Frequency Response 5-5 Magnitude in db -1-15 -2-25 -3-35 -4-45 -5 4 8 12 Frequency in MHz 16 2 Figure 17 Y Filter response (12MHz). 7.7 Comb_filter.v Because the higher luma frequencies and the modulated chroma frequencies overlap (for NTSC/PAL and acvi) a line comb filter is used to separate them. This is possible because the chroma subcarrier has a fixed phase relationship with respect to the horizontal line frequency (see Table 6) whereas the high frequency luma does not. For example, for NTSC, the subcarrier frequency is 227.5 times the horizontal frequency, meaning there is a 18 phase shift in the subcarrier for every line of a field. The low pass filtered U and V video are delayed in two line delay memories. For acvi and NTSC the current and the two delayed components are added together in a 1/4*H + 1/2*1H + 1/4*2H filter. For PAL the comb filter is (1/4*HU + 1/2*1HU + 1/4*2HU) + [(HV 2HV) * PALswitch] and (1/4*HV + 1/2*1HV + 1/4*2HV) + [(HU 2HU) * PALswitch] where the PAL switch contribution is crosstalk cancellation and allows the PAL comb to have the same 2 line aperture as NTSC (because of the additional 9 colour burst switch in PAL, usually a 4 line comb is required). For the comb filters to operate correctly the phase relationship of the colour component must be maintained; if not the HF luma will not be cancelled and can even be reinforced. It is therefore necessary to detect when the comb filter fails and switch to a better mode. The decision on the comb mode is made on a pixel by pixel basis using the amplitude differences of the Y, U and V components across the line comb filter aperture. Because the Y input still has chroma on it, it is low pass filtered in a 15 tap FIR filter, whose response is shown in Figure 18. Page 28 of 52

Inphase Filter Frequency Response -5 Magnitude in db -1-15 -2-25 -3-35 -4 1 2 3 Frequency in MHz 4 5 Figure 18 Comb filter luma LPF. In SD video mode, if the comb filter fails, a large portion of the luma signal (subcarrier frequency ± the demodulation filter response) is removed which gives very soft images with high levels of cross-colour. To alleviate this the chroma signal is low pass filtered using a ¼,,,, ½,,,, ¼ low pass filter (13.5MHz sampling). The comb mode (line comb or notch mode) can be forced using control register 2 and also, the comb mode selected in adaptive mode may be viewed. The comb filter may also be bypassed for formats where the luma and chroma are non-verlapping. The combed U and V outputs from the filter are input to the processing amplifier and also to the Remod.v module. 7.8 Remod.v The combed U and V components are then frequency shifted back to the subcarrier frequency using the delayed sine and cosine waveforms from the Demod.v module, added together to create a chroma component (which in line comb module will contain no high frequency luma information) and subtracted from the composite video to form a clean luma signal. The complementary nature of this architecture ensures there is no missing information from the final luma output. For example, if the line comb is operating correctly, the U and V outputs of the comb filter will be chroma only, with no high frequency luma. When this is subtracted from the CVBS signal, only the chroma is removed leaving the high frequency luma. 7.9 SPG.v A fixed offset is subtracted from the CVBS video such that the midpoint of the sync pulse is at value. The horizontal counter addresses a look up table whose output coefficients form an FIR low pass filter to remove chroma composite video. The coefficients are multiplied by the offset Page 29 of 52

video and accumulated across the aperture of the filter, being updated once per horizontal line. The frequency response of the sync filter for HD standards is shown in Figure 19 and for SD standards is shown in Figure 2. Inphase Filter Frequency Response 1 Magnitude in db -1-2 -3-4 -5-6 4 8 12 Frequency in MHz 16 2 Figure 19 Phase detector low pass filter response (HD standards). Inphase Filter Frequency Response 5-5 Magnitude in db -1-15 -2-25 -3-35 -4-45 -5-55 -6 1 2 3 Frequency in MHz 4 5 Figure 2 Phase detector low pass filter response (SD standards). When the midpoint of the falling edge of the horizontal pulse is coincident with the centre tap of the FIR filter the accumulated result will be zero. When they are not coincident an error will be generated. This error is filtered using a recursive filter (integrator) and proportional and integral Page 3 of 52

terms are added to create an error word which is both converted to a PWM signal to control an external voltage controlled oscillator (VCO) or added to the seed word for the DDS sinewave generator. (See chapter 6.) The horizontal pixel counter is used by the SPG, (sync pulse generator), to provide the horizontal timing pulses required by the decoder, including the burst gate pulse for the demodulator, which must lie in the centre of the colour burst signal.. The CVBS video is filtered in a 15-tap FIR filter to remove the chroma and the vertical field pulses are recovered by using a digital integrator on the sliced filtered video. The response of the vertical sync filter (for HD clock frequencies) is shown in Figure 21. Inphase Filter Frequency Response 5-5 Magnitude in db -1-15 -2-25 -3-35 -4-45 -5 2 4 6 Frequency in MHz 8 1 Figure 21 Vertical sync recovery filter (HD standards). The SPG also detects the input video standard. The number of field pulses/second, the number of lines/field, whether interlace is detected and the number of pixels/line are all used to determine the input standard. The resulting default values for each standard are then automatically loaded into the appropriate registers (in auto-register mode). 7.1 Procamp.v The combed luma is conditioned by the processing amplifier. First the black level offset (measured in the SPG module) is subtracted from the luma signal to set the black level at zero. The luma is then offset (to 64 code) and amplified to provide a 96 code (1 bit) output for a 75/1% colour bar input. The luma output is valid on the rising edge of the Clock. The low pass filtered chroma outputs are amplified separately to provide a nominal ±262.51 code output for a 75% colour bar input. The Cb and Cr outputs are offset binary, with the blanking level at 5121. The output is valid on the rising edge of the Clock when the Cmux output is 1. Page 31 of 52

The SPG also provides Vout (vertical field), Fout (frame ID for interlaced video) and Hout (horizontal) synchronizing pulses. 7.11 Measure.v The measure module provides the feedback for the automatic cable length compensation. The test waveform on Line 9 (acvi formats only see Figure 23) is used to provide the measure of the cable attenuation at high frequencies. 32 pixel wide gates are generated centred on the white, black and frequency burst parts of the waveform. The white and black gates accumulate the video values and then recursively filter the result. The frequency burst gate measures the peak positive and negative values of the video. The white black and peak positive peak negative values are calculated and differenced to give a measure of the high frequency attenuation of the video input. This measure is then used to modify the pre-emphasis gain in the transmitter via the data communication link (see Chapter 8). 7.13 Data.v This module provides the bi-directional data control to/from transmitter and receiver. The data transfer protocol is described in Chapter 9. Page 32 of 52

8. acvi Cable Compensation The following description only applies to acvi video. All cables attenuate high frequencies more than low frequencies. The coaxial cable illustrated in Figure 22 (type RG-59) is typical of that used and shows that, at 5MHz (the upper frequency of acvi is 37MHz) an attenuation of 6.2dB/1m. acvi compensates for the frequency loss by applying pre-emphasis to the transmitted signal as this avoids the problem of providing tunable high frequency gain at the receiver which will also boost noise. To avoid the impracticality of boosting the high frequencies, the low frequencies are attenuated. The frequency response of the filter is closely matched to that of the cable attenuation so at the receiver it is only necessary to apply flat gain. The pre-emphasis filter is in the digital domain so it easy to change for different cable types and no external frequency dependent analogue networks, at either the transmitter of receiver, are necessary. Figure 22 Coaxial cable frequency response. To adjust the amount of pre-emphasis, a test waveform is inserted by the transmitter into the acvi signal on line 9 (for all supported video standards). The waveform allows the differential measurement of low and high frequencies across the cable, which is measured in the PT51 and used to control, via a data link, the degree of pre-emphasis applied at the transmitter. The waveform is shown in Figure 23. Page 33 of 52

Figure 23 Insertion test signal. The waveform comprises a white and black reference level, the amplitude of which is also the amplitude of the frequency burst. The frequency burst is a 24.75MHz sine wave (74.25/3 MHz). The difference between the white black amplitude and the peak-to-peak amplitude of the frequency burst allows the calculation of the cable attenuation at 25MHz and therefore the amount of preemphasis that needs to be applied. The degree of pre-emphasis required for the cable is transmitted from the receiver (PT51) to the transmitter (PT55) on line 8 during the vertical blanking interval. The format of the data transfer is the same as that used by the data transfer described in Chapter 9. The instruction word is set to 5 for the pre-emphasis value and the data byte is the degree of compensation, being no preemphasis and 255 being the maximum pre-emphasis. Figure 24 shows the acvi waveform with no pre-emphasis applied. Figure 25 shows the acvi waveform with maximum pre-emphasis. Figure 24 acvi output, 3MHz sweep (Pre-emphasis = minimum). Page 34 of 52

Figure 25 acvi output, 3MHz sweep (Pre-emphasis = maximum). Page 35 of 52

9. Data Transfers The following description only applies to acvi video. The acvi interface supports the bi-directional transfer of data between receiver and transmitter. The format of the data is a 4 bit instruction word and an 8 bit data word. The instruction and data are not defined and may be set by the user. Each word is sent once per field/frame, so, for example, 6 words may be sent in each direction for the 72p/6 standard. To transmit data from receiver to transmitter, first the instruction word (C3-C in Figure 26) is written to Register $51. Next the data byte (D7-D in Figure 26) is written to Register $5. Register $52 should be read and bit (data busy) examined. If this bit is 1 the previously data transfer is still in progress, if then the transfer may be initiated by writing any data to Register $52. The data is sent on Line 12 of the vertical blanking interval for all acvi standards. After the transmit data request the word is formatted as shown in Figure 26 and transmitted on the next line 12. After transmission the data busy bit is reset. Figure 26 Data transfer protocol. Figure 27 shows the schematic used on the PT51 evaluation module (SM8) to insert the transmitted data into the acvi video input. U16 is a fast buffer amplifier. It is enabled or disabled by the signal on pin 5 which is connected to the Data_out output of the PT51. The resulting voltage is converted to a current by R53 which then inserts the data waveform onto the blanking level of the acvi video on Line 12. The data rate of the transfer is slow enough to be valid even before the cable compensation has settled. Page 36 of 52

Figure 27 PT51 Data insertion schematic. The data received from the transmitter is the same format as the transmitted data (Figure 26). The Data.v module slices the acvi digital data from the ADC and examines it for the header flag. The transmitter to receiver data is inserted on Line 13. Once the header flag is detected, a bit clock is synchronized to the data and the data stream is decoded into the instruction word, data word and parity checks. To read data, first Register $55, bit 7 should be examined if 1 it indicates new data has been received (and the received data parity check is OK). Register $55 also shows the status of the received instruction and data word parity. Next the received instruction word should be read from Register $54, and then the received data word from Register $53. When Register $53 is read the new data flag (Register $55 bit 7) is reset. When the new data bit is set new received data will not be latched, preventing corruption of received data, but also possibly missing transmitted data if the data is not read often enough. Page 37 of 52

1. Register interface Figure 28 shows the timing diagram for the register interface; it is a conventional microprocessor interface. Each register is selected via a 7 bit address bus. Writes to unused register locations are ignored. To write to the selected register the PT51_CSn (chip select) input must be asserted low and the A[6:] register address and the data for this register set up. The PT51_WRn input must then be driven low and high again: On the rising edge of this pulse the data is latched into the address selected. The PT51_CSn input should then be returned high. For the write to occur reliably the address (A[6:]) and data (Din[]) must be stable and valid during the low to high transition of the PT51_WRn pulse. The address input also selects the register data that is presented on the Register_out[] bus. This output is independent of the PT51_CSn or PT51_WRn inputs. Figure 28 PT51 Register timing. Page 38 of 52

11. Register descriptions Table 7 lists all of the control and status registers. All of the registers are 8 bit; unused register bits read back as zeros. Please note that some registers can be set to values that are illegal and will produce invalid outputs. Asserting the RESETn input resets the PT51 registers to their default values. Register Offset Register Name Bit Value Description Control Registers $ Control_1 Auto register 7 Auto standard 6 S96H 5 SD_HDn 4 Manual standard $1 Control_2 View comb mode 3: 7 Y Filter select 6 Auto comb mode 5 4 Manual comb mode (Luma) 3:2 Manual comb mode (UV) 1: If set to 1 (default value) the parameter values are set to their default values depending on the video standard (note: only those standards listed in bits [3:] have default values assigned). If set to, Registers $2-$4F may be programmed manually. If reset to the video standard is preset manually using bits 5:. If set to 1 (default value) the detected video standard together with the detected SD/HD format and the manually set. The S96H bit selects between NTSC/PAL and 96H formats or acvi and acvi.5 formats. If set to and the SD_HDn is set to a 1 the PT51 is set to NTSC/PAL mode, else 96H format is selected. If set to and the SD_HDn is set to a the PT51 is set to acvi mode, else acvi.5 mode is selected. If Auto_standard is set to : If SD_HDn set to the PT51 is set to HD (acvi) mode. If set to 1 the PT51 is set to SD (NTSC/PAL) mode. If Auto_standard is set to 1 : SD or HD format is determined automatically and this register bit has no effect. Bits Video standard Video standard 3: (SD_HDn=) (SD_HDn=1) S96H= S96H= 1 S96H= S96H= 1 72p/25 NTSC-M NTSC-96H 1 72p/3 1 72p/5 72p/5 11 72p/59 1 72p/6 72p/6 PAL PAL-96H 11 18p/24 11 18p/25 18p/25 111 18p/29 1 18p/3 18p/3 11 18i/5 11 18i/59 111 18i/6 If set to 1 this bit enables the auto comb mode selection to be displayed. If set to the video output is shown. If set to, the luma filter is set to 29.7MHz passband bandwidth (acvi and SD mode). If set to 1 the filter is set to 12MHz passband (other analogue HD standards). Not used If set to 1, the comb mode is set automatically depending on the comb failure detection logic. If set to the comb mode is manually set using the manual comb mode bits. Bit 1 Bit If the auto comb mode is set to. Forces low pass mode. 1 Forces line comb mode 1 Bypasses line comb 1 1 Not defined Bit 1 Bit If the auto comb mode is set to. Forces low pass mode. Page 39 of 52

Register Offset $2 Register Name Control_3 Bit Value 7 5:4 Enable CC 3 ACC 2 AGC 1 ABL $3 PD_gain $4 $5 $6 $7 DDS_seed_1 DDS_seed2 DDS_seed_3 DDS_seed_4 Sub_Luma_value_ NTSC_1 Sub_Luma_value_ NTSC_2 Ygain_value_NTSC _1 Ygain_value_NTSC _2 Ugain_value_NTSC _1 Ugain_value_NTSC _2 Vgain_value_NTSC _1 Vgain_value_NTSC _2 1: 1: 1: 1: $8-$F $8 $9 $A $B $C $D $E $F $1-$18 $1 $11 $12 Sub_Luma_value_ PAL_1 Sub_Luma_value_ PAL_2 Ygain_value_PAL_ 1 1: Description 1 Forces line comb mode 1 Bypasses line comb 1 1 Not defined Bypasses the sample rate converter if set to 1. Else the SRC mode is controlled by bit 6. Bits [5:4] VCO_PWM output Error output (VCO lock mode) 1 Force VCO_PWM output to. 1 Force VCO_PWM output to 1. 11 Force VCO_PWM output to 5%. Enables the automatic cable compensation (pre-emphasis value) if set to 1. Else the pre-emphasis correction value is set to (preemphasis off). Enables the automatic chroma gain control if set to 1. The burst amplitude is measured and compared with a reference and a correction gain is applied to the chroma demodulator outputs and to the remodulation chroma inputs. If set to a the chroma gain is preset to a nominal db level. Enables the automatic gain control if set to 1. The sync amplitude is measured and compared with a reference and a PWM output signal (Gain_control) is used to control an external voltage controlled amplifier (see chapter 5). If set to a the external voltage controlled amplifier gain is set manually using register $4 (PGA_control). Enables the automatic black level if set to 1. The back porch value is measured and subtracted from the composite video (effectively removing the sync pulses from the luma output). If ABL is turned off, a fixed DC offset set by registers $3 and $31 is subtracted from the output. DDS/PLL Control Control the gain of the PLL phase detector for both VCO and PLL mode. Default value is 321. If Control register 1, bit 7 is set to 1 the subcarrier frequency seed is preset according to the selected standard. If set to, the subcarrier frequency seed can be programmed manually using these 4 registers: ({FSc_1[], FSc_2[], FSc_3[], FSc_4[]}). The seed is a 32 bit number and FSc_1[7] is the MSB. Default value is 55693156H Procamp Proc-amp registers $8-$F apply if the video standard is NTSC-M (either manually or automatically set). Value subtracted from luma output (to remove synchronizing pulses), if ABL = (Control3[]). 1 bit word = ({Sub_Luma_value_NTSC_2[1:],Sub_Luma_value_NTSC_1[]}). Default value = 151. Luma gain control. 1 bit word = ({Ygain_value_NTSC_2[1:],Ygain_value_NTSC_1[]}). Default value = 7461. Chroma (B-Y) gain control. 1 bit word = ({Ugain_value_NTSC_2[1:],Ugain_value_NTSC_1[]}). Default value = 5121. Chroma (R-Y) gain control. 1 bit word = ({Ugain_value_NTSC_2[1:],Ugain_value_NTSC_1[]}). Default value = 5121. Proc-amp registers $1-$18 apply if the video standard is PAL (either manually or automatically set). Value subtracted from luma output (to remove synchronizing pulses), if ABL = (Control3[]). 1 bit word = ({Sub_Luma_value_PAL_2[1:],Sub_Luma_value_PAL_1[]}). Default value = 151. Luma gain control. 1 bit word = ({Ygain_value_PAL_2[1:],Ygain_value_PAL_1[]}). Default value Page 4 of 52

Register Offset $13 $14 $15 $16 $17 Register Name Bit Value Ygain_value_PAL_ 2 Ugain_value_PAL_ 1 Ugain_value_PAL_ 2 Vgain_value_PAL_ 1 Vgain_value_PAL_ 2 1: = 7461. 1: Chroma (B-Y) gain control. 1 bit word = ({Ugain_value_PAL_2[1:],Ugain_value_PAL_1[]}). Default value = 5121. 1: $18-$1F $18 1: $1A $1B Sub_Luma_value_ HD_1 Sub_Luma_value_ HD_2 Ygain_value_HD_1 Ygain_value_HD_2 1: $1C $1D Ugain_value_HD_1 Ugain_value_HD_2 1: $1E $1F Vgain_value_HD_1 Vgain_value_HD_2 1: $2 $21 Hcount_length_1 Hcount_length_2 3: $22 $23 Hout_start_1 Hout_start_2 3: $24 $25 Hout_end_1 Hout_end_2 3: $26 $27 HBlank_start_1 HBlank_start_2 3: $28 $29 HBlank_end_1 HBlank_end_2 3: $2A $2B Halfline_set_1 Halfline_set_2 3: $2C Burst_gate_start_ 1 Burst_gate_start_ 2 3: $19 $2D Description Chroma (R-Y) gain control. 1 bit word = ({Ugain_value_PAL_2[1:],Ugain_value_PAL_1[]}). Default value = 5121. Proc-amp registers $18-$1F apply if the video standard is HD (either manually or automatically set). Value subtracted from luma output (to remove synchronizing pulses), if ABL = (Control3[]). 1 bit word = ({Sub_Luma_value_HD_2[1:],Sub_Luma_value_HD_1[]}). Default value = 151. Luma gain control. 1 bit word = ({Ygain_value_HD_2[1:],Ygain_value_HD_1[]}). Default value = 7461. Chroma (B-Y) gain control. 1 bit word = ({Ugain_value_HD_2[1:],Ugain_value_HD_1[]}). Default value = 5121. Chroma (R-Y) gain control. 1 bit word = ({Ugain_value_HD_2[1:],Ugain_value_HD_1[]}). Default value = 5121. SPG If Control register 1, bit 7 is set to 1 Hcount Length is preset according to the selected standard. If set to, Hcount Length can be programmed manually using these 2 registers: ({Hcount Length_2[3:], Hcount Length_1[]}). The value is the total number of pixels per line - 1. If Control register 1, bit 7 is set to 1 Hout_start is preset according to the selected standard. If set to, Hout_start can be programmed manually using these 2 registers: ({Hout_start_2[3:], Hout_start_1[]}). The value is the position of the falling edge of the Hout sync pulse w.r.t. to the falling edge of the input horizontal sync pulse. If Control register 1, bit 7 is set to 1 Hout_end is preset according to the selected standard. If set to, Hout_end can be programmed manually using these 2 registers: ({Hout_end_2[3:], Hout_end_1[]}). The value is the position of the rising edge of the Hout sync pulse w.r.t. to the falling edge of the input horizontal sync pulse. If Control register 1, bit 7 is set to 1 HBlank_start is preset according to the selected standard. If set to, HBlank_start can be programmed manually using these 2 registers: ({HBlank_start_2[3:], HBlank_start_1[]}). The value is the position of the beginning of blanking w.r.t. to the falling edge of the input horizontal sync pulse. If Control register 1, bit 7 is set to 1 HBlank_end is preset according to the selected standard. If set to, HBlank_end can be programmed manually using these 2 registers: ({HBlank_end_2[3:], HBlank_end_1[]}). The value is the position of the end of blanking w.r.t. to the falling edge of the input horizontal sync pulse. If Control register 1, bit 7 is set to 1 Halfline_set is preset according to the selected standard. If set to, Halfline_set can be programmed manually using these 2 registers: ({Halfline_set_2[3:], Halfline_set_1[]}). The value is the position of the beginning of blanking w.r.t. to the falling edge of the input horizontal sync pulse. If Control register 1, bit 7 is set to 1 Burst gate start is preset according to the selected standard. If set to, Burst gate start can be programmed manually using these 2 registers: ({Burst_gate_start _2[3:], Burst_gate_start _1[]}). The value is the number of clocks after the falling edge of the input horizontal Page 41 of 52

Register Offset Register Name Bit Value $2E $2F Burst_gate_end_1 Burst_gate_end_2 3: $3 $31 Vout_start_1 Vout_start_2 2: $32 $33 Vout_end_1 Vout_end_2 2: $34 $35 Vout2_start_1 Vout2_start_2 2: $36 $37 Vout2_end_1 Vout2_end_2 2: $38 $39 Fout_start_1 Fout_start_2 2: $3A $3B Fout_end_1 Fout_end_2 2: $3C $3D VBlank_start_1 VBlank_start_2 2: $3E $3F VBlank_end_1 VBlank_end_2 2: $4 $41 VBlank2_start_1 VBlank2_start_2 2: Description sync pulse for the beginning of the burst gate. If Control register 1, bit 7 is set to 1 Burst gate end is preset according to the selected standard. If set to, Burst gate end can be programmed manually using these 2 registers: ({Burst_gate_start _2[3:], Burst_gate_start _1[]}). The value is the number of clocks after the falling edge of the input horizontal sync pulse until the end of the burst gate. If Control register 1, bit 7 is set to 1 the Vout_start is preset according to the selected standard. If set to, Vout start can be programmed manually using these 2 registers: ({Vout_start_2[2:], Vout_start_1[]}). The value is the number of horizontal lines after the falling edge of the vertical sync (field or frame if interlaced input) for the falling edge of the Vout output. If Control register 1, bit 7 is set to 1 the Vout_end is preset according to the selected standard. If set to, Vout end can be programmed manually using these 2 registers: ({Vout_end_2[2:], Vout_end_1[]}). The value is the number of horizontal lines after the falling edge of the vertical sync (field or frame if interlaced input) for the rising edge of the Vout output. If Control register 1, bit 7 is set to 1 the Vout2_start is preset according to the selected standard. If set to, Vout2 start can be programmed manually using these 2 registers: ({Vout2_start_2[2:], Vout2_start_1[]}). The value is the number of horizontal lines after the falling edge of the vertical sync (field or frame if interlaced input) for the falling edge of the Vout output for the interlaced field. For non-interlaced formats this register should be set to the same value as Vout_start. If Control register 1, bit 7 is set to 1 the Vout2_end is preset according to the selected standard. If set to, Vout2 end can be programmed manually using these 2 registers: ({Vout2_end_2[2:], Vout2_end_1[]}). The value is the number of horizontal lines after the falling edge of the vertical sync (field or frame if interlaced input) for the rising edge of the Vout output for the interlaced field. For non-interlaced formats this register should be set to the same value as Vout_end. If Control register 1, bit 7 is set to 1 the Fout_start is preset according to the selected standard. If set to, Fout start can be programmed manually using these 2 registers: ({Fout_start_2[2:], Fout_start_1[]}). The value is the number of horizontal lines after the falling edge of the vertical sync (field or frame if interlaced input) for the falling edge of the Fout output. This register is only valid for interlaced video formats. If Control register 1, bit 7 is set to 1 the Fout_end is preset according to the selected standard. If set to, Fout end can be programmed manually using these 2 registers: ({Fout_end_2[2:], Fout_end_1[]}). The value is the number of horizontal lines after the falling edge of the vertical sync (field or frame if interlaced input) for the rising edge of the Fout output. This register is only valid for interlaced video formats. If Control register 1, bit 7 is set to 1 the VBlank_start is preset according to the selected standard. If set to, VBlank start can be programmed manually using these 2 registers: ({VBlank_start_2[2:], VBlank_start_1[]}). The value is the number of horizontal lines after the falling edge of the vertical sync (field or frame if interlaced input) for the beginning of vertical blanking. If Control register 1, bit 7 is set to 1 the VBlank_end is preset according to the selected standard. If set to, VBlank_end can be programmed manually using these 2 registers: ({VBlank_end_2[3:], VBlank_end_1[]}). The value is the number of horizontal lines after the falling edge of the vertical sync (field or frame if interlaced input) for the end of vertical blanking. If Control register 1, bit 7 is set to 1 the VBlank2_start is preset according to the selected standard. If set to, VBlank2 start can be programmed manually using these 2 registers: Page 42 of 52

Register Offset Register Name Bit Value $42 $43 VBlank2_end_1 VBlank2_end_2 2: $44 $45 SVBlank_start_1 SVBlank_start_2 2: $46 $47 SVBlank_end_1 SVBlank_end_2 2: $48 $49 SVBlank2_start_1 SVBlank2_start_2 2: $4A $4B SVBlank2_end_1 SVBlank2_end_2 2: $4C $4D $4E $4F FSc_1 FSc_2 FSc_3 FSc_4 $5 $51 Tx Data word Tx Instruction word $52 Data transfer W 7:4 3: $52 Data busy R $53 Rx_Data_word R $54 Rx Instruction word Rx Parity R 3: $55 7:6 5 4 Description ({VBlank2_start_2[2:], VBlank2_start_1[]}). The value is the number of horizontal lines after the falling edge of the vertical sync (field or frame if interlaced input) for the beginning of vertical blanking for the interlaced field. This register is only valid for interlaced video formats. If Control register 1, bit 7 is set to 1 the VBlank2_end is preset according to the selected standard. If set to, VBlank2 end can be programmed manually using these 2 registers: ({VBlank2_end_2[2:], VBlank2_end_1[]}). The value is the number of horizontal lines after the falling edge of the vertical sync (field or frame if interlaced input) for the end of vertical blanking for the interlaced field. This register is only valid for interlaced video formats. If Control register 1, bit 7 is set to 1 the SVBlank_start is preset according to the selected standard. If set to, SVBlank start can be programmed manually using these 2 registers: ({SVBlank_start_2[2:], SVBlank_start_1[]}). The value is the number of horizontal lines after the falling edge of the vertical sync (field or frame if interlaced input) for the beginning of short vertical blanking. If Control register 1, bit 7 is set to 1 the SVBlank_end is preset according to the selected standard. If set to, SVBlank_end can be programmed manually using these 2 registers: ({SVBlank_end_2[3:], SVBlank_end_1[]}). The value is the number of horizontal lines after the falling edge of the vertical sync (field or frame if interlaced input) for the end of short vertical blanking. If Control register 1, bit 7 is set to 1 the SVBlank2_start is preset according to the selected standard. If set to, SVBlank2 start can be programmed manually using these 2 registers: ({SVBlank2_start_2[2:], SVBlank2_start_1[]}). The value is the number of horizontal lines after the falling edge of the vertical sync (field or frame if interlaced input) for the beginning of short vertical blanking for the interlaced field. This register is only valid for interlaced video formats. If Control register 1, bit 7 is set to 1 the SVBlank2_end is preset according to the selected standard. If set to, SVBlank2 end can be programmed manually using these 2 registers: ({SVBlank2_end_2[2:], SVBlank2_end_1[]}). The value is the number of horizontal lines after the falling edge of the vertical sync (field or frame if interlaced input) for the end of short vertical blanking for the interlaced field. This register is only valid for interlaced video formats. If Control register 1, bit 7 is set to 1 the subcarrier frequency seed is preset according to the selected standard. If set to, the subcarrier frequency seed can be programmed manually using these 4 registers: ({FSc_1[], FSc_2[], FSc_3[], FSc_4[]}). The seed is a 32 bit number and FSc_1[7] is the MSB. Default value is 55693156H Data Transfer Data word to be transmitted from receiver to transmitter. Not used Data word to be transmitted from receiver to transmitter. A write (data value is not important) to this register will initiate the transfer of the Tx data instruction and Tx data word over the acvi interface. Bit [] of this register indicates if the data transfer is complete. If Bit[] is a 1, the transfer is pending. If the transfer is complete and a new transfer may be initiated. Received data word. (note, this register will not be updated if there is a parity error). Received instruction word. Set to zero. Received instruction word parity. Calculated instruction word parity. Page 43 of 52

Register Offset Register Name Bit Value 3:2 1 $63 $6 AGC_Default_MSB AGC_Default_1 1: $63 $61 AGC_Default_MSB AGC_SD_PU_1 4:3 $63 $62 AGC_Default_MSB AGC_HD_PU_1 7:6 $66 $64 AGC_Limit_MSB AGC_LL_1 1: $66 $65 AGC_Limit_MSB AGC_UL_1 4:3 $67 PE_limit $6D Status R $6E Video standard R 7:1 7:6 5: Description Set to zero. Received data word parity. Calculated data word parity. AGC_control Value used for the PWM AGC gain control when AGC is turned off (Control Register 3 bit 1 = ). Effectively is the db gain value for the programmable gain amplifier.({agc_default_msb[1:],agc_default_1[]}). Default value = 3681. Starting value used for the PWM AGC gain control when AGC is turned on (Control Register 3 bit 1 = 1 ) and the video standard is SD or 96H. ({AGC_Default_MSB[4:3]AGC_SD_PU_1[]}). Default value = 3881. Starting value used for the PWM AGC gain control when AGC is turned on (Control Register 3 bit 1 = 1 ) and the video standard is HD. ({AGC_Default_MSB[7:6]AGC_SD_PU_1[]}). Default value = 51. Lower limit for the AGC PWM value when AGC is turned on (Control Register 3 bit 1 = 1 ). ({AGC_Limit_MSB[1:]AGC_LL_1[]}). Default value = 3481. Upper limit for the AGC PWM value when AGC is turned on (Control Register 3 bit 1 = 1 ). ({AGC_Limit_MSB[4:3]AGC_UL_1[]}). Default value = 5521. Maximum value of pre-emphasis that is sent to the transmitter in auto cable compensation mode (Register $2 bit 3 = 1 ). This limit value prevent the pre-emphasis being set to a value that the AGC of the receiver cannot compensate for. Status Not used Horizontal lock detect. Not used. Reports either the selected standard (Control 1, bit 4 = ) or the detected standard (Control 1, bit 4 = 1 ). Bits[5:] = ({S96H [Control Register 1 bit 5], Detected SD/HD format, Detected video standard[3:]}). Bits 5: Video standard 72p/25 1 72p/3 1 72p/5 11 72p/59 1 72p/6 11 18p/24 11 18p/25 111 18p/29 1 18p/3 11 18i/5 11 18i/59 111 18i/6 1 NTSC-M 11 PAL 11 NTSC-96H 111 PAL-96H 111111 Invalid standard Table 7 Register description. Page 44 of 52

12. Default register settings Parameter Hcount_length Hout_start Hout_end BP_gate_start BP_gate_end HBlank_start HBlank_end Halfline_set White_gate_start White_gate_end Vout_start Vout_end Vout2_start Vout2_end Fout_start Fout_end VBlank_start VBlank_end VBlank2_start VBlank2_end SVBlank_start SVBlank_end SVBlank2_start SVBlank2_end 72p/25 12'd3959 12'd98 12'd178 12'd185 12'd217 12'd2196 12'd276 12'd198 12'd297 12'd329 11'd747 11'd2 11'd747 11'd2 11'd 11'd 11'd742 11'd22 11'd742 11'd22 11'd742 11'd4 11'd742 11'd4 72p/3 12'd3299 12'd98 12'd178 12'd185 12'd217 12'd2196 12'd276 12'd198 12'd297 12'd329 11'd747 11'd2 11'd747 11'd2 11'd 11'd 11'd742 11'd22 11'd742 11'd22 11'd742 11'd4 11'd742 11'd4 72p/5 12'd1979 12'd98 12'd178 12'd185 12'd217 12'd2196 12'd276 12'd198 12'd297 12'd329 11'd747 11'd2 11'd747 11'd2 11'd 11'd 11'd742 11'd22 11'd742 11'd22 11'd742 11'd4 11'd742 11'd4 72p/59 12'd1649 12'd98 12'd178 12'd185 12'd217 12'd2196 12'd276 12'd198 12'd297 12'd329 11'd747 11'd2 11'd747 11'd2 11'd 11'd 11'd742 11'd22 11'd742 11'd22 11'd742 11'd4 11'd742 11'd4 72p/6 12'd1649 12'd98 12'd178 12'd185 12'd217 12'd2196 12'd276 12'd198 12'd297 12'd329 11'd747 11'd2 11'd747 11'd2 11'd 11'd 11'd742 11'd22 11'd742 11'd22 11'd742 11'd4 11'd742 11'd4 Table 8 Default register settings: acvi, 72p formats. Parameter Hcount_length Hout_start Hout_end BP_gate_start BP_gate_end HBlank_start HBlank_end Halfline_set White_gate_start White_gate_end Vout_start Vout_end Vout2_start Vout2_end Fout_start Fout_end VBlank_start VBlank_end VBlank2_start VBlank2_end SVBlank_start SVBlank_end SVBlank2_start SVBlank2_end 18p/24 12'd2749 12'd11 12'd19 12'd16 12'd192 12'd2196 12'd276 12'd1275 12'd297 12'd329 11'd1123 11'd3 11'd1123 11'd3 11'd 11'd 11'd1119 11'd39 11'd1119 11'd39 11'd1118 11'd4 11'd1118 11'd4 18p/25 12'd2639 12'd11 12'd19 12'd16 12'd192 12'd2196 12'd276 12'd1275 12'd297 12'd329 11'd1123 11'd3 11'd1123 11'd3 11'd 11'd 11'd1119 11'd39 11'd1119 11'd39 11'd1118 11'd4 11'd1118 11'd4 18p/29 12'd2199 12'd11 12'd19 12'd16 12'd192 12'd2196 12'd276 12'd1275 12'd297 12'd329 11'd1123 11'd3 11'd1123 11'd3 11'd 11'd 11'd1119 11'd39 11'd1119 11'd39 11'd1118 11'd4 11'd1118 11'd4 18p/3 12'd2199 12'd11 12'd19 12'd16 12'd192 12'd2196 12'd276 12'd1275 12'd297 12'd329 11'd1123 11'd3 11'd1123 11'd3 11'd 11'd 11'd1119 11'd39 11'd1119 11'd39 11'd1118 11'd4 11'd1118 11'd4 18i/5 12'd2639 12'd11 12'd19 12'd16 12'd192 12'd2196 12'd276 12'd1275 12'd297 12'd329 11'd1123 11'd2 11'd56 11'd564 11'd1123 11'd56 11'd1121 11'd2 11'd558 11'd583 11'd1123 11'd4 11'd56 11'd566 18i/59 12'd2199 12'd11 12'd19 12'd16 12'd192 12'd2196 12'd276 12'd1275 12'd297 12'd329 11'd1123 11'd2 11'd56 11'd564 11'd1123 11'd56 11'd1121 11'd2 11'd558 11'd583 11'd1123 11'd4 11'd56 11'd566 18i/6 12'd2199 12'd11 12'd19 12'd16 12'd192 12'd2196 12'd276 12'd1275 12'd297 12'd329 11'd1123 11'd2 11'd56 11'd564 11'd1123 11'd56 11'd1121 11'd2 11'd558 11'd583 11'd1123 11'd4 11'd56 11'd566 Table 9 Default register settings: acvi, 18p/i formats. Page 45 of 52

Parameter Hcount_length Hout_start Hout_end BP_gate_start BP_gate_end HBlank_start HBlank_end Halfline_set White_gate_start White_gate_end Vout_start Vout_end Vout2_start Vout2_end Fout_start Fout_end VBlank_start VBlank_end VBlank2_start VBlank2_end SVBlank_start SVBlank_end SVBlank2_start SVBlank2_end NTSC 12'd857 12'd41 12'd15 12'd11 12'd117 12'd21 12'd169 12'd429 12'd 12'd 11'd523 11'd1 11'd261 11'd264 11'd523 11'd261 11'd52 11'd15 11'd257 11'd278 11'd519 11'd3 11'd256 11'd266 PAL 12'd863 12'd46 12'd11 12'd11 12'd117 12'd24 12'd168 12'd432 12'd 12'd 11'd623 11'd1 11'd31 11'd313 11'd623 11'd31 11'd621 11'd2 11'd311 11'd333 11'd619 11'd3 11'd37 11'd316 NTSC-96H 12'd1143 12'd41 12'd126 12'd135 12'd151 12'd21 12'd169 12'd572 12'd 12'd 11'd523 11'd1 11'd261 11'd264 11'd523 11'd261 11'd52 11'd15 11'd257 11'd278 11'd519 11'd3 11'd256 11'd266 PAL-96H 12'd1151 12'd61 12'd146 12'd135 12'd151 12'd25 12'd19 12'd576 12'd 12'd 11'd623 11'd1 11'd31 11'd313 11'd623 11'd31 11'd621 11'd2 11'd311 11'd333 11'd619 11'd3 11'd37 11'd316 Table 1 Default register settings: SD formats. Page 46 of 52

13. PT51 Verification There are four components to the acvi progressive video format waveform. The description below will be based on the 18p/3Hz standard (see Figure 29). Figure 29 18p/3Hz video waveform - vertical interval. Each of the 4 components are supplied as 1-bit digital values in an Excel file. Each value represents the ADC digital acvi value that would be input to the PT51 decoder at nominal input levels. The values are calculated based on a 74.25MHz sample clock. The first 5 lines of the 18p standard are broad pulses (see Figure 3) which identify the field pulse. Each horizontal line of the 18p/3Hz standard has 22 pixels. Each of the 4 components of the video standard should be addressed using a horizontal counter clocked at 74.25MHz (74.25/22 = 33.75kHz horizontal line rate) and counting from to (22-1). At each reset of the horizontal counter a vertical line counter should be clocked, which should count from to (1125 1). The output of the vertical counter should be decoded according to Table 13 which selects one of the 4 components of the acvi 18p video signal. Figure 3 acvi broad pulse - 18p/3Hz. The pre- and post-broad pulses are standard line sync and blanked video with no burst (see Figure 31). Page 47 of 52

Figure 31 acvi blanking, no burst - 18p/3Hz. The vertical blanking interval comprises standard line sync with colour burst (see Figure 32). Figure 32 acvi blanking with burst - 18p/3Hz. The final component is the active video which is 75% colour bars (see Figure 33). Page 48 of 52

Figure 33 acvi 75% colour bars - 18p/3Hz. Line number 1-5 6, 1122-1125 7-41 42-1121 Component Broad pulses Blanking, no burst Blanking with burst Active video Description Field identification 75% colour bars Table 11 acvi vertical sync components - 18p. Page 49 of 52

14. Appendix A - VCXO Specification Figure 34 VCXO Specification - Page 1. Page 5 of 52

Figure 35 VCXO Specification - Page 2. Page 51 of 52

Figure 36 VCXO Specification - Page 3. Page 52 of 52