EEL 37 Digital Logic and Computer Systems Test 2 Fall Semester 25. Switch debouncing. (2 pts.) Why do we need to debounce the clock input on counter or state machine design? What happens if we don t? ( pts.) 2. Flip Flop Creation Using the JK Flip-Flop shown below and any logic gate (NANDs, ANDs, ORs, INVERTERs, etc.), create a T Flip-Flop with a SYNCHRONOUS clear. Assume all inputs & outputs to be high true (i.e., active high). Given: J Q K /Q + logic Design this: T Q CLR /Q J K Q + Q /Q Show work and draw your circuit here: CLR T Q + X Q /Q 2
EEL 37 Digital Logic and Computer Systems Test 2 Fall Semester 25 ( pts.) 3. Given the following ASM chart, complete the following timing diagram: A S B S X Y C S2 State S X Y A B C Notes:. Fill in the State and A,B,C signals above. 2. Show propagation delays and assume them to be this width. -> <- (5 pts.). Given the following logic equation and signal definitions, implement the equation using OPEN COLLECTOR NAND gates only (along with any necessary resistors) D = /( A+B ) + C A.L, B.H, C.H, D.L Draw your circuit here: OC 3
EEL 37 Digital Logic and Computer Systems Test 2 Fall Semester 25 (2 pts.) 5. Use the ALU shown on the next page for this problem. Complete the following timing diagram (as far as you can). Put the answer in binary for the MUXA Bus, MUXB Bus, REGA Bus, REGB Bus, and OUTPUT Bus below. INPUT Bus MSA MSA MSB MSB MSC2 MSC MSC MUXA Bus REGA Bus MUXB Bus REGB Bus OUTPUT Bus Indicate exactly where each value changes and show propagation delays.
EEL 37 Digital Logic and Computer Systems Test 2 Fall Semester 25 ALU Figure: Given below is the design of the ALU used in Lab 6. INPUT Bus REGA Bus REGB Bus OUTPUT Bus MSA MSA MUXA Bus MUX A s REG A MUXB Bus MUX B s REG B MSB MSB REGA Bus REGB Bus Combinatorial Logic MSC2: 3 MUX C s OUTPUT Bus MSA/MSB MSA/MSB INPUT Bus REGA Output Bus REGB Output Bus OUTPUT Bus CONTROL BYTE format X, MSA:, MSB:, MSC2: (Note the first bit X is a don t care ) MSC2: (Most Significant Bit is on the left) = > REGA Bus to OUTPUT Bus = > REGB Bus to OUTPUT Bus = > bit wise AND REGA/REGB Bus to OUTPUT Bus = > bit wise OR REGA/REGB Bus to OUTPUT Bus = > complement of REGA Bus to OUTPUT Bus = > REGA Bus Plus REGB Bus Plus Cin to OUTPUT Bus & Cout (There is an external Cin and an external Cout for the ALU) = > shift REGA Bus left one bit to OUTPUT Bus ( is shifted into OUTPUT Bus[].) = > shift REGA Bus right one bit to OUTPUT Bus ( is shifted into OUTPUT Bus[3].) 5
EEL 37 Digital Logic and Computer Systems Test 2 Fall Semester 25 (2 pts.) 6. Given the following block diagram for a controller that controls the ALU on the previous page, complete the following ASM chart that will perform the following functions. IR IR Controller MSA MSA MSB MSC2 MSC MSC When IR,IR = : Load REGA with data (from the INPUT Bus). Then, complement the data in REGA and store it into REGB. When IR,IR = (NOR operation) /(REGA OR REGB) => REGA, preserve REGB. When IR,IR = (Load and Sum operation) Load REGA with data (from the INPUT Bus). Load REGB with data (from the INPUT Bus). REGA plus REGB => REGA When IR,IR = (Complement both registers) /REGA => REGA /REGB => REGB After each function has been performed, go back to StateA. For maximum credit, use conditional outputs when possible and the minimum number of states. When not specified: Hold REGA, Hold REGB, MSC = StateA IR,IR 6
EEL 37 Digital Logic and Computer Systems Test 2 Fall Semester 25 7. Counter Design. For the State Diagram given below, answer the questions that follow. (3 pts.) Hold = False Hold = True S Hold = True Hold = False Hold = True If Hold = True, remain in the same state. If Hold = False, count as shown left. S: Q,Q = S: Q,Q = S2: Q,Q = S3: Q,Q = S2 S3 Hold = False Note: Hold is a synchronous signal. Hold = False Hold = True S You are given a T flip-flop and JK flip-flop to implement the design. The T flip-flop will be used for the Most Significant counter bit while the JK output will be used for the Least Significant counter bit. Characteristic tables are given for each device below: T Q + Q /Q J K Q + Q /Q Fill out the following Next State Table: Hold Q (T flip-flop) Q (JK flip-flop) Q + Q + T J K 7
EEL 37 Digital Logic and Computer Systems Test 2 Fall Semester 25 7. (continued) Derive the MSOP logic equation required for the T flip-flop input: T = Derive the MSOP logic equation required for the J input of the JK flip-flop: J = 8
EEL 37 Digital Logic and Computer Systems Test 2 Fall Semester 25 8. ROM Based ASM Implementations. ( pts.) You are given a K x 8 ROM based state machine as shown below with the following ROM contents: +5V K x 8 ROM A:3 D7: Not connected ROM Contents in Hex: Address Data IN.L Q.H Q.H A2 A A OE D3 D2 D clk D clk Q Q Q.H Q.H 3F8 5 3F9 3FA 52 3FB A 3FC B 3FD E 3FE 25 3FF 3 GND D D X.L Y.H Fill out the following Logic Next State Table for the above design: IN Q Q Q+ Q+ X Y 9
EEL 37 Digital Logic and Computer Systems Test 2 Fall Semester 25 9. Suppose the ROM contents of a ROM Based State Machine design produce the following logic table: ( pts.) IN Q Q Q+ Q+ X Y Draw the corresponding ASM Diagram for it: