hapter 9 ounters 9. Introduction ounters are devices which have a LOK input and produce n outputs. ounters consist of flip-flops connected together in specific ways such that on each clock edge the output changes. Normally the effect of this change is to generate an output that is in some way related to the previous output numerically. For example, every time a clock edge is detected the output could increase by. Therefore for n = 3 can write a table that illustrates this. lock Edge Output Q Q st 2 nd + 3 rd + 4 th + 5 th + 6 th + 7 th + 8 th + There is however a question that has to be answered; what happens after the 8 th clock edge? Generally it is required that the counter start again at. Hence the table can be re-written as follows: lock Edge Output Q Q st 2 nd 3 rd 4 th 5 th 6 th 7 th 8 th 9 th / st + + + + + + + Reset Variations on this are counters that have to be reset before the maximum value for n- bits is reached and counters that count up to a certain value before counting back to zero again and so on. Each will be discussed in the sections that follow. We will consider now the implementation of counters. It was stated previously that counters are implemented using flip-flops. JK flip-flops connected as T flip-flops are used. n flip-flops are required for an n-bit output counter. The flip-flops can be 9
connected in one of two ways, to produce either asynchronous counters or synchronous counters. In asynchronous counters, all the inputs are the same (tied ) and the output of each flip-flop is connected to the LK of the next flip-flop. In synchronous counters all the LKs of each flip-flop are connected to a common LOK, and the inputs are a combination of the previous outputs. The following diagrams illustrate these points. T J Q K LR Q Q T Q LR LR JK flip-flop connected as a T flip-flop. In counters the Q output is not normally required. A T flip-flop. Again the Q output is not normally required. In the above two diagrams the PRE is not shown as it is normally not used. Note that even though the PRE and Q are not always shown they are present. Remember from hapter 7 Flip-Flops, the truth table for the T flip-flop is : Inputs Outputs Description T Q Q Q Q No hange Q Q TOGGLE In other words if the input to the flip-flop is then the output toggles every time there is a clock edge detected, otherwise if the input is a then the output will not change. The next page shows a 4 bit asynchronous counter and a 4-bit synchronous counter so that they may be compared, based on the information previously given on the implementation of each type. 92
T Q T Q T 2 LR LR LR LR RESET LK Q Q 4-bit Asynchronous (Ripple) ounter T Q T Q T 2 LK Q Q 4-bit Synchronous ounter An asynchronous (ripple) counter and a synchronous counter are shown above. The RESET shown in red may be present in the synchronous circuit also. It has been left out for clarity. Notice that the least-significant bit (LSB) is shown on the left and the most-significant bit (MSB) is shown on the right. The observations previously mentioned can be seen to clearly, i.e. In asynchronous counters, all the inputs are the same (tied ) and the output of each flip-flop is connected to the LK of the next flip-flop. In synchronous counters all the LKs of each flip-flop are connected to a common LOK, and the inputs are a combination of the previous outputs. These observations assume that the counter is allowed to count to 2 n -, otherwise the circuits must be modified. The next sections looks at these two types of counters and also how they can be modified to achieve different effects. 93
9.2 Asynchronous (Ripple) ounters A typical asynchronous counter (4-bit) is shown below. Its operation will be considered. T Q T Q T 2 LR LR LR LR RESET LK Q Q The first thing to consider is that all the T-type flip-flops are tied. Therefore each time the clock edge (in this case a falling edge) is detected at each T flip-flop the output of each T flip-flop TOGGLES. onsider then that the RESET goes LOW. This causes the output of each flip-flop to go LOW also, i.e. Q Q =. If a falling clock edge now occurs at the input of the first flip-flop, the output, Q will change from to (because T = ). The next flip-flop remains unaffected by this because no falling edge has occurred. Therefore neither of the remaining two flip-flops change either. The output is now Q Q =. The next falling clock edge causes Q to TOGGLE as before, i.e. it changes from to. As Q changes from to there is a falling edge at the input to Q. This causes Q to TOGGLE (since T = ), therefore Q changes from to. This repeats as the table below shows. Q Q Q Q 2 3 4 5 6 7 8 9 2 3 4 5 94
Numbers highlighted in blue are numbers which have changed as a result of a falling clock edge being detected. The falling clock edges occur when the output of a previous flip-flop changes from a to a, in addition to the normal occurrence for the LK itself. The counter illustrated above will continue to cycle through the output values shown as long as LOK pulse is applied to the first flip-flop. The output waveforms for the circuit and that of the LOK are shown below. It can be seen that for each successive flip-flop the frequency of the waveform is halved, i.e. the frequency of Q is half that of the LK, the frequency of Q is half that of and so on. LK f Q f / 2 Q f / 4 f / 8 f / 6 2 3 4 5 6 7 8 9 2 3 4 5 2 3 If the LK has a frequency of f Hz then the frequency of each output is shown in terms of f on the right-hand side of the diagram. Again as in the previous table the blue numbers indicate a change due to the detection of the falling clock edge. The hashed red lines show falling clock edges. The counter shown counts to 5, where 5 is the maximum value that can be represented by 4 bits. 5 is said to be the maximum modulus of the counter. Often the maximum modulus is not required, rather a truncated sequence is desired. Typical examples are counting to 9 ( states) before starting again at or (2 or dozen states) before starting again at zero. This is the subject of the following subsection. 9.2. Truncated Asynchronous ounters The key to implementing truncated asynchronous counters is to detect the first undesired state and then RESET the flip-flops to zero that are not already zero. EAMPLE : An asynchronous counter is required that counts from to 9 before starting at again. 95
SOLUTION : Step We must determine how many flip-flops are required to implement a counter that counts to 9. From our knowledge gained from hapter 2 Number Systems (or by inspection) we know that 4 bits are required and hence 4 flip-flops will be used to implement the counter. Therefore we have: T Q T Q T 2 LR LR LR LR LK Q Q Step 2 We must detect when a is output by the counter, i.e. when Q Q =. When we detect this state we need to output a zero to those flip-flops not already zero. In order to output a zero we can used a NAND gate circuit, i.e. Q to LR Q Further examination of the table of outputs previously developed, i.e., Q Q Q Q 2 3 4 5 6 7 8 9 2 3 4 5 96
shows that if is then the number must be either 8, 9 or. can be distinguished from 8 and 9 because Q is also. Hence our circuit for detecting the presence of a can be simplified to: Q to LR This is possible because states, 2, 3, 4 and 5 cannot occur as the counter is RESET when is detected. However the previous circuit is perfectly acceptable. Step 3 We must decide on which flip-flops need to be RESET. When a is detected Q and are already zero, therefore they do not need to be RESET. However Q and are both so they must be RESET to. Hence the output of the detection circuit must be connected to their LR inputs. The circuit required therefore is : T Q T Q T 2 LR LR LR LR LK Q Q 4-bit Asynchronous ounter that counts from to 9 EAMPLE 2 : SOLUTION : An asynchronous counter is required that counts from to before starting at again. Step As before we determine how many flip-flops are required to implement a counter that counts to. By inspection we know that 4 bits are required and hence 4 flip-flops will be used to 97
implement the counter. Therefore we have our basic circuit as shown: T Q T Q T 2 LR LR LR LR LK Q Q Step 2 We must detect when a 2 is output by the counter, i.e. when Q Q =. When we detect this state we need to output a zero to those flip-flops not already zero. In order to output a zero we can used a NAND gate circuit, i.e. Q to LR Q Further examination of the table of outputs previously developed, i.e., Q Q Q Q 2 3 4 5 6 7 8 9 2 3 4 5 98
shows that if is then the number must be either 8, 9,, or 2. 2 can be distinguished from 8, 9, and because is also. Hence our circuit for detecting the presence of a 2 can be simplified to: to LR This is possible because states 3, 4 and 5 cannot occur as the counter is RESET when 2 is detected. Again the previous circuit is acceptable. Step 3 As before we decide on which flip-flops need to be RESET. When a 2 is detected Q and Q are already zero, therefore they do not need to be RESET. However and are both so they must be RESET to. Hence the output of the detection circuit must be connected to their LR inputs. The circuit required therefore is: T Q T Q T 2 LR LR LR LR LK Q Q 4-bit Asynchronous ounter that counts from to EAMPLE 3 : SOLUTION : An asynchronous counter is required that counts from to 2 before starting at again. Step As before we determine how many flip-flops are required to implement a counter that counts to 2. By inspection we know that 4 bits are required and hence 4 flip-flops will be used to 99
implement the counter. Therefore we have our basic circuit as shown: T Q T Q T 2 LR LR LR LR LK Q Q Step 2 We must detect when a 3 is output by the counter, i.e. when Q Q =. When we detect this state we need to output a zero to those flip-flops not already zero. In order to output a zero we can used a NAND gate circuit, i.e. Q Q to LR Further examination of the table of outputs previously developed, i.e., Q Q Q Q 2 3 4 5 6 7 8 9 2 3 4 5
shows that if is then the number must be either 8, 9,,, 2 or 3. 3 can be distinguished from 8, 9, and because is also. It is distinguished from 2 because Q is a. Hence our circuit for detecting the presence of a 2 can be simplified to: to LR Q This is possible because states 4 and 5 cannot occur as the counter is RESET when 3 is detected. Again the previous circuit is acceptable. Step 3 As before we decide on which flip-flops need to be RESET. When a 3 is detected only Q is already zero, therefore Q, and all must be RESET to. Hence the output of the detection circuit must be connected to their LR inputs. The circuit required therefore is: T Q T Q T 2 LR LR LR LR LK Q Q 4-bit Asynchronous ounter that counts from to 2 From the examples above it should be clear that truncating an asynchronous counter is trivial. Essentially the circuit is modified so that when the state after last state is entered any flip-flops whose output is are RESET. Note : Unused LR inputs are tied so that the flip-flops they are connected to will not be RESET.
9.3 Synchronous ounters A typical synchronous counter (4-bit) is shown below. Its operation will then be considered. T Q T Q T 2 LK Q Q The first thing to consider is that all the T-type flip-flops are clocked simultaneously. Therefore each time the clock edge (in this case a rising edge) is detected at each T flip-flop the output of each T flip-flop will depend on the value of the T input. If T = then the output will not change, if T = the output will TOGGLE. Obviously Q will TOGGLE every time a rising clock edge is detected because T =. onsider then that initially Q Q =. If a rising clock edge now occurs at the input of the first flip-flop, the output, Q will change from to (because T = ). At the same time there is a rising clock edge at the other flip-flops but there is no change in their outputs () because in each case the T input is. Therefore the output is now Q Q =. The next rising clock edge causes Q to TOGGLE as before, i.e. it changes from to. At the same time T =, therefore Q TOGGLES and changes from a to. T 2 = Q Q = (since Q = ) and T 2 = Q Q = (since = and Q = ) therefore and Q remain unchanged and stay equal to. This pattern repeats itself as the table on the following page shows. 2
T Q T = Q Q T 2 = Q Q T 2 = Q Q Q Q 2 3 4 5 6 7 8 9 2 3 4 5 Two sets of values are shown in the table above. The values for the flip-flop outputs; Q Q and the flip-flop inputs;, T 2, T and T. The table can be read as follows:. On each rising clock edge the value of T is inspected for each flip-flop and if it is, the output Q is TOGGLEd. 2. The value of T for each flip-flop is determined by inspecting the previous values of Q which are applicable. Red values indicate values when T =. Blue values for Q indicate that Q has TOGGLEd as a result of a rising clock edge when T =. The counter illustrated above will continue to cycle through the output values shown as long as LOK pulse is applied. The output waveforms for the circuit and that of the LOK are shown on the following page. It can be seen that for each successive 3
flip-flop the frequency of the waveform is halved, i.e. the frequency of Q is half that of the LK, the frequency of Q is half that of and so on. LK f T Q f / 2 T Q f / 4 T 2 f / 8 f / 6 2 3 4 5 6 7 8 9 2 3 4 5 2 3 If the LK has a frequency of f Hz then the frequency of each output is shown in terms of f on the right-hand side of the diagram. Again as in the previous table the blue numbers indicate a change due to the detection of the falling clock edge. The hashed red lines show rising clock edges. Notice that the waveforms for the T inputs are delayed slightly. This is because each T value (except T ) depends on the previous flip-flop outputs Q, thus there is a delay introduced to the waveform of T since there is a propagation delay inside the flipflops. It should be clear from the waveform diagram that outputs Q change (TOGGLE) each time there is a present in the corresponding T input. This is as expected as each flip-flop detects every rising clock edge, but while T = there is no change. 4
9.4 Design of Synchronous ounters In the last section, a counter design was presented and analysed. The analysis showed that it is a modulo-6 binary counter, ie it counts from to 5 and resets. onsider now the task of designing the counter from first principles. This requires selection of the required number of flipflops and determining the logic circuitry that needs to be added in order that the counter counts in the desired fashion. This involves determining the required logic functions, in terms of the counter outputs Q, to drive the flipflop toggle inputs T. EAMPLE : Design a modulo-6 synchronous counter that counts from to 5 before starting at again. SOLUTION : We must determine how many flip-flops are required to implement a counter that counts from to 5. By inspection we know that 4 bits are required and hence 4 flipflops will be used to implement the counter. Let the counter outputs be designated Q Q and the corresponding toggle counter inputs T 2 T T. Now draw the truth table for the counter, indicating also the required toggle levels for each count state, ie the required toggle levels to get the counter to move to the next state in the counting sequence. Q Q T 2 T T 2 3 4 5 6 7 8 9 2 3 4 5 In order to design the logic circuits to control each of the toggle inputs of the flipflops, the above truth-table is essentially that of a combinational logic circuit with 4 inputs Q Q and four outputs T 2 T T. The logic circuit to produce each of the outputs may be minimised using standard techniques, eg the Karnaugh Map method. From the truth-table above, it is clear that T = for all inputs Q Q and no further minimisation is required. From the truth-table, using min-term notation, we may also write the unminimised logic expressions for T, T 2, and as: 5
T = m(,3,5,7,9,,3,5) 2 = Q3Q2Q Q T m(3,7,,5) T 3 = m(7,5) Q3Q2QQ Q3Q2QQ K-maps for T, T 2, and are given below. Q Q Q Q Q Q 3 2 3 2 4 5 7 6 4 5 7 6 2 3 5 4 2 3 5 4 8 9 8 9 Q Q T T2 Q Q Q 3 2 4 5 7 6 2 3 5 4 8 9 Q T3 From the K-maps we can write the minimised logic expression for each toggle input as: T = Q ; T 2 = Q Q ; = Q Q. Also T =. omparing the above with the complete diagram of the counter on page 2 indicates that they correspond with the circuitry used to generate the control signals for the toggle inputs of the flipflops. 6
EAMPLE 2 : Design a synchronous decade counter that counts from to 9 before starting at again. SOLUTION : We must determine how many flip-flops are required to implement a counter that counts from to 9. By inspection we know that 4 bits are required and hence 4 flipflops will be used to implement the counter. Let the counter outputs be designated Q Q and the corresponding toggle counter inputs T 2 T T. Now draw the truth table for the counter, indicating also the required toggle levels for each count state, ie the required toggle levels to get the counter to move to the next state in the counting sequence. The input min-terms m() to m(5) inclusive are can t happen or don t care terms. Q Q T 2 T T 2 3 4 5 6 7 8 9 2 3 4 5 From the truth-table above, it is clear that T = for all inputs Q Q and no further minimisation is required. From the truth-table, using min-term notation, we may also write the unminimised logic expressions for T, T 2, and as: T T T 2 3 = = = m(,3,5,7) + Q3Q2Q Q m(3,7) + Q3Q2QQ m(7,9) + Q3Q2QQ Q3Q2QQ Q3Q2QQ Q3Q2QQ d(,,2,3,4,5) d(,,2,3,4,5) d(,,2,3,4,5) K-maps for T, T 2, and are given below. From the K-maps we can write the minimised logic expression for each toggle input as: T = Q ; T 2 = Q Q ; = Q Q + Q. Also T =. 7
Q Q Q Q Q Q 3 2 3 2 4 5 7 6 4 5 7 6 2 3 5 4 2 3 5 4 8 9 8 9 Q Q T T2 Q Q Q 3 2 4 5 7 6 2 3 5 4 8 9 Q T3 The circuit may therefore be drawn as: T Q T Q T 2 LK Q Q 4-bit Synchronous ounter that counts from to 9 8
9.5 Frequency Division using ounters As was illustrated earlier the frequency of the n th output (i.e. Q n- ) of a non-truncated counter has a frequency equal to the clock frequency divided by 2 n. Therefore for a 4- bit counter the output frequency will be the clock frequency, f LK, divided by 2 4, i.e. f LK flk =. This is the case because the required edge (falling or rising) of the last 2 4 6 output (n th output = Q n- ) only occurs once for every 6 similar edges on the clock waveform. This can be clarified by examining the waveforms for the 4-bit asynchronous and synchronous counters in section 8.2 and 8.3 respectively. If the counter is truncated, for example the counter counts from only to 9, then the required edge on the nth output will occur once for every similar edges on the clock waveform, i.e. the period of the n th output waveform is now shorter, hence the frequency is now larger ( f = ), which results in a waveform whose frequency is T f equal to LK. In general we can say that the frequency of the output waveform of the n th output of a counter is equal to the input clock frequency divided by the total number of states, say x, that the counter has (for example a non-truncated 5-bit counter has 32 states, a truncated 3-bit counter that counts from to 5 has 6 states and flk flk so on), i.e. fout = =. NumberOfStates x ounters are represented symbolically by the symbol: INPUT TEN T TR DIV x OUTPUT Q Q Q n Where TR DIV x indicates the number of states that the counter has; TEN is the enable for the counter and T is the n th output (Q n- output). Given the example below the frequency at T is simply calculated by dividing the clock frequency for each counter by the value for x. Output = 6 Hz Output = Hz INPUT = 6 Hz TEN T TR DIV TEN T TR DIV 6 TEN T TR DIV OUTPUT Output =. Hz 9