ST9212 ideo Processor for CRT Monitors with PictureBooST Main Features General I²C-Bus Controlled Supports AC- and DC-coupled applications 5 to 8 Power Supply Matches to virtually any video amplifier PictureBooST PictureBooST insertion input Full-screen PictureBooST via I²C-bus Context-sensitive Picture Enhancement ideo Clamping Input and Output ideo Clamp Sync Pulse Polarity Auto-rectification Clamp Pulse Generation timed either by sync or video blanking pulse ideo Processing Contrast Adjustment with excellent channel matching Gain stages for control of white Two DC-mode cut-off ranges Output DC offset control Automatic Beam Limiter (ABL) ideo Insertion Pulse (IP), 2 levels Amplifier Control (Blanking and Stand-by) OSD Insertion with Contrast Control Control Output Amplifier Standby and Blanking Control 3 DAC for control of DC Restore Amplifier or Brightness in DC-coupled system DIP24S:(Plastic Package) ORDER CODE: ST9212 General Description The ST9212 is an I²C-bus controlled color video processor designed for standard CRT monitor applications. It can drive systems where cathodes are either AC- or DC-coupled to the amplifier outputs. The three video channels provide contrast and white balance separate gain adjustments as well as one-per-channel DC cut-off control and common DC offset control functions. On top of these usual controls, it features context-sensitive picture enhancement circuitry to support the PictureBooST function that enhances the appearance of still pictures and moving video. In AC coupling applications, the device can pilot three cathode DC restore channels dedicated to set CRT cut-off bias voltages and to control brightness through cathodes. The RGB video outputs have a class A architecture and directly drive the amplifier channels without unnecessarily consuming current. Bandwidth limitation I²C-bus adjustments can contribute to keeping the application EMI under control. OSD (On-Screen Display) graphics are inserted by means of a Fast Blanking signal. Independent OSD contrast control facilitates adaptation to various OSD generators and provides system flexibility. The ST9212 is perfectly compatible with other ST components for CRT video boards, such as video amplifiers and OSD generators. July 23 1/34
ST9212 Table of Contents Chapter 1 ST9212 Pin Allocation and Description...............................4 1.1 Pinout...4 1.2 Pin Descriptions...4 Chapter 2 Functional Description.............................................5 2.1 ideo RGB Input Clamp...6 2.2 ideo Blanking...8 2.3 Contrast Control Stage and Automatic Beam Limiter...9 2.4 PictureBooST... 1 2.5 OSD Insertion... 11 2.6 Drive Stage... 11 2.7 ideo Insertion Pulse... 12 2.8 Output Stage... 12 2.9 Output Infra-black Level, Cut-off and Brightness... 15 2.1 Signal Waveforms... 18 2.11 Miscellaneous... 18 Chapter 3 I²C-Bus Interface Specifications.....................................2 3.1 I²C-bus Register Descriptions... 21 Chapter 4 Electrical Specifications...........................................24 4.1 Absolute Maximum Ratings... 24 4.2 Thermal Data... 24 4.3 Static Electrical Characteristics...24 4.4 Dynamic Electrical Characteristics... 25 4.5 I²C-Bus Electrical Characteristics... 27 4.6 I²C-Bus Interface Timing Requirements... 27 Chapter 5 Soldering Information.............................................29 Chapter 6 Package Mechanical Data.........................................3 Chapter 7 Input/Output Diagrams............................................31 2/34
ST9212 Chapter 8 Revision History..................................................33 3/34
ST9212 Pin Allocation and Description 1 ST9212 Pin Allocation and Description ST9212 1.1 Pinout Figure 1: ST9212 Pinout 1.2 Pin Descriptions IN1 HS IN2 ABL IN3 GNDA CCA PB 1 2 3 4 5 6 7 8 24 23 22 21 2 19 18 17 BLK AMPCTL OUT1 CCP OUT2 GNDP OUT3 CO1 OSD1 OSD2 9 1 16 15 CO2 CO3 OSD3 11 14 SDA FBLK 12 13 SCL Table 1: ST9212 Pin Descriptions Pin Name Function Pin Name Function 1 IN1 ideo Input, Channel 1 13 SCL I²C-bus Clock Input 2 HS ideo Clamp Sync Input 14 SDA I²C-bus Data Input/Output 3 IN2 ideo Input, Channel 2 15 CO3 Cut-off / Brightness DAC 3 Output 4 ABL Automatic Beam Limiter Input 16 CO2 Cut-off DAC 2 Output 5 IN3 ideo Input, Channel 3 17 CO1 Cut-off DAC 1 Output 6 GNDA Analog Ground 18 OUT3 ideo Output, Channel 3 7 CCA Analog Supply 19 GNDP Output Stage Ground 8 PB Picture Boost Input 2 OUT2 ideo Output, Channel 2 9 OSD1 OSD Input, Channel 1 21 CCP Output Stage Supply 1 OSD2 OSD Input, Channel 2 22 OUT1 ideo Output, Channel 1 11 OSD3 OSD Input, Channel 3 23 AMPCTL Output for Amplifier Control 12 FBLK OSD Insertion Control Input 24 BLK Blanking and ideo Clamp Sync Input 4/34
ST9212 2 Functional Description Functional Description The functional blocks are described in the order they act on the signal. Figure 2: ST9212 Block Diagram HS BLK FBLK PB CCA CCP ST9212 14 13 SDA SCL 1 IN1 3 IN2 5 IN3 4 ABL 2 24 12 8 7 21 ICP, OCP BLKI OCP BLKI PictureBooST ICP Clamp ref ICP Contrast I²C-bus Decoder I²C I²C-bus control path video/control signal path + + PreAmplifier Stand-by Drive OSD1 OSD2 OSD3 3 (DC) OCP I²C Amplifier DC or AC Output Stage 6 GNDA OUT1 22 G BLKI CO1 FBLK IP 17 G DC level DCIN1 Infra-black level I²C STDB/ OSD cut-off BLK Brightness Channel 1 GNDP 19 GND Channel 2 Channel 3 OSD Contrast 9 1 11 + BLKI Standby & Blanking I²C CCP 2 OUT2 16 CO2 18 OUT3 15 CO3 23 AMPCTL OUT1 DCOUT1 EHT 5/34
Functional Description ST9212 2.1 ideo RGB Input Clamp The three RGB inputs have to be supplied with a video signal through coupling capacitors playing the role of analog memories for internal video clamps. The input clamping level is approximately. The clamp is gated by the Input Clamp Pulse (ICP) that is internally generated from a signal on either the HS or BLK pin. The selection is done via register 8 of the I²C-bus. For more information, refer to Figure 3: ICP, OCP and BLKI Generation and Table 2: ICP Timing. Provided with an automatic polarity rectification function, the HS input accepts horizontal synchronization signals of either polarity. The device can select either the leading or trailing edge of this signal to trigger the ICP generator. The BLK input is followed by an inverter stage that can be enabled or by-passed via the I²C-bus. This allows the use of a signal of either polarity, the control software taking care of the inverter position according to the signal applied. The BLKI signal found behind this inverter stage also drives the video blanking circuitry which requires a positive BLKI polarity for correct operation. Once bit BLKPOL has correctly been uploaded to ensure a positive BLKI polarity, the ICP triggering edge can be selected via control bit BCEDGE. A horizontal flyback pulse is generally expected to be applied on the BLK input. As the edges of horizontal flyback pulse can fall into the active video content (outside the video signal line blanking portion), the application must ensure that such an edge is never selected for triggering the ICP. The width of the internally generated ICP is controlled via the I²C-bus. The HS input can be used to pass a clamping pulse, if available in the application, directly to clamping stages, without any additional processing. In this case, the appropriate polarity (positive) is required. See Table 2: ICP Timing. The ICP timings triggered by the trailing edge of the BLK signal are not presented. HS BLK The Output Clamp Pulse (OCP) is described in Section 2.8: Output Stage. 2 24 Automatic Polarity -1 1 Figure 3: ICP, OCP and BLKI Generation Pulse Generation on ICP (Internal) OCP (Internal) BLKPOL (Sad9/b) BCSC (Sad8/b) 1 BLKI -1 BCEDGE (Sad8/b1) 1 Pulse Generation on ideo blanking ICP width BCWDTH (Sad8/b2,b3) 1 ICP trig/pulse mode BCSC1 (Sad8/b4) 1 OCPSC (Sad8/b7) BLKI (Internal) I²C-bus field Note: The I²C-bus switches are displayed in their default positions 6/34
ST9212 Functional Description Trigger Source Trigger Event Table 2: ICP Timing BCSC1 BCSC BCEDGE BLKPOL Timing Diagram Trailing edge Don t care HS ICP negative or positive.33µs...1.33µs HS pin BLK Leading edge Pulse 1 Rising edge Falling edge 1 Don t care 1 1 Don t care Don t care Don t care 1 1 1 1 Figure 4: ideo Input Clamp Input video DC signal from graphics card (can vary) IN1 1 High Impedance stage HS ICP.33µs...1.33µs negative or positive HS (must be positive!) ICP BLK ICP.33µs...1.33µs BLK ICP.33µs...1.33µs Ref = Internal reference voltage (fixed) Ref To further processing clamped to GND ICP Note: Identical for IN2 and IN3 inputs 7/34
Functional Description ST9212 2.2 ideo Blanking The three video channels are simultaneously blanked with the high level of either BLKI or FBLK signals. BLKI is an internal signal drawn from the signal applied on the BLK pin (H-flyback) as shown in Figure 3. The blanking consists in forcing a black level to the internal clamped video signal. BLK Input The BLK input receives an H-flyback pulse that drives: the video blanking circuitry during scan line retrace, the output clamping stage. A clipping circuit at the input allows the direct use of a high-voltage H-flyback pulse applied through a serial resistor as shown in Figure 5. A logic-level signal is also accepted but the serial resistor remains mandatory. In all cases, the value of this resistor must be such that the sinking and sourcing currents are limited to 1mA and 1µA, respectively. 4 to 1 GND to -1 ~3 GND Permanent Blanking Figure 5: BLK Input Pin Typical H-Flyback signal Signal at BLK pin (Pin 24) The entire T screen can be blanked for an unlimited amount of time using the software blanking feature. Both bits SWBLK and TST1 must be set to 1. The three video outputs are forced to their infra-black levels as shown in Figure 6. Infra-black levels are defined in Section 2.9. Figure 6: Software Blanking R lim (*) (*) R lim is necessary to limit currents flowing through BLK pin (-1uA, +1mA max.) BLK 24 Normal operation SWBLK=, TST1= Software blanking in operation SWBLK=1, TST1=1 ideo output channels 1,2,3 Black level Infra-black level 8/34
ST9212 Functional Description The screen can also be blanked by permanently keeping the On-Screen Display FBLK input signal at high level. In this case, only the video contents of the three video channels are replaced by black level OSD content insertion (signals on pins OSD1 through OSD3 permanently at low level). Refer to Section 2.5: OSD Insertion on page 11. 2.3 Contrast Control Stage and Automatic Beam Limiter The contrast stages are simultaneously controlled on all three RGB channels with high attenuation matching precision. Refer to electrical specifications for values. See Figure 7: Contrast Control and Table 4: I²C-Bus Register Map. Figure 7: Contrast Control Before contrast stage After contrast stage CRST=max CRST=mid CRST=min Note: CRST I²C-bus field acts equally on all 3 video channels The Automatic Beam Limiter (ABL) is an attenuator controlled through the ABL input, independent of contrast stage attenuation. The operating range is about 2 (from 3 to 1 ). A typical characteristic is shown in Figure 8. Refer to Section 4: Electrical Specifications for specific values. When not used, the ABL pin is to be connected to CCA. Figure 8: ABL Characteristics Attenuation (db) -2-4 -6-8 -1-12 -14-16 1 ideo Black Level ideo Black Level 2 3 4 5 ABL () Ref Ref 9/34
Functional Description ST9212 2.4 PictureBooST The PictureBooST function provides a picture enhancement effect for images with photographic or moving video contents. The function is activated whenever the level on pin PB is high (TTL) or the bit PBINS is at 1, if the general PictureBooST enable bit PBGEN is at 1. By means of PB input signal toggling, the function can take effect in a part of the screen, e.g. a window, or on the whole screen. The picture enhancement is achieved through combination of three actions, as shown in Figure 9: a content-sensitive peaking with slow restore (vivacity), a contrast addition, a brightness addition. The vivacity amplitude depends on the slope height and steepness and on the status of bits PBIAM[1:]. The return to stabilized state is exponential with a time constant adjustable via bits PBITC[2:]. Any undershoot below the video black level is clipped to a level close to black. The PictureBooST brightness is a DC offset superimposed on the video signal in the boosted zone. Its value is selected by bits PBBRIG[1:]. The vivacity and PictureBooST brightness are both enabled by bit PBIEN. The PictureBooST contrast component evenly increases the video amplitude in the boosted zone. Its value is controlled by bits PBCRST[1:]. Refer to Section 4: Electrical Specifications for values. H-sync ideo before PictureBooST stage PB input ideo after PictureBooST stage Figure 9: PictureBooST Action τ viv viv PB contrast A A PB brightness clipping 1/34
ST9212 Functional Description 2.5 OSD Insertion The On-Screen Display (OSD) is inserted with a high level on the FBLK input (TTL). The device acts as follows: The three RGB video input signals (IN1, IN2, IN3) are internally blanked, i.e. put at the black level. Binary levels (TTL) on inputs OSD1, OSD2 and OSD3, after processing in the OSD contrast stage, are added to the corresponding blanked video channels. In this way, the OSD contents replace the video contents where the FBLK input is high. See Figure 2 and Figure 1. The OSD is inserted after the PictureBooST block and before the Drive block. As a consequence, OSD insertion overlaps all video contents, including the PictureBooST -ed zones. Color temperature adjustments by means of the I²C-bus Drive registers act in the OSD insets. The OSD contrast stage allows the adjustment of the level of OSD insets simultaneously on the three OSD channels and independently of the video contrast adjustment. Refer to Section 4: Electrical Specifications for values. OSD Signals ideo before OSD insertion FBLK OSD1(2,3) ideo after OSD insertion 2.6 Drive Stage Figure 1: OSD Insertion OSD max mid min. OSDCRST Note: The OSDCRST I²C-bus field acts equally on all 3 OSD channels. ideo Black Level ideo Black Level The Drive stage is a set of three attenuators separately controlled via three I²C-bus registers, DRIE1, DRIE2 and DRIE3. It affects all signals, ordinary video, PictureBooST processed video and OSD insets. It is designed to compensate for differences in gain of the three CRT cathodes. See Figure 11 and for values, refer to Section 4: Electrical Specifications. Ref Ref 11/34
Functional Description ST9212 Figure 11: Drive Control Before Drive Stage ideo Black Level Ref After Drive Stage DRIEx=max DRIEx=mid One I²C-bus register DRIEx (x=1, 2 or 3) per video channel 2.7 ideo Insertion Pulse ideo Black Level Ref The ideo Insertion Pulse (IP) creates an indent on the three video signals, timed with the positive part of the BLKI signal. (See Section 2.2: ideo Blanking on page 8). As its level is below the video black level, it introduces a video infra-black level. The video infra-black level position versus ground is then controlled in subsequent stages. In the absence of the blanking pulse on pin BLK, the IP is not inserted and the subsequent stages control the position of video black level. Figure 12 shows the signal before and after insertion of the IP. Two different IP values are programmable by bit IP. Refer to Section 4: Electrical Specifications for values. ideo before IP insertion BLKI signal DRIEx=min Figure 12: IP Insertion ideo after IP insertion IP ideo Black Level ideo Black Level ideo Infra-black Level Ref Ref + IP Ref Note: Identical for video channels 1, 2 and 3. 2.8 Output Stage The output stage consists of an output clamp and a buffer. If a reduced output video amplitude and/ or a reduced infra-black level range is sufficient in the application, the CCP can be lowered to 5. 12/34
ST9212 Functional Description Even at 8 of CCP, care must be taken at device application level to ensure operation without signal top limitation. 2.8.1 Output Clamp The DC position of video infra-black and video black levels at the video outputs must be fixed regardless of video or OSD inset contents, especially in applications where the device s output infra-black level determines directly the infra-black level on the CRT cathodes (DC-coupled applications). This fixing is achieved by means of a fully-integrated output clamp that brings the output video infra-black level (video black level, in absence of the BLK pulse) to the level of a variable reference ( ib ) as shown in Figure 13. The ib is described in detail in Section 2.9 on page 15. The clamp circuit is driven by the Output Clamp Pulse (OCP). For correct operation, this pulse must entirely fall into the IP pulse if this is present (clamp of infra-black level) or onto the video black part (clamp of black level). In the former case, the OCP generator is to be triggered with the leading edge of the BLK pulse, in the latter case it must copy the ICP pulse. Refer to Figure 3 for the OCP generation block diagram. Table 3 shows possible OCP timings. Although possible, the OCP timings, triggered by the BLK trailing edge, are not shown as they have no practical use. 2.8.2 Bandwidth Control Controlled via bits BW[3:], the output stage can limit the rise and fall time of the output signal. The optimum choice for this adjustment is highly application dependent. Refer to Section 4: Electrical Specifications for values and to Section 6: Application Hints for practical advice. 2.8.3 Output Buffer The output buffer provides enough current so that external buffers are not required and the power amplifier can interface directly to the device s outputs. BLKI OCP ideo before output stage GND Ref Figure 13: Output Stage Output Infra-black Level Note: Identical for video channels 2 and 3. OCP Clamp & Buffer - + ib 15 22 CCP OUT1 ib 13/34
Functional Description ST9212 Source Trigger Event Table 3: OCP Timing OCPSC BLKPOL Timing Diagram ICP Pulse 1 Don t care ICP OCP BLK Rising edge BLK OCP Falling edge 1 BLK OCP 14/34
ST9212 Functional Description 2.9 Output Infra-black Level, Cut-off and Brightness The schematic diagram of these functions is shown in Figure 14. Figure 14: Cut-off and Brightness Control Block Diagram I²C-bus field Ref Output stage ib OUT1 OUT2 OUT3 1 for 3 channels ib IBOF ideo DC level ibmin DC IBL3 IBL2 IBL1 BRIG 1 per channel Cut-off Cut-off Cut-off 1 for 3 channels Brightness 2.9.1 Output Infra-black Level range range BRIGRG range ibldc DC: AC:1 iblac briac IBLRG Channel 3 Only The infra-black level of the video signal at the video outputs OUT1, OUT2 and OUT3 is positioned to the ib reference by the output clamp circuit, thus defining the Output infra-black level. If the output clamp circuit is furnished with a correctly timed OCP (see corresponding sections), the output infra-black level equals ib. ib is composed of a fixed DC voltage ( ibmin ), a variable DC voltage ( ibof ) applied on all three channels and a per-channel variable DC voltage ( ibl (1,2,3)) as shown in Figure 15. In AC-coupling mode (bit MOD = 1), the ibl part is suppressed and the ib is therefore equal on all three channels, only varying with bits IBOF[5:] acting on ibof. This can be used to match the device s outputs to the input of the video amplifier used (biasing). In DC-coupling mode (bit MOD = ), ibl (1,2,3) are separately set via bits IBL1[7:], IBL2[7:] and IBL3[7:], respectively. This serves to adjust the cut-off points of the three CRT cathodes. In this case, ibof can serve to pre-position the cut-off ranges in the factory adjustment procedure or/and to provide a rough brightness control. AC:1 DC: bridc MOD ~4kΩ DC COmin Note: Identical for CO1, CO2 and CO3 outputs except for brightness ( bridc ) that is only output at CO3 while MOD=. The switches are drawn in their default positions. * ~ when the output is left open CO CO1 CO2 CO3 COmax CO GND MOD=1 MOD= iblac briac bridc ~* COmin Ch3 Ch1 Ch2 15/34
Functional Description ST9212 Figure 15: Output Infra-black Level 19 GNDP 22 2 18 OUT1 OUT2 OUT3 black ib (1) ibl (1) infra-black ibl (2) 2.9.2 Cut-off and Brightness Control Outputs 19 Outputs CO1, CO2 and CO3 provide a DC voltage controlled via bits BRIG[7:], IBLx[7:], IBLRG[7:], BRIGRG[1:] and MOD[7:]. The principal of operation is shown in Figure 14. When bit MOD is in position AC (= 1), the output voltage is a sum of the brightness briac, cut-off iblac and a fixed COmin providing a bottom limitation. The brightness adjustment is equally applied to all three CO1, CO2 and CO3 outputs. It varies depending on bits BRIG[7:] and BRIGRG[1:], with bits BRIGRG[1:] controlling the range of BRIG adjustment. The cut-off adjustment is separate for each channel, having one I²C-bus field per channel: IBL1, IBL2 and IBL3. The ratio between the brightness and cut-off ranges depends on the brightness range selection. See Figure 16. GNDP Figure 16: CO1, CO2 and CO3 Outputs while MOD = 1 CO (1) ib (3) ibl (3) DC: differential cut-off AC: ibl (1,2,3) = I²C: IBL1, IBL2, IBL3 ibof ib (2) ibof DC: common cut-off/brightness ibof AC: video amp. biasing I²C: IBOF ibmin ibmin ibmin fixed DC Channel 1 Channel 2 Channel 3 17 16 15 CO1 CO2 CO3 iblac (1) iblac (2) CO (3) briac CO (2) briac briac iblac (3) cut-off I²C: IBL1, IBL2, IBL3 brightness through cathods I²C: BRIG COmin COmin COmin fixed DC Channel 1 Channel 2 Channel 3 When bit MOD is in position DC (= ), the output voltage on CO3 output is a sum of the brightness bridc and a fixed COmin providing a pedestal. Outputs CO1 and CO2 are floating with internal 16/34
ST9212 Functional Description resistors of approximately 4 kω to ground. The bridc varies with bits BRIG[7:] and does not depend on bits BRIGRG[1:]. See Figure 17. Figure 17: CO1, CO2 and CO3 Outputs while MOD = 19 GNDP 17 16 15 CO1 CO2 CO3 CO (3) bridc brightness through G1 I²C: BRIG COmin fixed DC Channel 1 Channel 2 Channel 3 Note: Channels 1 and 2 shown with CO1 and CO2 outputs left open 17/34
Functional Description ST9212 2.1 Signal Waveforms Figure 18 gives a summary of main signals waveforms. Figure 18: Signal Waveforms Control signals BLKI HS Clamp signals ICP OCP OSD signals ideo input IN1 (2,3) FBLK OSD input OSD1 (2,3) ideo output OUT1 (2,3) 2.11 Miscellaneous 2.11.1 Stand-by Mode The device is set in Stand-by mode either by means of bit PASTBY or by lowering the CCP supply voltage below the CCPS threshold. Once in Stand-by mode, the device does not process the video signal and its power consumption is significantly reduced. The I²C-bus interface remains operational. A low level is forced on the AMPCTL output. Refer to Section 4: Electrical Specifications for values. 2.11.2 AMPCTL Output Black-level Infra-black level The AMPCTL is designed to control a video power amplifier. It provides a three-level logical signal that depends on bits ASTBY and ABLEN, as well as on the operating mode (stand-by / normal) of the device. Figure 19 gives all possible states of the AMPCTL output. Refer to Section 4: Electrical Specifications for electrical parameter values. Pin AMPCTL is of push-pull type. It must not directly 18/34
ST9212 Functional Description be grounded in the application and it can be left floating. Only video amplifiers provided with an appropriate control input can take advantage of the signal on the AMPCTL output. Figure 19: AMPCTL Output States BLKI signal AMPHI AMPCTL pin signal AMPBL I²C-bus bits ASTBY PASTBY ABLEN CCP X 1 1 X X X > STBTH Note: X stands for don t care value 1 X X X > STBTH > STBTH < STBTH AMPSB GND 19/34
I²C-Bus Interface Specifications 3 I²C-Bus Interface Specifications ST9212 The device is compatible to general I²C-bus specification. Its slave write address is DCh. Subaddress (Sad) auto-incrementing is not available. Only Write mode is supported. The control register map is given in Table 4. Bold weight denotes default values assumed at power-on reset. The power-on reset is effected every time that the supply voltage on CCA pin drops below PORTH threshold (Refer to electrical specifications). In order to ensure compatibility with future devices, all Reserved bits are to be set to once uploaded by the control software. Table 4: I²C-Bus Register Map Sad b7 b6 b5 b4 b3 b2 b1 b 1 CRST Reserved 1 2 BRIG 1 3 DRIE1 Reserved 1 4 DRIE2 Reserved 1 5 DRIE3 Reserved 1 6 Reserved BRIGRG 1 7 Reserved OSDCRST 1 1 OCPTG TST1 TST BCSC1 BCWDTH BCEDGE BCSC 8 :BLK :Normal :Normal :Trig mode :Rising :HS trig 1 1:ICP 1:Test 1:Test 1:HS pulse 1:Falling 1:BLK trig ASTBY ABLEN Reserved TST2 Reserved MOD SWBLK BLKPOL 9 :Normal :Bl. disable :Test :DC :Disable :Non-inv. 1:Standby 1:Bl. enable 1:Normal 1:AC 1:Enable 1:Inverted A IBL1 1 B IBL2 1 C IBL3 1 PASTBY Reserved TST4 TST3 BW D :Normal :Normal :Normal 1:Standby 1:Test 1:Test 1 E F 1 :.2 1:.4 IP IBOF IBLRG 1 PBGEN PBINS Reserved PBCRST Reserved PBBRIG :Disable 1:Enable :PB Pin 1:Perman. :Wide 1:Narrow 1 1 PBIEN PBIAM Reserved PBITC Reserved :Disable 1 1 1:Enable 2/34
ST9212 I²C-Bus Interface Specifications 3.1 I²C-bus Register Descriptions Sad1 Read/Write Reset alue: 1 (8h) 7 CRST[6:] alues and 7Fh in field CRST[6:] are prohibited. Bits[7:1] = Contrast Adjustment (CRST) Bit = Reserved Sad2 Read/Write Reset alue: 1 (8h) 7 BRIG[7:] Bits[7:] = Brightness Adjustment (BRIG) In AC mode, this value is added to infrablack levels and output on pins CO1, CO2 and CO3. In DC mode, it is output all alone on pin CO3. Sad3 Read/Write Reset alue: 1 (8h) 7 DRIE1[6:] alues and 7Fh in field DRIE1[6:] are prohibited. Bits[7:1] = Gain Adjustment on Channel 1 (DRIE1) Bit = Reserved Sad4 Read/Write Reset alue: 1 (8h) Bit = Reserved Sad5 Read/Write Reset alue: 1 (8h) 7 DRIE3[6:] alues and 7Fh in field DRIE3[6:] are prohibited. Bits[7:1] = Gain Adjustment on Channel 3 (DRIE3) Bit = Reserved. Sad6 Read/Write Reset alue: 1 (1h) 7 BRIGRG [1:] Bits[7:2] = Reserved. Bits[1:]= Brightness Adjustment Range (BRIGRG) Four positions. See Section 4.4: Dynamic Electrical Characteristics. Sad7 Read/Write Reset alue: 11 (9h) 7 OSDCRST[3:] Bits[7:4] = Reserved. Bits[3:]= OSD Contrast Adjustment Sad8 Read/Write Reset alue: 1 (4h) 7 DRIE2[6:] alues and 7Fh in field DRIE2[6:] are prohibited. Bits[7:1] = Gain Adjustment on Channel 2 (DRIE2) 7 OCPT G TST[1:] BCSC 1 BCWDTH[1:] BCED GE BCSC Bit 7 = Output clamping pulse selection : Pulse triggered by BLK input (default) 1: Internal ICP pulse 21/34
I²C-Bus Interface Specifications ST9212 Bits[6:5] = Test mode activation for device testing in fabrication. When performing software blanking through SWBLK bit, TST1 bit must be set to 1. : Normal operation mode (Default) 1: Test mode Bits[4,] = Blanking and clamping pulse source. Bits[3:2] = Width of ICP pulse when bit BCSC1 is. Bit 1 = When HS pin is selected to trigger the ICP pulse generator. : Trailing edge of HS pulse (Default) 1: Leading edge of HS pulse When BLK pin is selected to trigger the ICP pulse generator: Refer to BLKPOL bit description. Sad9 BCSC1 BCSC Selected Source HS pin trigger (Default) 1 BLK pin trigger 1 Don t care HS pin pulse BCWDTH Read/Write Reset alue: 1 (1h) BCPC Width.33 µs 1.66 µs (Default) 1 1 µs 1 1 1.33 µs BCEDGE BLKPOL Trigger on BLK Rising edge (default) 1 Falling edge 1 Falling edge 1 1 Rising edge 7 ASTB ABLE TST2 MOD SWBL BLKP Y N K OL Bit 7 = Amplifier standby selection. : Normal (default) 1: Standby Bit 6 = Amplifier blanking enable. The bit is don t care whenever bit ASTBY is in Standby position. : Blanking pulse not generated (default) 1: Blanking pulse generated Bit 5 = Reserved. Bit 4 = Test mode activation for device testing in fabrication. : Test mode 1: Normal operation mode (Default) Bit 3 = Reserved. Bit 2 = Application mode selection. : Application with DC-coupled cathodes. (Default) 1: Application with AC-coupled cathodes. Bit 1 = Permanent blanking of video channels through software. : Disable, blanking gated with signal on BLK pin. (Default) 1: Permanent blanking. Bit TST1 must also be set to 1. Bit = Blanking signal (H-fly back) polarity inversion. For correct operation, the internal BLKI pulse after this controlled inversion must be positive. : Non Inverted, good for positive blanking pulse (Default) 1: Inverted, good for negative blanking pulse SadA, SadB and SadC Read/Write Reset alue: 1 (8h) 7 IBL1[7:] IBL2[7:] IBL3[7:] Bits[7:] = Infra-black (Cut-off) Level Control, Channels 1 to 3 (IBLx) In DC-coupling mode, the register controls the pedestal of corresponding video channel signal. In AC-coupling mode, the register controls the level on outputs CO1, CO2 or CO3, respectively. SadD Read/Write Reset alue: 1 (8h) 7 PAST TST[4:3] BW[3:] BY Bit 7 = Preamplifier and Amplifier STandBY selection : Normal (default) 1: Standby Bit 6 = Reserved. 22/34
ST9212 I²C-Bus Interface Specifications Bits[5:4] = Test mode activation bits for device testing in fabrication. : Normal operation mode (Default) 1: Test mode Bits[3:] = Internal band width limitation control. Refer to electrical characteristics. SadE Read/Write Reset alue: 11 1 (C1h) 7 IP Bit 7 = ideo Insertion Pulse depth. :.2 1:.4 (default) Bits[6:1] = Infra-black level offset control simultaneously on all three video channels. Bit = Control range of infra-black level adjustments via IBL1, IBL2 and IBL3 registers. Acts either on video signal channels or CO1, CO2, CO3 outputs. Refer to electrical characteristics. : Wide 1: Narrow (default) SadF IBOF[5:] Read/Write Reset alue: 11 (9h) IBLR G 7 PBGE PBIN PBCRST[1:] PBBRIG[1:] N S Bit 7 = PictureBooST General Enable. (PBGEN) : Disable, function inhibited (Default) 1: Enable, function active Bit 6 = PictureBooST Insertion Control. (PBINS) : PB pin insertion (Default) 1: Permanent insertion regardless of signal on PB pin Bit 5 = Reserved. Bits[4:3] = PictureBooST Contrast Control (PBCRST) Bit 2 = Reserved. Bits[1:] = PictureBooST Brightness Control (PBBRIG) Sad1 Read/Write Reset alue: 1 1 (28h) 7 PBI PBIAM[1:] PBITC[2:] EN Bit 7 = PictureBooST vivacity and brightness enable. : Disable (default) 1: Enable Bits[6:5] = PictureBooST ivacity Amplitude Control. Bit 4 = Reserved. Bits[3:1] = PictureBooST ivacity Time Constant Control. Bit = Reserved. 23/34
Electrical Specifications 4 Electrical Specifications ST9212 4.1 Absolute Maximum Ratings All voltages refer to the GNDA pin. Symbol Parameter Min. Max. Units CCA Supply voltage on CCA (Pin 7) TBD 5.5 CCP Supply voltage on CCP (Pin 21) TBD 8.8 IN oltage at any pin except video inputs and supply pins TBD 5.5 I oltage at video inputs (Pins 1,3 and 5) TBD 1.4 ESD ESD susceptibility Human Body Model (1 pf discharge through 1.5 kω) TBD ±2 k T STG Storage Temperature -4 +15 C T OPER Operating Junction Temperature -4 +15 C 4.2 Thermal Data Symbol Parameter Min. Typ. Max. Units R thja Junction-to-Ambient Thermal Resistance 6 C/W T AMB Operating Ambient Temperature 7 C/W 4.3 Static Electrical Characteristics T AMB = 25 C, CCA = 5, and CCP = 8, unless otherwise specified. All voltages refer to the GNDA pin. Symbol Parameter Test Conditions Min. Typ. Max. Units Supply CCA Supply oltage Pin 7 4.5 5 5.5 CCP Power Stage Supply oltage Pin 21 4.5 8 8.8 CCPS Power Supply oltage Stand-by Threshold Pin 21 2.5 3. 3.5 I CCA CCA Supply Current CCA = 5 (PBGEN Disable) CCA = 5 (PBGEN Enable) I CCP CCP Supply Current CCP = 8 5 ma I S Total Supply Current in Stand-by Mode Pin 21 and pin 7 6 ma Inputs and Outputs I ideo Input voltage amplitude.7 1 65 85 ma ma O Output voltage swing.5 (1) CCP -.5 IL Low level input voltage (TTL) OSD, FBLK, PB, HS,BLK.8 IH High level input voltage (TTL) OSD, FBLK, PB, HS,BLK 2.4 I IL BLK input current BLK -.1 +1. ma I IN Input current OSD, FBLK, PB -1 1 µa 24/34
ST9212 Electrical Specifications Symbol Parameter Test Conditions Min. Typ. Max. Units R HS Input resistance HS 4 kω AMPSB Output voltage at AMPCTL pin, standby (Figure 18) I²C-bus bit ASTBY = 1 or/and CCP < CCPS Sink current 2µA 8 2 m AMPBL Output voltage at AMPCTL pin, blanking (Figure 18) I²C-bus bit ASTBY = 1 I²C-bus bit ABLEN = 1 Sink current µa BLKI at high level TBD 1.6 TBD AMPHI Output voltage at AMPCTL pin, no standby, no blanking (Figure 18) I²C-bus bit ASTBY = and CCP > CCPS Sink current µa 3.1 4.4 Dynamic Electrical Characteristics T AMB = 25 C, CCA = 5, CCP = 8, i =.7 PP, C LOAD = 5 pf, R S = 1 Ω serial resistor between output pin and C LOAD, unless otherwise specified. x denotes channel number and can assume values of 1, 2 and/or 3. All voltages refer to the GNDA pin. Symbol Parameter Test Conditions Min. Typ. Max. Units ideo Output Signal (Pins 18, 2 and 22) - Contrast and Drive G Maximum total gain for video path with PictureBooST off OM Maximum video output voltage (2) ON CAR DAR Nominal video output voltage Contrast control range Drive control range I²C-bus fields CRST = 7Eh, DRIEx =7Eh PBGEN = I²C-bus fields CRST = 7Eh, DRIEx =7Eh PBGEN = PBGEN = 1 I²C-bus fields CRST = 4h, DRIEx = 4h (POR state) Max. to min. contrast (CRST = 7Eh to CRST = 1h) Max. to min. drive (DRIEx = 7Eh to DRIEx = 1h) GM Gain matching (3) I²C-bus fields CRST = 4h, DRIEx = 4h (POR state) ideo Output Signal - OSD OSD OSD insertion output level referenced to output black level DRIEx = 7Eh OSDCRST = Fh OSDCRST = h 12 db ideo Output Signal - IP IP ideo Insertion Pulse level From Infrablack level to black level IP = 1 IP = (4).2 ideo Output Signal - Infra Black Level (Figure 15) 2.8 4. TBD 28 db 13 db ±.1 db ibmin Infra black level pedestal.4 4.9 pp pp ibof Infra black offset component IBOF = 3Fh IBOF = h 2.1 ibl [x] Infra black level component IBLx = h or MOD = 1 (AC mode) IBLx = FFh, MOD = (DC mode) IBLRG = 1 IBLRG = 1.3 1.8 25/34
Electrical Specifications ST9212 Symbol Parameter Test Conditions Min. Typ. Max. Units Cut-off Output (Pins CO1, CO2 and CO3) COmin Pedestal level on COx outputs.5 COmax briac bridc iblac (x) Upper limitation on COx outputs Brightness component in AC mode (Figure 16) Brightness component in DC mode on CO3 pin (6) (Figure 17) Cut-off component PictureBooST Block (Figure 9) G PB BriPB viv /A τ viv ABL (Figure 9) G ABL Maximum gain PictureBooST brightness expressed in equivalent input level ivacity amplitude as percentage of its host square pulse level before PictureBooST( A in Figure 9) ivacity time constant ABL gain Sum of briac + iblac or bridc exceeding the limit MOD = 1 (AC mode) BRIG = h BRIG = FFh: BRIGRG = b BRIGRG = 1b BRIGRG = 1b BRIGRG = 11b MOD = (DC mode) BRIG = h BRIG = FFh MOD = (DC mode) MOD = 1 (AC mode) IBLx = h IBLx = FFh: IBLRG = IBLRG = 1 PBGEN = 1 PBCRST = b PBCRST = 1b PBCRST = 1b PBCRST = 11b PBGEN = 1 and PBIEN = 1 PBBRIG = b PBBRIG = 1b PBBRIG = 1b PBBRIG = 11b PBGEN = 1 and PBIEN = 1 PBIAM = b PBIAM = 1b PBIAM = 1b PBIAM = 11b PBGEN = 1 and PBIEN = 1 PBITC = b PBITC = 1b PBITC = 111b ABL >3.2 ABL = 1 CCA -.5 ThABL ABL threshold voltage 3 I ABL ABL input current ABL = 3.2 ABL = 1.4.8 1.25 1.9 4 3.7 1.85.8 1.6 2.3 3 64 48 32 16 12.5 25 37.5 5 35 245-15 -2 db db db db m m m m % % % % ns ns ns db db µa µa ideo Output Signal - Dynamic Performances (Figure 15) t r, t f Rise Time, Fall Time (5) BW Large signal bandwidth OUT = 2 PP (IP exclusive) BW = Fh BW = h OUT = 2 PP, sinus wave, -3dB BW = Fh BW = h 3.5 7 TBD TBD ns ns MHz MHz 26/34
ST9212 Electrical Specifications Symbol Parameter Test Conditions Min. Typ. Max. Units CT Crosstalk between ideo Outputs OUT = 2 PP f = 1 MHz f = 5 MHz TBD TBD db db 4.5 I²C-Bus Electrical Characteristics T amb = 25 C, CCA = 5, CCP = 8, i =.7 PP, C LOAD = 5 pf Symbol Parameter Test Conditions Min. Typ. Max. Unit s IL Low Level Input oltage On Pins SDA, SCL 1.5 IH High Level Input oltage 3 I IN Input Current (Pins SDA, SCL).4 < IN < 4.5-1 +1 µa f SCL(Max.) SCL Maximum Clock Frequency 2 khz OL Low Level Output oltage SDA pin when ACK Sink Current = 6mA 4.6 I²C-Bus Interface Timing Requirements.6 Symbol Parameter Min. Typ. Max. Units t BUF Time the bus must be free between two accesses 13 ns t HDS Hold Time for Start Condition 6 ns t SUP Set-up Time for Stop Condition 6 ns t LOW The Low Period of Clock 13 ns t HIGH The High Period of Clock 6 ns t HDAT Hold Time Data 3 ns t SUDAT Set-up Time Data 25 ns t r Rise Time of both SDA and SCL 1 µs t f Fall Time of both SDA and SCL 3 ns SDA SCL Figure 2: I²C-Bus Timing Diagram t BUF t HDS t SUDAT t HDAT t SUP thigh t LOW Notes on Electrical Characteristics Note 1. The video on the preamplifier output must remain above.5 even for high frequency signals. 2. Assuming that the video output signal remains inside the linear area of the preamplifier output (between.5 and CCP -.5). 27/34
Electrical Specifications ST9212 3. Matching measured between the different outputs. 4. When the Blanking signal is present on the BLK input, the IP insertion pulse is always generated. Only its amplitude changes (see Figure 12). 5. t R, t F are simulated values, assuming an ideal input signal with rise/fall time =.1 ns. Measured between 1% and 9% of the pulse height. 6. When MOD =, the CO1 and CO2 are internally grounded through resistors. 28/34
ST9212 5 Soldering Information Soldering Information The device can be soldered by wave, dipping or manually. Wave soldering is the preferred method for mounting through-hole mount IC packages on a printed-circuit board. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 26 C; solder at this temperature must not be in contact with the joints for more than 5 seconds.the total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T STG [max]). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Manual soldering Apply the soldering iron (24 or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 3 C it may remain in contact for up to 1 seconds. If the bit temperature is between 3 and 4 C, contact may last up to 5 seconds. 29/34
Package Mechanical Data 6 Package Mechanical Data ST9212 Figure 21: 24-Pin Plastic Dual In-Line Package, Shrink 3-mil Width E E1 A1 A2 A L b b2 e Stand -o ff.15 in. ea 24 1 D Table 5: Package Dimensions Dim. Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 5.8.2 A1.51.2 A2 3.5 3.3 4.57.12.13.18 b.38.46.56.15.18.22 b2.89 1.2 1.14.35.4.45 c.23.25.38.9.1.15 D 22.35 22.61 22.86.88.89.9 E 7.62 8.64.3.34 E1 6.1 6.4 6.86.24.252.27 e 1.78.7 ea 7.62.3 eb 1.92.43 ec. 1.52..6 L 2.54 3.3 3.81.1.13.15 Number of Pins N 24 13 12 E1 c E ec eb eb.15 in..38 mm. Gage Plane 3/34
ST9212 7 Input/Output Diagrams Input/Output Diagrams Figure 22: ideo Inputs Figure 25: Hsync Input CCA CCA 3k IN1 1 HIGH IMPEDANCE 2 GNDA Idem for pads IN2 (3) and IN3 (5) GNDA GNDL Figure 23: ABL Input Figure 26: PictureBooST and OSD Inputs CCA CCA ABL 4 GNDA 1k Figure 24: Amplifier Control Output AMPCTL 23 CCA 1 OSD1 9 GNDA Idem for pads OSD2 (1), OSD3 (11) PB (8), FBLK (12) Figure 27: Analog Supplies CCA 7 LOGIC PART (8) GNDL GNDA GNDA 6 31/34
Input/Output Diagrams ST9212 Figure 28: I²C-Bus Figure 31: Output Stage Ground SCL 13 (8) GNDA 3kΩ 4pF GNDL GNDP 19 CCA SDA 14 GNDA 3kΩ 4pF GNDL GNDA Figure 29: Output Stage Supply and ideo Outputs CCP 19 (2) OUT1 22 GNDA GNDP Idem for pads OUT2 (2) and OUT3 (18) Figure 3: Blanking / ideo Clamping Sync Inputs BLK 24 CCA GNDA GNDL Figure 32: Cut-off DAC Output Pins CO1 17 GNDA CCA Idem for pads CO2 (16) and CO3 (15) 32/34
ST9212 8 Revision History Revision History Table 6: Summary of Modifications ersion Date Description 1. 14 Nov 22 First Issue 1.1 3 Jul 23 Minor modifications. 33/34
ST9212 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 23 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. www.st.com 34/34