Introduction to JTAG / boundary scan-based testing for 3D integrated systems (C) 2011 - GOEPEL Electronics - www.goepelusa.com
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Outline JTAG / boundary-scan applications Ways to test mixed-signal PCBA with JTAG / bscan Example: 3-D stacked, mixed-signal dies 3
Benefits of JTAG / boundary scan Test for manufacturing defects at board and system level Access to on-chip test / debug / emulation resources In-system programming Efficient ATPG tools, pin level diagnostics Deterministic (predictive) test coverage Standardized: IEEE 1149.1, 1149.4, 1149.6, 1149.7, 1500, 1532, P1149.8.1, P1687, P1838,... 4
What is Boundary Scan? A little bit of history (and outlook)... 5
Basics of IEEE 1149.1 IEEE 1149.1 specifies... Test resources to be implemented in devices Boundary Scan Description Language (BSDL) Digital Core Logic /TRST TDI TCK TMS ID Reg IR BP TAP Controller TDO 6
JTAG / boundary scan applications 7
Outline Board level JTAG / boundary-scan applications Ways to test mixed-signal PCBA with JTAG / bscan Example: 3-D stacked, mixed-signal dies 8
Ways to test mixed-signal PCBA w/ bscan Combine bscan (digital) w/ functional test (analog) Combine bscan (digital) w/ ICT / FPT (analog) Utilize mixed-signal I/O modules, controlled by the boundary scan test system IEEE 1149.4 enabled devices ADC/DAC with IEEE 1149.1 access Loop-back on UUT (DAC to ADC loop-backs) PCBA = Printed circuit board assembly ICT = In-circuit tester FPT = Flying probe tester ADC = Analog/Digital converter DAC = Digital/Analog converter UUT = Unit under test bscan - boundary scan IEEE 1149.1 / boundary scan = simple, embedded, standardized access to internal device structures 9
Boundary scan and ICT / FPT Probes can be used to provide access with digital test resources and with analog test resources 10
Mixed-signal test principle with IEEE 1149.1 Analog to Digital Converter: Provide analog stimulus with tester channel or measure circuit nodes Read digital output with BScan 11
Mixed-signal test principle with IEEE 1149.1 Digital to Analog Converter: Provide digital stimulus with BScan Measure analog output with tester channel or functional test equipment 12
Mixed-signal test principle with IEEE 1149.4 13
Mixed-signal test principle with IEEE 1149.4 14
Mixed-signal test principle with IEEE 1149.4 15
JTAG / boundary-scan systems SCANFLEX TAP Transceiver 2... 8 programmable TAP s 32 dynamic digital I/O 3 static digital I/O 2 analog I/O 3 trigger lines SFX I/O module slot SFX/LS port various form factors for stand-alone systems and for 3rd party ATE integration SYSTEM CASCON software Useful for mixed-signal tests SCANFLEX I/O module Several types, such as: digital I/O (96 channels) differential I/O (50 pairs) mixed signal I/O analog measurement IEEE 1149.4 TAP VarioCORE modules Custom designs SFX/carrier SCANFLEX Controller PCI, PCI Express, USB, LAN, FireWire, PXI, PXI Express, VXI, LXI Three performance classes A, B, and C Up to 80 MHz TCK HYSCAN support SPACE II chip set 2 SFX/LS ports 16
JTAG / boundary-scan systems CION I/O modules Several types, such as: digital I/O (96 channels) mixed-signal I/O (96 or 192 digital I/O, 1149.6 I/O, analog I/O, relays, opto-coupled, I/O, and more) DIMM interface modules PCI interface modules Scan chain controlled Useful for mixed-signal tests SYSTEM CASCON software ScanBooster TM Controller PCI, USB, Cables PCI Express Low-cost controller Up to 16 MHz TCK 2 programmable TAP s 32 dynamic digital I/O 3 static digital I/O 2 analog I/O 3 trigger lines fixture integrated TIC modules 17
PCBA vs. SOC / SIP / MCM / 3D Stacked Die Multi-die IC level test access problem similar to PCBA Similar test strategy, just at different scale 18
Outline JTAG / boundary-scan applications Ways to test mixed-signal PCBA with JTAG / bscan Example: 3-D stacked, mixed-signal dies 19
Observations Test bus access: pins to bottom die, from there through stacked interconnects; need special DFT with layout requirements (where to place TSVs for inter-die test bus signal interconnects) IEEE 1149.1 focuses on die to die (chip to chip) interconnects IEEE 1500 for core level boundary scan IEEE P1687 will offer standardized access to embedded instruments, incl. IEEE 1500, BIST, BERT, etc. IEEE 1149.7 offers attractive test bus signal network between cores and dies IEEE P1838 to standardize 3D stacked die test 20
3D stacked dies This and the following slides are just examples of boundary scan configurations - others are possible. This is a conceptual drawing and does not represent an actual implementation! Die-to-Die interconnects Number of pins, boundary scan cells, analog or digital logic, and size of chips, TSVs, and solder balls are not in scale (e.g. test logic is very small compared to functional logic, and the number of pins and boundary scan cells is much higher than illustrated here). Power Analog I/O 21
3D stacked dies Please note that this is a conceptual drawing and does not represent an actual implementation! Die-to-Die interconnects Number of pins, boundary scan cells, analog or digital logic, and size of chips, TSVs, and solder balls are not in scale (e.g. test logic is very small compared to functional logic, and the number of pins and boundary scan cells is much higher than illustrated here). 22
3D stacked dies Please note that this is a conceptual drawing and does not represent an actual implementation (e.g. TBIC circuitry is missing)! Die-to-Die interconnects Number of pins, boundary scan cells, analog or digital logic, and size of chips, TSVs, and solder balls are not in scale (e.g. test logic is very small compared to functional logic, and the number of pins, boundary scan cells and ABMʼs is typically much higher than illustrated here). 23
3D stacked dies Mixed-signal die Please note that this is a conceptual drawing and does not represent an actual implementation (e.g. TBIC circuitry is missing)! Die-to-Die interconnects Number of pins, boundary scan cells, analog or digital logic, and size of chips, TSVs, and solder balls are not in scale (e.g. test logic is very small compared to functional logic, and the number of pins, boundary scan cells and ABMʼs is typically much higher than illustrated here). 24
Summary IEEE 1149.1 has been created for digital test, but...... what about analog / mixed-signal circuitry? Along came IEEE 1149.4, specifying mixed-signal boundary scan resources, but are there any insertion tools for 1149.4 features? Mixed-signal tests based on IEEE 1149.1 are possible using A/D converters and mixed signal tester resources IEEE P1687 will offer new possibilities IEEE 1581 may help for non-boundary scan chips / dies (e.g. stacked memory dies without wrapper boundary register) 25
Contact info, upcoming sessions June 6, 2011 at 12:30 PM EDT: Commercial testing of next generation circuits and systems, Scott Bulbrook, DA-Integrated June 20, 2011 at 12:30 PM EDT: Research frontiers in DFT and BIST, Steve Sunter, Mentor Graphics Heiko Ehrenberg GOEPEL Electronics +1 512 501 6535 www.goepelusa.com h.ehrenberg@goepelusa.com 26