Macronix OctaFlash Serial NOR Flash White Paper Introduction Macronix, a leading provider of non-volatile memory solutions, is the world s leading supplier of ROM and Serial NOR Flash products. Macronix currently produces ROM, NOR Flash, and NAND Flash memories in a wide range of densities for embedded, consumer, enterprise, wireless, and automotive applications. NOR flash is normally used for system boot up, application code and data storage. Today s multi task systems require flash to be not only high performance, high density, and high quality but also low cost, low pin count and easy to implement using a simple interface. Higher performance requires higher data bandwidths, but existing Serial NOR Flash devices have two major factors that are bandwidth limiting. The first factor is the maximum number of I/Os is typically limited to four (Quad I/O). The second and more important factor is the maximum practical clock rate is ~133MHz. This frequency limitation is not necessarily device related; it is primarily due to the round trip clock and data path delays that exist between the SoC/ASIC and the flash device. At higher clock rates, output data from the flash device is skewed relative to the SoC/ASIC clock and arrives too late to be reliably captured by the SoC/ASIC. This paper will show how the new Macronix OctaFlash Serial NOR Flash overcomes these two bandwidth limitations and still provides a perfect low cost, low pin count solution using a simple interface. OctaFlash Serial NOR Flash Design Macronix OctaFlash provides high operational performance by introducing several innovative design features: 8 I/O pins (SIO[7:0] in "Figure 1: MCU and Flash Block Diagram"): A Byte of data is transferred each clock cycle ("Figure 2: Page Program (PP) Sequence in x8 STR-OPI Mode"). This allows for twice the data transfer rate of current quad I/O flash and 8 times that of flash using single I/O mode at the same clock rate. Figure 1: MCU and Flash Block Diagram P/N: AN0447 1
WHITE PAPER Figure 2: Page Program (PP) Sequence in x8 STR-OPI Mode tchsh CS# SCLK tslch SIO[7:0] 02h FDh A[31:24] A[23:16] A[15:8] A[7:0] D0 D1 D254 D255 DTR (Double Transfer Rate) mode is supported and uses both the rising and falling edges of the clock to transfer instructions, addresses, and data ("Figure 3: Read Mode in x8 DTR-OPI"). This effectively doubles the bandwidth without increasing the number of I/O pins or clock rate. When using a 200MHz clock, DTR allows the device reach its target bandwidth of 400MB/sec. Figure 3: Read Mode in x8 DTR-OPI CS# SCLK DQS SIO[7:0] EEh 11h A[31:24]A[23:16] A[15:8] A[7:0] D1 D0 D3 D2 Address Dummy word unit word unit P/N: AN0447 2
Data Strobe (DQS) pin: an output reference clock added to enable the SoC/ASIC to reliably capture data at much higher clock rates. The DQS can be treated as a special type of data as they are bundled and tightly linked with data (source synchronous). Strobes save power because they are active only in the presence of data, unlike clocks, which are active continuously. It only needs one extra pin (does not use or require an inverse DQS pin) for signal synchronization. When the system is using high speed DTR mode, the Macronix flash device synchronizes DQS with SIO[7:0] output data to help the SoC/ASIC locate the center of the valid data window known as the data eye ("Figure 4: DTR Mode SIO[7:0] Data Eye, DQS, and SoC/ASIC Data Capture Strobe"). Since DQS output edges are aligned with the SIO[7:0] output edges in DTR mode, the SoC/ASIC finding the center of DQS will also locate the center of the data eye and can be used to capture data reliably at very high clock rates. Figure 4: DTR Mode SIO[7:0] Data Eye, DQS, and SoC/ASIC Data Capture Strobe Data Valid Window SIO[7:0] data eye DQS aligned with SIO[7:0] DQS SoC/ASIC data capture strobe derived from DQS P/N: AN0447 3
Single I/O compatibility: Legacy and current applications usually boot up in Single I/O mode and switch to high speed mode to access the flash memory later on. To remain compatible, Macronix OctaFlash devices retain Single I/O functionality after power-up to reduce firmware development time and helping to improve your application release schedule ("Figure 5: Page Program (PP) Sequence in x1 Single I/O Mode"). Figure 5: Page Program (PP) Sequence in x1 Single I/O Mode CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK Command 24-Bit Address Data Byte 1 SI 02h 23 22 21 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB CS# 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 2072 2073 2074 2075 2076 2077 2078 2079 SCLK Data Byte 2 Data Byte 3 Data Byte 256 SI 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 MSB MSB MSB P/N: AN0447 4
WHITE PAPER When implementing new system components, it takes time and cost to verify the system. This Macronix solution provides a low cost and simple way to reduce your migration effort. In hardware design, the device interface is based on the traditional serial NOR interface. In addition, SoC/ASIC designs only need to add an extra 4 I/O pins to implement the Octa I/O solution. There is no requirement to spend extra cost to add components or related peripheral devices, such as a PHY, to enable the high speed DTR mode. In software design, it is backward compatible with Single I/O mode, so that software modification only needs to focus on Octa I/O mode implementation. The self-timed Page Program Cycle time (tpp) is initiated as soon as Chip Select (CS#) goes high. CS# must remain low during the whole Page Program command sequence, and CS# must go high exactly at the byte boundary (the latest 8 bits of data being latched in SPI mode) or while SCLK is low in DTR-OPI mode. Otherwise, the instruction will be rejected and will not be executed. The sequence of issuing PP instruction is: CS# goes low sending PP instruction code 4-byte address at least 1-byte of data in SPI and STR-OPI mode; at least two bytes of data in DTR-OPI mode CS# goes high ("Figure 6: DTR Mode Write Waveform").. Figure 6: DTR Mode Write Waveform tslch tclsh CS# SCLK SIO[7:0] 02h FDh A A A A [31:24] [23:16] [15:8] [7:0] D1 D0 D255 D254 word unit word unit Note: tslch=cs# Active Setup Time (relative to SCLK); tclsh=cs# active hold time DQ to DQS Skew control: DQS-DQ skew can occur when the routing of output paths are not matched and when there is simultaneous-switching-noise. For high-speed operation, DQS-DQ skew adjustment becomes critical. The Macronix OctaFlash provides a skew adjustment feature that minimizes skew to enhance the high-speed system interface. Preamble feature: The Preamble Bit data pattern is an alternative to the DQS method of finding the center of the output data eye. It is designed as a known 16-bit data pattern that can be used as a reference while the SoC/ASIC adjusts its data latch strobe delay. It can be enabled or disabled by setting the Configuration Register. High reliability and quality: Very cold or hot environments can have a negative impact on flash. Macronix understands this and has developed flash capable of operating reliably in the industrial temperature ranges of -40 C to 85 C. Macronix devices are developed with specific NOR technology that is compliant with JEDEC standards that ensure endurance and data retention requirements. Macronix OctaFlash products have an endurance of 100K cycles and 20 years of data retention. Macronix also has an Automotive grade program where wider temperature ranges are supported while still supporting our basic endurance and data retention standards. P/N: AN0447 5
High Level Solution Macronix 1.8V OctaFlash support a 200MHz clock rate with DTR in x8 mode to achieve a 400MB/sec throughput which makes it ideal for in XiP (Execute-in-Place) applications as well as in SnD (Store and Download) applications. "Figure 7: Serial NOR Flash Read Performance" illustrates the Read performance improvement which can be realized when using the OctaFlash at 200MHz with DTR vs traditional Single I/O Serial NOR Flash or current fast Quad I/O products, which typically run at 133Mhz to 166MHz without DTR. Figure 7: Serial NOR Flash Read Performance 450.00 400.00 350.00 300.00 250.00 200.00 150.00 100.00 50.00 0.00 MB/s Traditional x1 I/O 133MHz Current fast solution x4 I/O 133MHz 6 ~ 24 times faster Throughput (MB/s) x8 I/O 200MHz DTR Serial NOR Flash read performance, when compared to Parallel NOR Flash, used to be limited by I/O pin count. Now, the OctaFlash x8 I/O bus has doubled the I/O pin count vs QSPI solutions, and provides a better solution than any previous serial flash family. And with OctaFlash support of DTR mode, it provides 6 times better read performance than the Page Read function of Parallel NOR Flash and 2 times the random read throughout using XIP mode. With these kind of performance improvements, it is obvious that OctaFlash offers a clear advantage for system boot up, data transferring, and massive data accessing (such as GUI) applications. P/N: AN0447 6
Figure 8: Parallel NOR Flash, and Serial NOR Flash Read Performance 450.00 400.00 350.00 300.00 250.00 200.00 150.00 100.00 50.00 0.00 MB/s Parallel NOR Flash x16, Page Read 70ns (taa), 25ns (tpa) 6 times faster Throughput (MB/s) Serial NOR Flash x8 I/O 200MHz DTR Figure 9: Parallel NOR Flash, NAND Flash and Serial NOR Flash Random Read Performance 400.00 350.00 300.00 250.00 200.00 150.00 100.00 50.00 0.00 MB/s 1.8~2.6 times faster 0 1 Byte 16 Byte 32 Byte 64 Byte 128 Byte 256 Byte Throughput (MB/s) Serial NOR Flash 8xI/O DTR 200MHz DTR Parallel NOR Flash x16, Page Read 70ns (taa), 25ns (tpa) Serial NOR Flash 4xI/O 133MHz NAND Flash x8, 25us (tr) 20ns (twc), 20ns (trc) P/N: AN0447 7
The NAND flash interface is very similar to serial flash when using the page read function to reduce data read time. Macronix Octa I/O DTR mode throughput is 8 times faster than NAND flash throughput. In performance critical applications, Macronix OctaFlash is a superior solution. Figure 10: OctaFlash vs NAND Flash Read Performance 450.00 400.00 350.00 300.00 250.00 200.00 150.00 100.00 50.00 0.00 MB/s NAND Flash x8, 25us (tr) 20ns (twc), 20ns (trc) 8 times faster Throughput (MB/s) Serial NOR Flash x8 I/O 200MHz DTR Reducing programming time will reduce production cost in a factory Mass Production line. Macronix OctaFlash has improved programming performance to reduce MP cost and reduce data storage time requirements. OctaFlash throughput is 2 times that of similar density Macronix devices. Figure 11: Serial NOR Flash Page Program Performance 1.400 1.200 1.000 0.800 0.600 0.400 0.200 0.000 MB/s x1 I/O 133MHz x4 I/O 133MHz 2 times faster Throughput (MB/s) x8 I/O 200MHz DTR Notes: 1. Macronix Octa I/O device program time: 200us (Typ.) 2. Current Macronix device program time: 500us (Typ.) P/N: AN0447 8
Summary Macronix OctaFlash with high speed DTR allows for a fast system boot and short data access times. By making use of the DQS (Data Strobe) pin, your system can more reliably receive stable data during high speed DTR data transfers. In addition, Macronix competitive pricing makes this an ideal high performance solution. Macronix OctaFlash devices target multiple product applications including automotive control and entertainment systems, DSLR cameras, laptop gamming, and FPGA configuration. These systems require high speed access to reduce boot up time and improve multitasking system performance. Figure 12: OctaFlash Field Applications Automotive Cluster ADAS Camera Data Communication FPGA Configuration Digital Camera P/N: AN0447 9
Revision History Revision No. Description Page Date Rev. 1 Initial Release ALL 17 th, June, 2016 P/N: AN0447 10
Except for customized products which have been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright Macronix International Co., Ltd. 2016. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, elite- Flash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vee, Macronix MAP, Rich Au dio, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto (if any) are for identification purposes only. For the contact and order information, please visit Macronix s Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. P/N: AN0447 11