a (centimeters) AD9884A Evaluation Kit Documentation Includes Documentation for: - AD9884A Evaluation Board - SXGA Panel Driver Board Rev 0 1/4/2000 Evaluation Board Documentation For the AD9884A
Purpose The purpose of the AD9884A evaluation board is both to demonstrate the performance of the AD9884A and to serve as an implementation example for design and layout of the device. To aid in real-world evaluation, it was designed so that it could be connected as easily as possible into another pc board, (such as a graphics controller board). Requirements All that is needed to use this board are a 5V power supply, a graphics signal (through the 15 pin VGA connector), and a means to program the internal chip registers. (Hardware and software for programming the internal chip register are provided when the evaluation kit is ordered.) Typical Configuration In most cases, this evaluation board will be used to digitize an analog RGB graphics signal and pass the data on to another board. To do this simply connect the graphics signal to the 15 pin VGA connect, supply 5V to the board, and program the internal serial register. (Supplying power and programming the chip are described later in this document). The digitized data, generated clock signals, and control signals are passed off the board through connector J3. Power The AD9884A evaluation board contains three 3.3V voltage regulators. These regulators are what supply power to the AD9884A. There are three regulators to match the three power supplies on the AD9884A. The best performance can be obtained from the AD9884A when the analog supply (Vd) and the PLL (PVdd) supply have their own regulators. The three regulators work nominally when supplied with 5V, but will work with a range of voltages. Power can be applied to the board through three possible connectors. (Note: only one power connection should be made since all three of these power inputs are connected together.) The first possible power connection is through J3. This would be the typical power connection when power is supplied from another board. (As is the case using the panel driver board). The second possible connection is with the connection next to J4. This connection would be made by soldering wires into the given holes then connecting them to a 5V supply and ground. The final possible connection is with connector J4. The actual connector is not supplied on board but it allows for connecting to a 5V brick type power supply like on the panel driver board. Programming the Internal Chip Registers Hardware and software for programming the AD9884A internal registers are provided. The hardware consists of a standard printer cable and a receiver chip located on the panel driver board. The programming signals come onto the AD9884A board through pins 38 & 39 on connector J3. The software is included on the installation CD and is described below: Setup Software The software is a Visual Basic program requiring Windows 95. It is included with the evaluation board kit. (See the readme.txt file for additional information). The screen output shown in figure 1 should be displayed at program execution from a successful installation.
Figure 1 AD9884A Setup Software Screen Output Channel Mode You can set channel mode, which determines if output data is output on A port only, or both A and B output ports. (Requires setting jumper W11 also) Single mode ----- (ADC clock < = 100 MHz) Dual mode ---- (ADC clock <= 140 MHz). Output Mode Output Mode in dual operation can be set to parallel or interleaved. In parallel mode data bits on A and B ports change on same clock edge. In interleaved mode A and B data are clocked out of phase. Clock Mode The Clock Mode setting in software enables or disables the chip PLL. In PLL enabled mode, the PLL divisor, HYNC polarity, VCO Range, Phase Adjust, and Charge Pump Current fields are pertinent and need to be set correctly. RGB Gain and Offset The three analog channels can have their gain and offset independently set here. Gain setting is from 0 to 255, Offset from 0 to 63.
PLL Divisor, VCO Range, Phase Adjust and Charge Pump Current The PLL divisor field is the ratio between pixel clock and input Hsync, (for example: 135MHZ / 80KHz = 1687) This input should be an odd integer. It is offset by +1 on chip. VCO range is from 0 to 3, higher settings imply higher VCO frequency. This setting is determined from required pixel clock frequency, (135 MHz SXGA would require VCO range setting of 3). Phase adjust (0 to 31) adjusts the delay between sampling clock and incoming data in (1 pixel / 32) increments. Charge pump current (Ip) setting (0-7) determines (along with Kvco, filter caps, and Divisor) the PLL loop s natural frequency and loop stability. See datasheet for design equations. Higher operating frequency typically implies higher I P. See sample settings at end of this section Polarity Hsync polarity indicates if lock is to Hsync falling (-) or rising (+) edge. If Hsync leading edge is falling, set polarity to (-). Assertion of external coast and clamp functions is determined by respective polarity setting. Clamp Clamping can be implemented using internal or external means. Internal clamping is accomplished setting the internal clamp function field and clamp placement(0 to 255) and clamp duration(0 to 255) fields. Resolution on placement and duration is 1 ADC clock cycle. Clamping is relative to trailing Hsync edge. (Clamp polarity field has no affect for internal clamp) External clamping can be done by setting Clamp function field to external. The clamp polarity field should be set for desired polarity. (+ or -) Placement and duration fields have no affect for external clamp.
Sample Settings for Evaluation Board PLL Settings Chart Horizontal 2 Mode Resolution Nominal Frequency Hs Sync Polarity PLL Divider 1 N+1 Nominal Pixel Clock (MHz) VCO Range Charge Pump Current VGA 640x480 @ 60 Hz 31.469 N 800 25.175 00 000 640x480 @ 72 Hz 37.861 N 832 31.500 00 000 640x480 @ 75 Hz 37.500 N 840 31.500 00 000 640x480 @ 85 Hz 43.269 N 832 36.000 00 001 SVGA 800x600 @ 56 Hz 35.156 N/P 1024 36.000 00 001 800x600 @ 60 Hz 37.879 P 1056 40.000 00 001 800x600 @ 72 Hz 48.077 P 1040 50.000 00 010 800x600 @ 75 Hz 46.875 P 1056 49.500 00 001 800x600 @ 85 Hz 53.674 P 1048 56.250 01 010 XGA 1024x768 @ 60 Hz 48.363 N 1344 65.000 01 010 1024x768 @ 70 Hz 56.476 N 1328 75.000 01 011 1024x768 @ 75 Hz 60.023 P 1312 78.750 01 011 1024x768 @ 80 Hz 64.000 P 1336 85.500 10 011 1024x768 @ 85 Hz 68.677 P 1376 94.50 10 011 SXGA 1280x1024 @ 60 Hz 60.020 P 1688 108.000 10 011 1280x1024 @ 75 Hz 79.976 P 1688 135.000 11 100 Note 1: ( PLL divisor to chip should be odd integer: PLL Divide Ratio = Input N + offset of 1)
Figure 2 below shows the regenerated Hsync from the AD9884A running in dual parallel mode, DataReady_A Pixel Clock (A) from the AD9884A and an Aport Data bit at the 80 pin output connector (pins 7, 9, 23 at connector). The AD9884A is set to sync on Hsync falling Data_Ready_ A rises on Hsync falling. Note that the output clock is well centered on the data pixel, satisfying typical required timing margins. This measurement was taken for an XGA 60Hz input waveform HS DataReady_A Aport DataBit Figure 2 Output Timing
Schematics and Layout The schematics and layout for this board are included in separate files. They can be found on the installation CD. Contact Information Questions? Please email us directly at flatpanel_apps@analog.com, visit our web site at http://www.analog.com/flatpanel, or call the Analog Devices help line at 1-800-AnalogD. ORDERING INFORMATION: Please contact your local Analog Devices sales office to order the AD9884A Evaluation Kit.
a (centimeters) SXGA Panel Driver Board Flat Panel Interface Rev 0 1/4/2000 Evaluation Board Documentation For the SXGA Panel Driver Board
Purpose The purpose of the SXGA Panel Driver Board is to aid in the evaluation of the AD9884A or AD9887. It is designed to be used in conjunction with either the AD9884A Evaluation Board or the AD9887 Evaluation Board, and is included as part of the evaluation board kits. It is a conduit for displaying digitized images on the LCD panel, specifically the 18 SXGA panel from Sharp, (model # LQ181E1DG12). Requirements All that is needed to use this board is either an AD9884A or AD9887 evaluation board (included), a 12V dc power supply (included), a Centronix printer cable for serial bus programming (included), a computer with a 60Hz SXGA graphics signal, and an LCD panel. Limitations This board is designed to help demonstrate the performance of the AD9884A and AD9887 interface chips only. It does not include scaling, frame rate conversion, or auto setup capabilities. Therefore, it is designed for only displaying 1280x1024, 60Hz images. Power This board is designed to received 12V dc through connector J4. The power supply that is included in the kit will plug into that connector. Board Functions Data buffering The function that this board does is to buffer the data, clock, and sync inputs. The purpose of this is to help minimize the capacitance and lead length that the interface chip has to drive. The buffering is done with chips U2, U3, U4, & U5. DE Generation The Sharp panel requires a Data Enable signal that indicates actual image data. Since analog interfaces do not generate this signal, the SXGA Panel Driver Board does. (Exact use of this circuit is described later.) DE is generated by the Altera chip U6 and the switches located next to it. Serial Bus to Computer Interfacing Some circuitry is needed in order to interface the AD9884A/AD9887 s serial register with a computer. That circuitry is included on this board, specifically U1, & U9. Panel Power All voltages that are required for panel operation are generated on this board. The 12 volts comes from the external supply and a voltage regulator regulates the 12V down to 5V which the panel also needs, (U7). Panel Protection Circuitry Applying power to a panel without the appropriate signals can damage a panel. Therefore, circuitry is included that disconnects power to the panel whenever the data clock and data enable (DE) signals are missing. (Even with this protection circuitry, we do not recommend leaving the board powered up for long without the appropriate signals being provided.) The circuit for this function is made up of U10, Q1, Q2, Q3, & Q4. Back Light Power The board also provides the necessary voltages for powering the panel s backlight. (Note: the backlight power does not need an ac signal to work properly. Therefore, it does not need the same type of protection circuitry, and remains connected when an input signal is missing.) The backlight power connector is J6. AD9884A/AD9887 Power This board provides regulated 5V power to the AD9884A/AD9887 evaluation boards though the J3 connector. Software No software is needed to drive this board. The necessary software for driving the AD9884A and AD9887 boards is included with the evaluation kit, which can be ordered from your local Analog Devices sales office. Configuring the Board There are only two things that need to be configured on this board, both of which are related to data enable (DE).
The first is to select the source of DE for the panel. The digital interface portion of the AD9887 provides its own DE signal, while the analog interfaces on the AD9884A and AD9887 do not. Therefore depending on which interface is used, you need to select the appropriate DE input for the panel. The DE from the AD9887 Evaluation Board (for the digital interface only) can be selected by connecting the center pin of W1 to the single pin of W13. (They are located next to each other.) The DE that is generated on this, the SXGA Panel Driver Board (needed for the analog interfaces) can be selected by connecting the center pin of W1 to the pin on the right side of W1. The second thing that can be configured is the shape of the DE signal. Since the number of pixel clocks from Hsync to the first pixel can vary from video card to video card, and since the number of lines from Vsync to the first video line can vary, we included a method for selecting the delay in pixel clocks from Hsync and the delay in video lines from Vsync before DE starts. To set the delay in pixels from Hsync, you can set the switches in S1. The delay can be set for any number between 1 and 255. The switches are weighted in binary with the left most one being the LSB and the right most one being the MSB. Also, the count starts from the trailing edge of Hsync, but the chip does not know the polarity of Hsync. The bottom switch on S2 selects the polarity of Hsync. To select positive polarity, flip the switch to the right. To set the delay in lines from Vsync, you can set the switches in S2. The delay can be set for any number between 1 and 127. The switches are weighted in binary with the next to bottom one being the LSB and the top one being the MSB. The next photo shows how this board interfaces with the AD9887 evaluation board. Connecting to the panel This board connects to the panel through the large white connector, J2. This connector is on the bottom of the board and is shown in this picture: Schematics and Layout The schematics and layout for this board are included in separate files. They can be found on the CD, which is contained in the AD9884A Evaluation Kit. Evaluation Board Connections Below is a photo of how this board interfaces with the AD9884A Evaluation Board.
Contact Information Questions? Please email us directly at flatpanel_apps@analog.com, visit our web site at http://www.analog.com/flatpanel, or call the Analog Devices help line at 1-800-AnalogD. Ordering Information: Please contact your local Analog Devices sales office to order the AD9884A Evaluation Kit.