Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report

2015.06.25 Altera JESD204B IP Core and ADI AD9250 Hardware Checkout Report AN-JESD204B-AV Subscribe The Altera JESD204B IP core is a high-speed point-to-point serial interface intellectual property (IP). The JESD204B IP core has been hardware-tested with a number of selected JESD204B-compliant ADC (analog-to-digital converter) device. This report highlights the interoperability of the JESD204B IP core with the AD9250 Analog-to-Digital Converter evaluation module (EVM) from Analog Devices Inc. (ADI). The hardware checkout methodology and test results are described in the following sections. Related Information JESD204B IP Core User Guide ADI AD9250 Analog-to-Digital Converter Hardware Requirements The hardware checkout test requires the following hardware and software tools: Arria V GT FPGA Development Kit with 19 V power adaptor Arria V SoC Development Kit ADI AD9250 EVM (AD9250-FMC-250EBZ) Mini-USB cable Related Information Arria V GT FPGA Development Kit User Guide Arria V GT FPGA Development Board Reference Manual Arria V SoC Development Kit User Guide Arria V SoC Development Board Reference Manual Hardware Setup Set up the development kit with the ADI AD9250 daughter card module installed to the board's FMC connector. Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Nios, Quartus and Stratix words and logos are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries. Intel warrants performance of its FPGA and semiconductor products to current specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. *Other names and brands may be claimed as the property of others. ISO 9001:2008 Registered www.altera.com 101 Innovation Drive, San Jose, CA 95134

2 AN-JESD204B-AV 2015.06.25 Hardware Setup Figure 1: Hardware Setup for Arria V GT Development Kit The AD9250 module derives power from the FMC connector on the development board. The AD9250 module supplies the device clock to FPGA 2. For subclass 1 mode, the FPGA generates SYSREF for the JESD204B MegaCore function as well as the AD9250 module. FPGA 1 FPGA 2 Status LED Transceiver Lanes Device Clock SYSREF rx_dev_sync_n Power Arria V GT FPGA Development Board ADI AD9250 Module

AN-JESD204B-AV 2015.06.25 Hardware Setup 3 Figure 2: Hardware Setup for Arria V SoC Development Kit The AD9250 module derives power from the FMC connector on the development board. The AD9250 module supplies clock to the FPGA and ADC. For subclass 1 mode, the FPGA generates SYSREF for the JESD204B IP core as well as the AD9250 module.

4 Hardware Checkout Methodology Figure 3: System Diagram AN-JESD204B-AV 2015.06.25 The system-level diagram shows how the different modules connect in this design. In this setup where LMF = 222, the data rate of the both transceiver lanes is 4.915 Gbps. The AD9517 clock generator provides 122.88 MHz clock to the FPGA and 245.76 MHz sampling clock to both AD9250 devices. Oscillator 100 MHz LED mgmt_clk jesd204b_ed_top.v Arria V FPGA #2/Arria V SoC ISSP SignalTap II Logic Analyzer Qsys System JTAG to Avalon Master Bridge Avalon-MM Slave Translator global_reset rx_seriallpbken Avalon-MM Interface Signals jesd204b_ed.v (Example Design) JESD204B IP (Duplex) L = 2, M = 2, F = 2 sclk, ss_n[0], miso, mosi device_clk (122.88 MHz) link_clk (122.88 MHz) Sysref sysref_out Generator rx_dev_sync_n rx_serial_data[0] (4.915 Gbps) rx_serial_data[1] (4.915 Gbps) FMC 4-Wire AD9250-FMC-250EBZ CPLD 3- or 4-Wire AD9517 Clock Generator Single-Ended to Differential Distribution L0 L1 3-Wire sync_n sysref ADC#2 clk (245.76 MHz) Slave AD9250 ADC#1 CLK and SYNC Slave AD9250 ADC#2 CLK and SYNC ADC ADC ADC ADC Related Information AN 696: Using the JESD204B IP Core in Arria V Devices More information on how to set up the board. Hardware Checkout Methodology The following section describes the test objectives, procedure, and the passing criteria. The test covers the following areas: Receiver data link layer Receiver transport layer Descrambling Deterministic latency (Subclass 1) Receiver Data Link Layer This test area covers the test cases for code group synchronization (CGS) and initial frame and lane synchronization. On link start up, the receiver issues a synchronization request and the transmitter transmits /K/ (K28.5) characters. The SignalTap II Logic Analyzer tool is used to monitor the operation of receiver data link layer.

AN-JESD204B-AV 2015.06.25 Code Group Synchronization (CGS) 5 Code Group Synchronization (CGS) Table 1: CGS Test Cases Test Case Objective Description Passing Criteria CGS.1 Check whether sync request is deasserted after correct reception of four successive /K/ characters. The following signals in <ip_variant_ name>_inst_phy.v are tapped: jesd204_rx_pcs_data[(l*32)- 1:0] jesd204_rx_pcs_data_valid[l- 1:0] jesd204_rx_pcs_kchar_ data[(l*4)-1:0] (1) The following signals in <ip_variant_ name>.v are tapped: rx_dev_sync_n jesd204_rx_int The rxframe_clk is used as the SignalTap II sampling clock. Each lane is represented by 32-bit data bus in jesd204_rx_pcs_data. The 32-bit data bus is divided into 4 octets. /K/ character (0xBC) is observed at each octet of the jesd204_rx_pcs_data bus. The jesd204_rx_pcs_data_ valid signal is asserted to indicate that data from the PCS is valid. The jesd204_rx_pcs_kchar_ data signal is asserted whenever control characters like /K/, /R/, /Q/, or /A/ are observed. The rx_dev_sync_n signal is deasserted after correct reception of at least four successive /K/ characters. The jesd204_rx_int signal is deasserted if there is no error. CGS.2 Check full CGS at the receiver after correct reception of another four 8B/10B characters. The following signals in <ip_variant_ name>_inst_phy.v are tapped: jesd204_rx_pcs_ errdetect[(l*4)-1:0] jesd204_rx_pcs_disperr[(l*4) -1:0] (1) The jesd204_rx_pcs_errdetect, jesd204_rx_pcs_disperr, and jesd204_rx_int signals should not be asserted during CGS phase. The following signal in <ip_variant_ name>.v is tapped: jesd204_rx_int The rxframe_clk is used as the SignalTap II sampling clock. (1) L is the number of lanes.

6 Initial Frame and Lane Synchronization Initial Frame and Lane Synchronization AN-JESD204B-AV 2015.06.25 Table 2: Initial Frame and Lane Synchronization Test Cases Test Case Objective Description Passing Criteria ILA.1 Check whether the initial frame synchronization state machine enters FS_DATA state upon receiving non /K/ characters. The following signals in <ip_variant_ name>_inst_phy.v are tapped: jesd204_rx_pcs_data[(l*32)- 1:0] jesd204_rx_pcs_data_valid[l- 1:0] jesd204_rx_pcs_kchar_ data[(l*4)-1:0] (2) The following signals in <ip_variant_ name>.v are tapped: rx_dev_sync_n jesd204_rx_int The rxframe_clk is used as the SignalTap II sampling clock. Each lane is represented by 32-bit data bus in jesd204_rx_pcs_data. The 32-bit data bus is divided into 4 octets. /R/ character or K28.0 (0x1C) is observed after /K/ character at the jesd204_rx_pcs_data bus. The jesd204_rx_pcs_data_ valid signal must be asserted to indicate that data from the PCS is valid. The rx_dev_sync_n and jesd204_rx_int signal are deasserted. Each multiframe in the ILAS phase ends with /A/ character or K28.3 (0x7C). The jesd204_rx_pcs_kchar_ data signal is asserted whenever control characters like /K/, /R/, /Q/, or /A/ are observed. ILA.2 Check the JESD204B configuration parameters from ADC in the second multiframe. The following signals in <ip_variant_ name>_inst_phy.v are tapped: jesd204_rx_pcs_data[(l*32)- 1:0] jesd204_rx_pcs_data_valid[l- 1:0] (2) The following signal in <ip_variant_ name>.v is tapped: jesd204_rx_int /R/ character is followed by /Q/ character or K28.4 (0x9C) at the beginning of the second multiframe. The jesd204_rx_int signal is deasserted if there is no error. Octets 0-13 read from these registers match with the JESD204B parameters in each test setup. The rxframe_clk is used as the SignalTap II sampling clock. The System Console accesses the following registers: ilas_octet0 ilas_octet1 ilas_octet2 ilas_octet3 (2) L is the number of lanes.

AN-JESD204B-AV 2015.06.25 Receiver Transport Layer 7 Test Case Objective Description Passing Criteria ILAS.3 Check the lane alignment The following signals in <ip_variant_ name>_inst_phy.v are tapped: jesd204_rx_pcs_data[(l*32)- 1:0] jesd204_rx_pcs_data_valid[l- 1:0] (2) The following signal in <ip_variant_ name>.v is tapped: rx_somf[3:0] dev_lane_aligned jesd204_rx_int The rxframe_clk is used as the SignalTap II sampling clock. The dev_lane_aligned signal is asserted after the end of the fourth multiframe in ILAS phase but before the first rx_ somf signal is asserted. The rx_somf signal marks the start of multiframe in user data phase. The jesd204_rx_int signal is deasserted if there is no error. Receiver Transport Layer To check the data integrity of the payload data stream through the RX JESD204B IP core and transport layer, the ADC is configured to output PRBS-9 test data pattern. The ADC is also set to operate with the same configuration as set in the JESD204B IP core. The PRBS checker in the FPGA fabric checks data integrity for one minute. Figure 4 shows the conceptual test setup for data integrity checking. Figure 4: Data Integrity Check Using PRBS Checker AD9250 PRBS Generator TX Transport Layer TX JESD204B IP Core PHY and Link Layer FPGA PRBS Checker RX Transport Layer RX JESD204B IP Core PHY and Link Layer The SignalTap II Logic Analyzer tool is used to monitor the operation of the RX transport layer.

8 Descrambling Table 3: Transport Layer Test Cases AN-JESD204B-AV 2015.06.25 Test Case Objective Description Passing Criteria TL.1 Check the transport layer mapping. The following signals in altera_ jesd204_transport_rx_top.v are tapped: jesd204_rx_data_valid jesd204_rx_link_data_valid jesd204_rx_link_error The following signals in jesd204b_ ed.v are tapped: data_error[m-1:0] jesd204_rx_int M is the number of converters. The rxframe_clk is used as the SignalTap II sampling clock. The data_error signal is the PRBS checker's pass or fail indicator. The jesd204_rx_data_valid and jesd204_rx_link_data_ valid signals is asserted. The jesd204_rx_link_error and jesd204_rx_int signals is deasserted. Descrambling The PRBS checker at the RX transport layer checks the data integrity of descrambler. The SignalTap II Logic Analyzer tool is used to monitor the operation of the RX transport layer. Table 4: Descrambler Test Cases Test Case Objective Description Passing Criteria SCR.1 Check the functionality of the descrambler. Enable scrambler at the ADC and descrambler at the RX JESD204B IP core. The signals that are tapped in this test case are similar to test case TL.1 The jesd204_rx_data_valid and jesd204_rx_link_data_ valid signals is asserted. The jesd204_rx_link_error and jesd204_rx_int signals is deasserted. Deterministic Latency (Subclass 1) Figure 5 shows the block diagram of deterministic latency test setup. A SYSREF generator provides a periodic SYSREF pulse for both the AD9250 and JESD204B IP core. The SYSREF generator is running in link clock domain and the period of SYSREF pulse is configured to the desired multiframe size. The SYSREF pulse restarts the LMF counter and realigns it to the LMFC boundary.

AN-JESD204B-AV 2015.06.25 Deterministic Latency (Subclass 1) 9 Figure 5: Deterministic Latency Test Setup Block Diagram Oscillator 100 MHz USER2_PB0 (S11) mgmt_clk global_rst_n USER2_DIPSW[0] (SW3) jesd204b_ed_top.v Arria V FPGA #2/Arria V SoC SignalTap II Logic Analyzer Deterministic Latency Measurement jesd204b_ed.v (Example Design) JESD204B IP (Duplex) L = 2, M = 2, F = 2 sclk, ss_n[0], miso, mosi device_clk (122.88 MHz) link_clk (122.88 MHz) Sysref Generator rx_dev_sync_n rx_serial_data[0] (4.915 Gbps) rx_serial_data[1] (4.915 Gbps) FMC 4-Wire sysref_out AD9250-FMC-250EBZ CPLD 3- or 4-Wire AD9517 Clock Generator Single-Ended to Differential Distribution L0 L1 3-Wire sync_n sysref ADC#2 clk (245.76 MHz) Slave AD9250 ADC#1 CLK and SYNC Slave AD9250 ADC#2 CLK and SYNC ADC ADC ADC ADC The deterministic latency measurement block checks the deterministic latency by measuring the number of link clock counts between the start of deassertion of SYNC~ to the first user data output. Figure 6: Deterministic Latency Measurement Timing Diagram Link Clock State ILAS USER_DATA SYNC~ RX Valid sync_to_rxvalid_cnt 1 2 3 n - 1 n With the setup above, four test cases were defined to prove deterministic latency. By default, the JESD204B IP core performs a single SYSREF detection. The SYSREF N-shot mode is enabled on the AD9250 for this deterministic measurement. Table 5: Deterministic Latency Test Cases Test Case Objective Description Passing Criteria Check the LMFC alignment. Check that the FPGA and ADC are aligned to the desired LMF periods. SYSREF detection is always enabled. Observe the sysref_lmfc_err signal from the Signal Tap II Logic Analyzer. The sysref_lmfc_err signal should not be triggered.

10 JESD204B IP Core and AD9250 Configurations AN-JESD204B-AV 2015.06.25 Test Case Objective Description Passing Criteria Check the SYSREF capture. Check that the FPGA and ADC capture SYSREF correctly and restart the LMF counter. Both the FPGA and ADC are also repetitively reset. Observe the csr_rbd_count signal from the Signal Tap II Logic Analyzer. If the SYSREF is captured correctly and the LMF counter restarts, the csr_rbd_count value should only drift a little for every reset due to word alignment. Check the latency from start of deassertion of SYNC~ to the first user data output. Check that the latency is fixed for every FPGA reset. Repetitively reset the FPGA upon assertion of RX valid. Record the number of link clocks count from start of deassertion of SYNC~ to the first user data output. Consistent latency from the start of deassertion of SYNC~ to the first user data output latency. Continuously compare the current test (n) that records the number of link clocks from deassertion of SYNC~ to the first user data output with the previous test (n-1) record. JESD204B IP Core and AD9250 Configurations The JESD204B IP core parameters (L, M and F) in this hardware checkout are natively supported by the AD9250 module's quick configuration register at address 0x5E. The transceiver data rate, sampling clock frequency, and other JESD204B parameters complies with the AD9250 operating conditions. The hardware checkout testing implements the JESD204B IP core with the following parameter configuration. Table 6: Parameter Configuration JESD204B Parameters Configuration Setting LMF 112 124 222 211 HD 0 0 0 1 S 1 1 1 1 N 14 14 14 14 N' 16 16 16 16 CS 0 0 0 0 CF 0 0 0 0

AN-JESD204B-AV 2015.06.25 Test Results 11 FPGA Clock Configuration /K/ Character Replacement Data Pattern Device Clock (MHz) (3) 122.88 Management Clock (MHz) 100 Setting Frame Clock/Sampling Clock 245.76 122.88 245.76 245.76 (MHz) (4) Link Clock (MHz) (4) 122.88 61.44 Enabled PRBS-9 Ramp (5) Test Results The following table contains the possible results and their definition. Table 7: Results Definition Result with comments FAIL Warning Refer to comments Definition The Device Under Test (DUT) was observed to exhibit conformant behavior. The DUT was observed to exhibit conformant behavior. However, an additional explanation of the situation is included, such as due to time limitations, only a portion of the testing was performed. The DUT was observed to exhibit non-conformant behavior. The DUT was observed to exhibit behavior that is not recommended. From the observations, a valid pass or fail could not be determined. An additional explanation of the situation is included. The following table shows the results for test cases CGS.1, CGS.2, ILA.1, ILA.2, ILA.3, TL.1, and SCR.1 with different values of L, M, F, K, subclass, data rate, sampling clock, link clock and SYSREF frequencies. Table 8: Test Results Test L M F Subclass SCR K Data rate (Mbps) Sampling Clock (MHz) Link Clock (MHz) SYSREF (MHz) 1 1 1 2 0 0 16 4915 245.76 122.88 2 1 1 2 0 0 32 4915 245.76 122.88 3 1 1 2 0 1 16 4915 245.76 122.88 Result (3) The device clock is used to clock the transceiver. (4) The frame clock and link clock is derived from the device clock using an internal PLL. (5) The ramp pattern is used in deterministic latency measurement test cases,, and only.

12 Test Results AN-JESD204B-AV 2015.06.25 Test L M F Subclass SCR K Data rate (Mbps) Sampling Clock (MHz) Link Clock (MHz) SYSREF (MHz) 4 1 1 2 0 1 32 4915 245.76 122.88 5 1 1 2 1 0 16 4915 245.76 122.88 15.36 6 1 1 2 1 0 32 4915 245.76 122.88 7.68 7 (6) 1 1 2 1 1 16 4915 245.76 122.88 15.36 8 (6) 1 1 2 1 1 32 4915 245.76 122.88 7.68 9 1 2 4 0 0 16 4915 122.88 122.88 10 1 2 4 0 0 32 4915 122.88 122.88 11 1 2 4 0 1 16 4915 122.88 122.88 12 1 2 4 0 1 32 4915 122.88 122.88 13 1 2 4 1 0 16 4915 122.88 122.88 7.68 14 1 2 4 1 0 32 4915 122.88 122.88 3.84 15 (6) 1 2 4 1 1 16 4915 122.88 122.88 7.68 16 (6) 1 2 4 1 1 32 4915 122.88 122.88 3.84 17 2 1 1 0 0 20 2457 245.76 61.44 18 2 1 1 0 0 32 2457 245.76 61.44 19 2 1 1 0 1 20 2457 245.76 61.44 20 2 1 1 0 1 32 2457 245.76 61.44 21 2 1 1 1 0 20 2457 245.76 61.44 12.288 22 2 1 1 1 0 32 2457 245.76 61.44 7.68 23 (6) 2 1 1 1 1 20 2457 245.76 61.44 12.288 24 (6) 2 1 1 1 1 32 2457 245.76 61.44 7.68 25 2 2 2 0 0 16 4915 245.76 122.88 26 2 2 2 0 0 32 4915 245.76 122.88 27 2 2 2 0 1 16 4915 245.76 122.88 28 2 2 2 0 1 32 4915 245.76 122.88 29 2 2 2 1 0 16 4915 245.76 122.88 15.36 30 2 2 2 1 0 32 4915 245.76 122.88 7.68 31 (6) 2 2 2 1 1 16 4915 245.76 122.88 15.36 32 (6) 2 2 2 1 1 32 4915 245.76 122.88 7.68 Result (6) Results for both Arria V GT and Arria V SoC devices.

AN-JESD204B-AV 2015.06.25 Test Results 13 Table 9: Deterministic Latency Measurement for Arria V GT Test L M F Subclass K Data rate (Mbps) Sampling Clock (MHz) Link Clock (MHz) SYSREF (MHz) 2 2 2 1 32 4915 245.76 122.88 7.68 2 2 2 1 32 4915 245.76 122.88 7.68 2 2 2 1 32 4915 245.76 122.88 7.68 with Result observed: 131-132 Table 10: Deterministic Latency Measurement for Arria V SoC Test L M F Subclass SCR K Data Rate (Msps) Link Clock (MHz) 1 1 2 1 1 16 4915 122.88 Result with observed: 83 1 1 2 1 1 32 4915 122.88 1 2 4 1 1 16 4915 122.88 with observed: 131 with observed: 131

14 Test Results Test L M F Subclass SCR K Data Rate (Msps) Link Clock (MHz) 1 2 4 1 1 32 4915 122.88 AN-JESD204B-AV 2015.06.25 Result with observed: 227 2 1 1 1 1 20 2457 61.44 2 1 1 1 1 32 2457 61.44 2 2 2 1 1 16 4915 122.88 2 2 2 1 1 32 4915 122.88 with observed: 63 with observed: 83 with observed: 83 with observed: 131 The following figure shows the SignalTap II waveform of the clock count from the deassertion of SYNC~ in the first output of the ramp test pattern. The clock count measures the first user data output latency.

AN-JESD204B-AV 2015.06.25 Test Result Comments 15 Figure 7: Deterministic Latency Measurement Ramp Test Pattern 001h 002h 1Fh 00h 03h 000h 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 131 test_fail test_cnt sysref test_k rx_sync_n rx_valid csr_rbd_count csr_rbd_offset sync_to_nvalid_cnt sync_to_rxvalid_cnt_pre 0000000h 001h 1Fh 00h 000h 0 131 002h 03h 131 jesd204_rx_dataout[13:0] jesd204_rx_dataout[27:14] Test Result Comments In each test case, the RX JESD204B IP core successfully initialize from CGS phase, ILA phase, and until user data phase. No data integrity issue is observed by the PRSB checker. For test case with LMF = 211, the data rate is reduced to 2457 Mbps to limit the ADC sample clock to less than 250 MHz. The following table describes the scenarios where there is a difference in the data rate. Table 11: Sample Rate Implication for Test Case with LMF = 211 Item Scenario 1 Scenario 2 Remark Data rate 4915 Mbps 2457 Mbps Data rate is within the operating condition of AD9250.

16 Document Revision History AN-JESD204B-AV 2015.06.25 Item Scenario 1 Scenario 2 Remark = data rate/40 122.88 MHz 61.44 MHz frequency is determined by the data rate. ADC sample clock must be ADC maximum sampling rate 491.52 MHz 245.76 MHz Sample clock frequency in scenario 1 is beyond the operating condition of AD9250. The link clock count variation in the deterministic latency measurement is caused by the word alignment, where control characters fall into the next cycle of data some time after realignment. This makes the duration of the ILAS phase longer by one link clock some time after reset. Document Revision History Date Version Changes June 2015 2015.06.25 Added new information on hardware setup, parameter configurations, and test results for Arria V SoC device. December 2013 2013.12.02 Initial release.