Placement Rent Exponent Calculation Methods, Temporal Behaviour, and FPGA Architecture Evaluation. Joachim Pistorius and Mike Hutton

Similar documents
EN2911X: Reconfigurable Computing Topic 01: Programmable Logic. Prof. Sherief Reda School of Engineering, Brown University Fall 2014

Peak Dynamic Power Estimation of FPGA-mapped Digital Designs

ESE (ESE534): Computer Organization. Last Time. Today. Last Time. Align Data / Balance Paths. Retiming in the Large

Automatic Transistor-Level Design and Layout Placement of FPGA Logic and Routing from an Architectural Specification

Investigation of Look-Up Table Based FPGAs Using Various IDCT Architectures

288 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 12, NO. 3, MARCH 2004

The Stratix II Logic and Routing Architecture

Exploring Architecture Parameters for Dual-Output LUT based FPGAs

Skip Length and Inter-Starvation Distance as a Combined Metric to Assess the Quality of Transmitted Video

COMPUTER ENGINEERING PROGRAM

On the Sensitivity of FPGA Architectural Conclusions to Experimental Assumptions, Tools, and Techniques

Cascadable 4-Bit Comparator

ESE534: Computer Organization. Today. Image Processing. Retiming Demand. Preclass 2. Preclass 2. Retiming Demand. Day 21: April 14, 2014 Retiming

Achieving Timing Closure in ALTERA FPGAs

Latch-Based Performance Optimization for FPGAs. Xiao Teng

Future of Analog Design and Upcoming Challenges in Nanometer CMOS

March 13, :36 vra80334_appe Sheet number 1 Page number 893 black. appendix. Commercial Devices

Boolean, 1s and 0s stuff: synthesis, verification, representation This is what happens in the front end of the ASIC design process

More About Regression

Innovative Fast Timing Design

Power-Driven Flip-Flop p Merging and Relocation. Shao-Huan Wang Yu-Yi Liang Tien-Yu Kuo Wai-Kei Tsing Hua University

Characterization and improvement of unpatterned wafer defect review on SEMs

CS184a: Computer Architecture (Structures and Organization) Last Time

Cyclone II EPC35. M4K = memory IOE = Input Output Elements PLL = Phase Locked Loop

EEC 116 Fall 2011 Lab #5: Pipelined 32b Adder

homework solutions for: Homework #4: Signal-to-Noise Ratio Estimation submitted to: Dr. Joseph Picone ECE 8993 Fundamentals of Speech Recognition

Designing for High Speed-Performance in CPLDs and FPGAs

The Effect of Wire Length Minimization on Yield

Adding Analog and Mixed Signal Concerns to a Digital VLSI Course

L14: Quiz Information and Final Project Kickoff. L14: Spring 2004 Introductory Digital Systems Laboratory

Clock-Aware FPGA Placement Contest

Field Programmable Gate Arrays (FPGAs)

EL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP. Due İLKER KALYONCU, 10043

INF4420 Project Spring Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC)

Optimizing area of local routing network by reconfiguring look up tables (LUTs)

Practical De-embedding for Gigabit fixture. Ben Chia Senior Signal Integrity Consultant 5/17/2011

A High-Resolution Flash Time-to-Digital Converter Taking Into Account Process Variability. Nikolaos Minas David Kinniment Keith Heron Gordon Russell

VGA Controller. Leif Andersen, Daniel Blakemore, Jon Parker University of Utah December 19, VGA Controller Components

AP Statistics Sampling. Sampling Exercise (adapted from a document from the NCSSM Leadership Institute, July 2000).

FPGA Design. Part I - Hardware Components. Thomas Lenzi

Sharif University of Technology. SoC: Introduction

FPGA Development for Radar, Radio-Astronomy and Communications

LabView Exercises: Part II

A Module Area Estimator for VLSI Layout*

Why FPGAs? FPGA Overview. Why FPGAs?

SCSI Cable Characterization Methodology and Systems from GigaTest Labs

Pattern Smoothing for Compressed Video Transmission

Scan. This is a sample of the first 15 pages of the Scan chapter.

LOW POWER DIGITAL EQUALIZATION FOR HIGH SPEED SERDES. Masum Hossain University of Alberta

Fine-grain Leakage Optimization in SRAM based FPGAs

High Performance Carry Chains for FPGAs

Reconfigurable Architectures. Greg Stitt ECE Department University of Florida

Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow

Towards Trusted Devices in FPGA by Modeling Radiation Induced Errors

Slack Redistribution for Graceful Degradation Under Voltage Overscaling

Integrated circuits/5 ASIC circuits

ECE 555 DESIGN PROJECT Introduction and Phase 1

TSIU03, SYSTEM DESIGN. How to Describe a HW Circuit

INTEGRATED CIRCUITS. AN219 A metastability primer Nov 15

Glitch Reduction and CAD Algorithm Noise in FPGAs. Warren Shum

Analog Integrated Circuit Design Automation

Analysis of local and global timing and pitch change in ordinary

Testing Digital Systems II

LFSR Test Pattern Crosstalk in Nanometer Technologies. Laboratory for Information Technology University of Hannover, Germany

UNIT IV CMOS TESTING. EC2354_Unit IV 1

Lossless Compression Algorithms for Direct- Write Lithography Systems

Predicting the immediate future with Recurrent Neural Networks: Pre-training and Applications

New Techniques for Designing and Analyzing Multi-GigaHertz Serial Links

PICK THE RIGHT TEAM AND MAKE A BLOCKBUSTER A SOCIAL ANALYSIS THROUGH MOVIE HISTORY

Random Access Scan. Veeraraghavan Ramamurthy Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL

DOCTORAL DISSERTATIONS OF MAHATMA GANDHI UNIVERSITY A STUDY OF THE REFERENCES CITED

Sampling Worksheet: Rolling Down the River

COPY RIGHT. To Secure Your Paper As Per UGC Guidelines We Are Providing A Electronic Bar Code

Level and edge-sensitive behaviour

Implementation of an MPEG Codec on the Tilera TM 64 Processor

EECS150 - Digital Design Lecture 18 - Circuit Timing (2) In General...

Asynchronous Scan-Latch controller for Low Area Overhead DFT

Improving FPGA Performance with a S44 LUT Structure

Performance Driven Reliable Link Design for Network on Chips

Noise Margin in Low Power SRAM Cells

Day 21: Retiming Requirements. ESE534: Computer Organization. Relative Sizes. Today. State. State Size

OPTIMALITY AND STABILITY STUDY OF TIMING-DRIVEN PLACEMENT ALGORITHMS. Jason Cong, Michail Romesis, Min Xie

PLACEMENT is an important step in the overall IC design

International Journal of Engineering Research-Online A Peer Reviewed International Journal

An Improved Recursive and Non-recursive Comb Filter for DSP Applications

Static Timing Analysis for Nanometer Designs

INTERMEDIATE FABRICS: LOW-OVERHEAD COARSE-GRAINED VIRTUAL RECONFIGURABLE FABRICS TO ENABLE FAST PLACE AND ROUTE

AUDIOVISUAL COMMUNICATION

EE178 Spring 2018 Lecture Module 5. Eric Crabill

DAT335 Music Perception and Cognition Cogswell Polytechnical College Spring Week 6 Class Notes

Retiming Sequential Circuits for Low Power

Lecture #4: Clocking in Synchronous Circuits

CS/EE 6710 Digital VLSI Design CAD Assignment #3 Due Thursday September 21 st, 5:00pm

Abstract. Keywords INTRODUCTION. Electron beam has been increasingly used for defect inspection in IC chip

EECS 427 Discussion 1

BER MEASUREMENT IN THE NOISY CHANNEL

On Figure of Merit in PAM4 Optical Transmitter Evaluation, Particularly TDECQ

Prototyping an ASIC with FPGAs. By Rafey Mahmud, FAE at Synplicity.

On the Characterization of Distributed Virtual Environment Systems

LFSRs as Functional Blocks in Wireless Applications Author: Stephen Lim and Andy Miller

Transcription:

Placement Rent Exponent Calculation Methods, Temporal Behaviour, and FPGA Architecture Evaluation Joachim Pistorius and Mike Hutton

Some Questions How best to calculate placement Rent? Are there biases in calculation methods? How does Rent exponent change with timing-driven placement? Do circuit types have a common Rent characteristic? How does Rent exponent change with placement quality? MH 2/28

Goals of this paper Purely empirical study. Many benchmarks, different sizes. Commercial FPGA architecture. Looking for interesting trends in the data. Try to address the preceding questions. Look at FPGA architecture wiring requirements and Rent s Rule. MH 3/28

Applying Rent s Rule: P = kb r One circuit: Estimate wirelength, pre-placement. Extract r, follow models for wirelength. Many circuits: Estimate wirelength required for an FPGA architecture. Extract a typical r. Did we provide enough interconnect at each level of hierarchy? MH 4/28

FPGA Architecture How many? LAB Cyclone C6 M4K H channel H PLL PLL PLL IO V V channel LAB LE LAB lines LOCAL How many? How many? MH 5/28

Motivation: Apex Rent Exponents P = 0.6522B + 1.8435 APEX 20K400 log P P = 0.5854B + 1.694 R 2 = 0.6215 log B 1 0.8 0.6 0.4 0.2 Unconstrained r 0 circuits MH 6/28

Questioning the methodology: Contribution to Rent exponent number of samples 50000 45000 40000 35000 30000 25000 20000 15000 10000 5000 0 box %tot %>10 10 72% 0% 20 3% 9% 40 1% 3% 80 0% 1% 160 7% 24% 320 6% 23% 640 5% 18% 1280 4% 15% 2560 1% 5% 5120 1% 2% 10240 0% 1% 10 20 40 80 160 320 640 1280 2560 5120 10240 box size MH 7/28

Calculating Rent Parameters Partitioning Rent: Matches the APEX CAD flow and architecture Placement Rent More relevant to a placed circuit. Feuer: for a good placement, a sample of the placement should behave as Rent. But what is a sample? Hypothesize that the definition of the sample will affect both the results and spirit of the analysis. MH 8/28

I. Partition-based MH 9/28

II. Random x-y region MH 10/28

III. Random x-y + lengths x MH 11/28

IV. Random x-y + radius x MH 12/28

Region Size Is it fair that smaller samples contribute much more heavily to the Rent parameter? MH 13/28

Sampling Frequency Is it fair that some cells of the placement contribute much more heavily to the Rent parameter? MH 14/28

Rent exponents differ with method 0.8 RND_xy_rad vs. PART RND_xy_rad 0.7 0.6 0.5 0.4 0.4 0.5 0.6 0.7 0.8 PART MH 15/28

Significantly MH 16/28

Preconceived biases Placement cost function is: Minimum wire usage Best worst-case path delay Placer is simulated annealing based A priori belief that RND_xy_rad should be a more accurate reflection of the placement quality / architecture stress. MH 17/28

Conclusions on sampling methods The straightforward way of measuring does not seem fair. Other methods seem more natural. If you believe in applying Rent to a non-partitioning situation. Significant variation in measured r based on the method used. Question: what does this mean? Unfortunately, no answer for this. MH 18/28

Design Characterization. Parameter r varies with the structure and type of circuit? MH 19/28

Timing-driven placement Pushes out both Rent (r), wirelength (w). If you measure r,w with a partitioner, but apply it to a timing-driven placer, results will differ. MH 20/28

Complicating observation. Both r and w move, but not necessarily together. MH 21/28

Temporal correlation For a given circuit, decrease in r over the course of placement correlates strongly with placement quality / wirelength! MH 22/28

Conclusions on time and wirelength. I don t see a correlation between circuit type and r. It looks to be more complicated. TDC affects both r and w. But not in lock-step. *If* you start with normalized r and w, the two are surprisingly correlated as the placement quality improves. Does this apply outside of the simulated annealing world? MH 23/28

Predicting wirelength Simple goal: how well does a naïve model work for FPGAs? Answer: random scatter, until we adjust the model for the architecture, then reasonable MH 24/28

Rent and Cyclone Rent used only as a guiding principle in designing Cyclone almost entirely empirical. Rent exponent of the device is.72, while the average in the design set is.55. MH 25/28

Easy and hard designs The Rent exponent of the architecture is safely above the most stressed design. Almost exactly r + 2 Note worst-case vs. average case. We do not consider Cyclone to be over-routed. MH 26/28

Segmented Rent Plot Rent parameter of cyclone is NOT 0.72. LABs have input 26, output 10, size 10. 80 global tracks in H and V direction. 80 26 2*26 2*10 10 10 20 80 10x10 20x20 Wires increase with perimeter MH 27/28

Conclusions Empirical study. Importance of Rent methodology Biases and effect on r,w. Measurement and correlation to FPGA architectures. Naïve adjustment of Feuer works OK Interesting Rent properties on Cyclone. Rent exponent and placement quality/time. Stronger than expected correlation. MH 28/28