Power and Area analysis of Flip Flop using different s Neha Thapa 1, Dr. Rajesh Mehra 2 1 ME student, Department of E.C.E, NITTTR, Chandigarh, India 2 Associate Professor, Department of E.C.E, NITTTR, Chandigarh, India Abstract - The use of very large scale Integration (VLSI) technology in high performance computing, wireless communication and consumer electronics has been rising at a very fast rate. The challenge of advanced VLSI technology is growing in leakage power consumption. In these days standby leakage power dissipation is emerging as the major design consideration. Leakage control is very important, especially for low power applications and handheld devices such as cellular phones and PDA. This paper enumerates a low power and area of proposed pass transistor based flip flop using self adjustable voltage level circuit by comparison with different CMOS s. This work analysis the power and area of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. All the circuits are simulated with and without application of leakage reduction s. The circuits are simulated with CMOS in MICROWIND and DSCH using 180nm technology. Keywords : CMOS, Leakage Power, Pass Transistors, Process Technology, Stacking Effect, Transmission Gates 1. Introduction With development in technology and increasing demand of battery operated mobile platforms like laptop, palmtop computers, cellular phones, wireless modems and portable multimedia applications, etc. has directed the VLSI designers to be more power aware [1]. Most of the current designs are synchronous, which implies that flip-flops and latches are concerned in one way or another in the data and control paths. One of the challenges of low power methodologies for synchronous systems is the power utilization of these flip-flops and latches. It is significant to save power in these flip-flops and latches without compromising state reliability or performance. Several researchers have worked on low power flip-flop design, but they are mostly focused on one or a few types of flip-flops or applications. The requirement for comparing different designs and approaches is the main motivation for this paper. The main tradeoffs of any flip-flop are very important for a Power consumption of the clock system increases considerably and clock uncertainties take a significant part of the clock cycle at high frequencies. Moreover the non-ideal clock distribution fallout in degradation of the clock waveform, power supply noise and crosstalk. About 30%-70% of the total power of the system is dissipated due to clocking network, and the Flip-Flop. The latest advancement in computing technology has set a goal of high performance with low power consumption for VLSI designer [2]. Flip-flops are important timing elements in digital circuits which have a great impact on circuit power consumption and speed. The performance of the Flip-Flop is an important element to conclude the performance of the whole synchronous circuit, particularly in deeper pipelined design. Technology scaling of a transistor feature size has provided a remarkable innovation in silicon industry for the past few decades. Designers are striving for small silicon area, higher speed, low power consumption and reliability due to ever increasing demand and popularity of portable electronics. With the increasing use of mobile devices, consumer electronics markets demand a stringent constraint on reducing the power dissipation. In order to reduce the complexity of circuit design, a large proportion of For improving the performance one innovating is to increase the clock frequency [3]. The design for low power issues can t be overcome without defining the power prediction and optimization tools. Therefore, there is a critical need for certain tools to calculate power dissipation during the design to meet the power constraints to ignore the costly redesign effort However, using high clock frequency has many disadvantages. Power consumption of the clock system increases dramatically and clock uncertainties take a significant part of the clock cycle at high frequencies. Moreover the nonideal clock distribution results in degradation of the clock waveform, power supply noise and crosstalk. About 30%-70% of the total power of the system is dissipated due to clocking network, and the Flip-Flops [3]. An another clocking approach is based on the use of storage elements which are capable of capturing data on ISSN: 2231-2803 http://www.ijcttjournal.org Page 57
both rising and falling edges of the clock. Such storage elements are termed as Dual-Edge Triggered Flip-Flops (DETFFs). In this scenario, same data throughput can be achieved at half of the clock frequency as compared to the single edge triggered Flip-Flops [4]. In other words,we can say that double edge clocking can be used to save half of the power in the clock distribution network.storage elements which are capable of capturing data on both rising and falling edges of the clock. Such storage elements are termed as Dual-Edge Triggered Flip-Flops (DETFFs). In this scenario, same data throughput can be achieved at half of the clock frequency as compared to the single edge triggered Flip-Flops [5]. In other words, we can say that double edge clocking can be used to save half of the power in the clock distribution networkthe designer s main purpose in the field of digital circuit design is minimization of power consumption. A large part of research has been performed to expand and advance conventional Complementary Metal Oxide Semiconductor s for the fabrication of ULTRA low power integrated circuits. These advancements are responsible for special design s for digital circuits distant from conventional CMOS design style. Gate Diffusion Input design was introduced as a promising alternative to complementary CMOS Logic design. The GDI cell contains three inputs: G (common gate input of NMOS and PMOS), P (input to the source/drain of PMOS), and N (input to the source/drain of NMOS). The GDI cell structure is different from the existing PTL s [7]. Voltage scaling is associated with threshold voltage scaling which can cause the leakage power to increase exponentially. By using double-edge triggered flip-flops (DETFFs), the clock frequency can be significantly reduced ideally, cut in half while preserving the rate of data processing. It must be remarked that not all of the functions are possible in standard p-well CMOS process, but can be successfully implemented in twin-well CMOS or silicon on insulator (SOI) technologies. Dynamic power is proportional to the square of the supply voltage, contributes highest power consumption among the three. Therefore, reducing the supply voltage is the most valuable way to reduce power consumption of the design. Reduction in clock frequency is another alternative to reduce the dynamic power.the double edge clocking approach is adapted in this paper to reduce the clock frequency. Fig.1 Basic GDI cell Stack forced is based on the fact that natural stacking of MOSFET helps in achieving leakage current. The leakage through two series OFF transistor is much lower than that of single transistor because of stack effect. Power consumption of CMOS consists of dynamic and static components. Dynamic power is consumed when transistors are switching, and static power is consumed apart from of transistor switching. An effective way to reduce leakage power in active mode is stacked of the transistor. The proposed works concurrently with voltage and frequency scaling and power reduction is achieved by power gating within the clock cycle during which is applied during idle mode [8]. wider use of sequential logic and memory storage systems in modern electronics outcome in the implementation of low power and high speed design of basic memory elements. One of the most important basic memory elements is the D flip-flop (DFF). Three different designs of D flip-flops in CMOS logic are presented in this section 2. CMOS Implementation of D Flip Flop The wide exploit of sequential logic and memory storage systems in modern electronics results in the realization of low power and high speed design of basic memory elements. One of the most important basic memory elements is the D flip-flop (DFF). Three different ISSN: 2231-2803 http://www.ijcttjournal.org Page 58
designs of D flip-flops in CMOS logic are presented in this section. The D flip-flop combines a pair of master and slave D latch. Design I use pass transistors and inverters for the master-slave latches [10]. The flip-flop changes its state during the falling edge of the clock. Fig 2 shows the design II that uses transmission gates and inverters. The D flipflop combines a pair of master and slave D latch. Design I use pass transistors and inverters for the master-slave latches. The two chained inverters are in memory state when the PMOS loop transistor is on, that is when clock equals to 0. Other two chain inverters on the right hand side acts in the opposite way. complementary values of the internal signals and the circuit outputs. Fig.3 D FF using GDI Fig.2 D FF with pass transistor circuit Fig.3 shows design III with master-slave connection of two GDI D-latches. In this the body gates are responsible for the state of the circuit. These gates are controlled by the clock signal and create two alternative paths. One for transparent state of the latch, when the clock is low and the signals are propagating through PMOS transistors.the other one is in the holding state of the latch, when the clock signal is high and internal values are maintained due to conduction of the NMOS transistors. The inverters are responsible for maintaining the 3.D Flip Flop Reduction Techniques In this section two leakage reduction s, namely transistor stacking and selfadjustable voltage level circuit that is applied to the above circuits are described. The leakage current flowing through a stack of series connected transistors reduces when more than one transistor of the stack is turned OFF. This effect is known as the Stacking Effect. When two or more transistors that are switched OFF are stacked on top of each other then they dissipate less leakage power than a single transistor that is turned OFF. This is because each transistor in the stack induces a slight reverse bias between the gate and the source of the transistor, right below it, and this increases the threshold voltage of the bottom transistor making it more resistant to leakage[12]. ISSN: 2231-2803 http://www.ijcttjournal.org Page 59
Fig.4 D FF with stack forced Fig.6. shows the general self-adjustable voltage Level circuit, where Vdd is the supply voltage and VL is the output voltage of this circuit, which is applied to any load circuit. (In this paper D flip-flop is the load circuit). During the active mode (when SL=0), this circuit supplies maximum supply voltage to the load circuit through the ON PMOS transistor (P1) so that the load circuit can operate quickly. During the standby mode (SL=1), it provides slightly lower supply voltage to the load circuit through the weakly ON NMOS transistors So the voltage applied to the load circuit is given by: V L = V dd V n Where Vn is the voltage drop of m weakly ON NMOS transistors. The drain to source voltage Vdsn of the OFF NMOS in the standby mode is expressed as: V dsn = V L - Vss = V L Vdsn can be decreased by increasing Vn that is increasing m, the number of NMOS transistors. When Vdsn is decreased, the drain- induced barrier-lowering (DIBL) effect is decreased this in turn increases the threshold voltage Vtn of NMOS transistors. Consequently the sub threshold leakage current of the OFF MOSFETs decreases, so leakage power is minimized, while data are retained. Fig.7 shows the proposed leakage power reduced D flip-flop design using self adjustable voltage level circuit. Fig. 5 D FF with self adjustable voltage level circuit 3. Layout Design Analysis Various layout design implementation using different s has been shown below: Fig. 6 Layout design of D FF with pass transistor circuit Fig.7 Layout design of D FF using GDI ISSN: 2231-2803 http://www.ijcttjournal.org Page 60
Fig.8 Layout design of D FF with stack forced Fig.11 I/O waveform using Self adjustable voltage level circuit Comparison table of different s shown below: Various Techniques used GDI Pass transistor circuit Stack force Self adjustable circuit Power (µw) Area (µm 2 ) 0.0135 0.0293 0.0259 0.0254 305.1 229.1 202.9 198.4 Fig. 9 Layout design of D FF with self adjustable voltage level circuit In these works different designs of D flip-flops have been implemented in 180 nm CMOS process technology. The simulations are done in MICROWIND by using 180 nm technology. The Fig. 8 and Fig. 9 show the input-output waveforms of D flip-flop with stack force and Self adjustable voltage level s. 5. Conclusion In this paper three CMOS implementation of DFFs using pass transistors, transmission gates and GDI gates are proposed. The average power and area of the designs are presented. The leakage power of all the designs decreases when reduction s are applied. The percentage reduction of leakage power is more with the proposed SAL. Therefore, for low leakage power applications SAL design can be used in 180 nm technology. In low power applications area and power consumption of the device are the main technological aspects to prefer a design over the other contending designs. In this paper various literatures have studied and based on all the above comparisons among different s will be done to find which one is better. 7. References [1] Surya Naik and Rajeevan Chandel, Design of a Low Power Flip-Flop Using CMOS Deep Submicron Technology, IEEE International Conference on Recent Trends in Information, Telecommunication and Computing (ITC),pp. 253-256, 2010. Fig.10 I/O waveform using stack force [2] Z. Peiyi, M. Jason, K. Weidong, W. Nan, and W. Zhongfeng, Design of Sequential Elements for Low Power Clocking System. IEEE Transaction on Very large Scale Integration, pp. 914-918, July 2010. ISSN: 2231-2803 http://www.ijcttjournal.org Page 61
[3] M. Janaki Rani and S. Malarkann, Leakage Power reduction and analysis of CMOS sequential circuits, International Journal of VLSI design & Communication Systems Volume3, pp.13-23, February 2012. [4] Bhuvana S, Sangeetha R, A Survey on Sequential Elements for Low Power Clocking System, Journal of Computer Applications, ISSN: 0974 1925, Volume 5, 10 February 2012. Jalandhar, India. Mr. Mehra has more than 16 years of academic experience. He has authored more than 100 research papers including more than 50 in Journals. Mr. Mehra s interest areas are VLSI Design, Embedded System Design, and Advanced DSP. [5] A. G. M. Strollo, D. De Caro, E. Napoli, and N. Petra, A novel high speed sense-amplifier-based flipflop, IEEE Trans. Very Large Scale Integration (VLSI) Syst.,Volume 13, no. 11, pp. 1266 1274, Nov. 2005. [6] Z. Peiyi, M. Jason, K. Weidong, W. Nan, and W. Zhongfeng, Design of Sequential Elements for Low Power Clocking System. IEEE Transaction on Very large Scale Integration, pp. 914-918, July 2 [7] C. K. Teh, M. Hamada, T. Fujita,H. Hara, N. Ikumi, and Y. Oowaki, Conditional Data Mapping Flip-Flops for Low-Power and High-Performance Systems, IEEE Transactions on very large scale integration (VLSI) systems, Volume 14, No. 12, pp. 1379-1383, December 2006. [8]Tanvi Sood, Rajesh Mehra, "Design a Low Power Half Subtractor Using 90 μm CMOS Technology", IOSR journal of VLSI and Signal Processing, Volume :2, pp. 51-56, 2013. [9] Bhuvana S, Sangeetha R, A Survey on Sequential Elements for Low Power Clocking System, Journal of Computer Applications, ISSN: 0974 1925, Volume 5, 10 February 2012. [10] Prashant Upadhyay, Rajesh Mehra, "Low Power Design of 64-bits Memory by using 8-T Proposed SRAM Cell", International Journal of Research and Reviews in Computer Science, Volume 1, pp. 168-172, 2010, ISBN 2079-2557. [10] Pushpa Saini, Rajesh Mehra, "A Novel Technique for Glitch and Leakage Power Reduction in CMOS VLSI Circuits", International Journal of Advanced Computer Science and Applications, Volume 3, pp. 161-168, 2012, ISBN 0975-888. [11] Akhilesh Verma, Rajesh Mehra, "Design and Analysis of Conventional and Ratioed CMOS Logic Circuit", IOSR Journal of Engineering, Volume 2, pp. 25-29, 2013. [12] Anjali Sharma, Rajesh Mehra, "Area and Power Efficient CMOS Design by hybridizing PTL and GDl Techniques", International Journal of Computer Applications, Volume 66, pp. 15-22, 2013, ISBN 0975-888 AUTHORS BIOGRAPHY Neha Thapa is currently pursuing Regular M.E. from National Institute of Technical Teachers Training and Research, Chandigarh Sec-26. She has completed her B.Tech from Amritsar college of Engineering & Technology, Amritsar (Punjab). Dr. Rajesh Mehra is currently Associate Professor at National Institute of Technical Teachers Training & Research, Chandigarh, India. He has completed his M.E. From NITTTR, Chandigarh, India and B. Tech.from NIT, ISSN: 2231-2803 http://www.ijcttjournal.org Page 62