Power Analysis of Double Edge Triggered Flip-Flop using Signal Feed-Through Technique

Power Analysis of Double Edge Triggered Flip-Flop using Signal Feed-Through Technique Pragati Gupta 1, Dr. Rajesh Mehra 2 M.E. Scholar 1, Associate Professor 2 Department of Electronic and Communication Engineering NITTTR, Chandigarh ABSTRACT: For VLSI circuit applications Power consumption of the circuit is most crucial factor. In this brief, Explicit type pulse trigger flip flop is implemented using the cadence tool at CMOS 90nm Technology. This paper works in 1V supply voltage to optimize the size of gate terminal for low power dissipation. This Explicit type flip-flop use an explicit source for pulse generation that is double edge trigger pulse generator, that require half of clock frequency than single edge trigger pulse generator. The proposed a new Double Edge Triggered pulse generator, which is suitable for low power applications. The Pulse generation logic used is shared for many numbers of flip flop at a time this shows result in reduction of power. If any circuit dissipates low power means heat generation of that circuit is also low that increase durability of that circuit, which is achieved in this paper. Keywords - Flip-flop, power dissipation, pulse generation and VLSI. I. INTROUCTION Digital electronics use digital signal or can say that discrete value of continuous signals and these continuous signals are called analog signals. The digital signal is having two states, mainly 0 or 1, where one represents a high logic and 0 represents low logic. Digital signals are more advantageous than analog signals as they are from noise. When digital are transmitted no degradation of transmitted signal occur through noise as occur in analog signals. For example, continuous signals, i.e. audio signals are transmitted in the form of 0 and 1, then these signals are reconstructed without degradation of noise. When digital signals are represented by more binary digit, then performance is better than the low digits. Digital circuits are constructed by small logic circuit means by using logic gates that are helpful to create combinational logic. Electrically controlled switches use maximum time for the creation of logic gate, most commonly transistors are used previously. The output of one logic gate is working as input to other logic gate or can say feedback to it for controlling. Multiple transistors are fabricated on single silicon chip to form integrated circuit as this is the simplest and less exclusive way to form logic gates. Enginners design integrated circuits by automation software by taking these requirements and perform functions [1]. Digital systems are divided into two types first is combinational system and second is sequential system. When same input are given to the combinational circuit then same output is obtained. It is a simple representation of logic functions. When feedback is applied to the combinational circuit then these circuits are called sequential circuit. This will have to perform logic operations and make it useful digital world. The simplest example of sequential circuits are flip-flops, a device that characterizes a digit that is binary or called bit. Finite state machines is basic sequential machine. This is the method design by engineers to judge the system performance and test it for simulation, this will be done deprived of allowing for all the facts of the logic functions. Sequential systems are divided into two classes. One is synchronous system and another is asynchronous systems. When clock signals state change then the state of synchronous sequential system will change all at one time [2]. When input changes at any time that change will reflect at the output an asynchronous system. Design of Synchronous sequential logic are use of thrivingcategorized asynchronous sequential circuits as flipflops, in which changes occur only when the clock pulse change or varied, and which have cautiously considered timing margins. The synchronous state machine are implemented in simple way by divide it into two categories one combinational logic and another set of flip flops that is named a "state register." The state register will take the feedback signal that generate from the previous input state as the clock signal arrive and send back to the unchanging input to the combinational part of the state machine. For most of the time intervening calculation fastest rate of clock is settled in the combinational logic. State register is used for the representation of binary number. Numbers are given to every state in state register, so the states of state machine are easy to manage then next state in combinational logic is produce by the logic function [3]. ISSN: 2231-5381 http://www.ijettjournal.org Page 204

Mostly all types of digital machines are synchronous because of the simplicity of the synchronous designs and easy verification. As we know there are two types of logic synchronous and asynchronous, asynchronous design is better because of the speed in this design is not forced by an random clock. Instead, maximum speed of logic gate is obtained. Asynchronous system is faster by using faster parts. Many times synchronous systems needs asynchronous systems externally for faster operation. These types of circuits are asynchronous in their design. Examples of such types of circuit which includes synchronizers are flip-flops, switches etc [4]. Designing of asynchronous logic circuits are hard because their logic components are difficult to design in which timing is most considering factor in all possible states. Generally used method for this is to make a table containing information of time and adjust all these circuits to decrease the number of states [5]. After all this circuit is forced by the designer to wait for compatible state this is called resynchronization. If all these design strategy are not adopted then the design produce asynchronous design logic and astable states. This type of results are called real electronics because of delay caused by small disparities in the values of electronic components. A flip-flop is a circuit that consist two stable states and similarly latch that also have two states, both are used to store information of state. A flip-flop have one or two output and its circuit can be finished to vary state by signals applied to one control inputs or more then one. The flip-flop is the fundamental storage element if talked about sequential logic family. Flip-flops consist main applications areas similarly latches in computer area, communications purpose, and former types of systems. Flip-flops and latches are generally used as data storage [1]. A flipflop stores a single bit of data; one of its two states represents a "one" and the other represents a "zero". Such data its storage is used for storage of state and circuit is defined as sequential logic. If talk about finite-state machine, the output of FSM and its next state depend not only on its current input. Its other uses are for counting of pulses, and for synchronizing variably-timed input signals to some reference timing signal. When discussed about clocked signals and circuit it is easy to replace the term flip-flop, and the simple circuit are called latches [3]. For high speed applications as well as low power operations Pulse-triggered FF (P-FF) has been measured a popular alternate to the conventional master slave-based FF. A key design experiment of the electronics industry is the overall power dissipation of integrated circuits (ICs).The most power consuming system is the clock system, which involves of the clock distribution network and sequential elements (flip-flops and latches in a VLSI system, consist for 35% to 65% of the total power dissipation in a system [5]. Consequently, Total power consumed by flip flop is directly affected by the power consumed by these components. The clock drivers consume a large portion of on chip power. While designing a clock system we must be cautious to reduce clock load. Circuit simplicity is not only the speed advantage but for the clock tree system it also help in decreasing the consumed power by the system. [6] II. PULSE TRIGGER FLIP FLOP Explicit type source is used in P-FF for pulse generation which consist for strobe signs and a latch signals on behalf of data storage. Meanwhile pulse width of activating pulses produced on the conversion edges of the clock signal are very thin, the latch works as an edge-triggered FF. In master slave configuration two latches are used.the complication of a P-FF is abridged from masterslave, as it consist only one latch, that is needed. Borrowing of time across clock cycle is also need full. Not only these benefits Pulse clock dissemination net requires pulse generation circuitry for subtle pulse width regulator in the aspect of development dissimilarity [4]. On the technique of pulse generation, P-FF designs can be defined as implicit or explicit [6]. In implicit-type P-FF, no external pulse generator circuit, and no exterior pulse signals are produced. In an explicit-type P-FF, PG is not a part of design, pulse of Numerous classes of FFs had been anticipated to realize a favorite energy and delay adjustment and subject on the structures of the submission (high swiftness and low energy etc.) [7]. The choice of flip flop used for particular on application is very difficult task, so is their assortment, as it depends upon transistors sizing and already existing designs. In precise, an appropriate size and choice of methodology is important to get unfailing results that are used in real-world designs. As in explicit type P-FF pulse generator are separate from the design,but this design better in terms of delay But is talk about, implicit type P-FFs, they gives more power advantage. Nevertheless, Longer discharging path occur in these circuits, so that characteristics of time are low-grade [8, 9]. This type of logic separation provide better speed that occur from latch design FF. If the shearing of pulse generator is used that is the input source then the power consumption and complexity of circuit can be exceptionally reduced. III. PROPOSED DESIGN SIMULATION All type of flip flop that are developed previously by different technique [2, 3], suffers from worst case ISSN: 2231-5381 http://www.ijettjournal.org Page 205

timing occurring at 0 to 1 data stuck when transitions occur from 1 to 0 or 0 to 1, the proposed explicit type pulse triggered flip-flop design will use a signal feed-through technique to improve this type of discharging path problem, that is basically a delay. For this double edge triggered pulse generator is used as input source [10]. As in SCDFF design, the DETPFF design also use a static latch structure to avoid superfluous switching at an node x,as show in output waveform of figure 7.In this design a pull-up pmos transistor P1is used that is having weedy pull up with ground is on gate terminal and it is a first stage. Second, a pass transistor that is controlled by the pulse clock that is directly connected to input data pulse is comprised therefore input data can directly drive node Q of the latch directly that s by it is called that the design is constructed by signal feed through scheme. Data transition delay is also shorten up by pulled the main node level [11]. The transistor behind the x node is provides a discharging path. Thus this transistor have dual fold, i.e., it provides extra lashing to node Q during 0 to 1 data transitions, and discharging node x d when 1 to 0 data transitions occur [1]. This the one extra component introduced is an nmos pass transistor to support signal feed through. All design encounter the problem of 0 to 1 delay is improved by this signal feed through scheme. With regards to other P-FF designs the proposed design shows the most balanced delay behaviors.[12, 13] The proposed design i.e dual edge-triggered P-flipflops will help to decrease the clock frequency to half that of the old design which used single edgetriggered pulse generator for the flip-flops, while continuing the same data output. In fact, the dualedge triggered flip-flop involves lower clock frequency than the single-edge triggered flip-flop and to accomplish analogous performance. At the half of clock frequency the dual edge triggered flip flop gives the same data output of single edge-trigger flip-flop gives, So the proposed design gives power economical circuit. Firstly the performance of existing flip-flop design is evaluated,the existing flip-flop designs are explicit-data Close to Output, Static Conditional Discharge Flip-Flop, CDFF and pulse triggered flip flop using signal feed through scheme. By the performance evaluation that is already done before[1],it is clear that P-FF design using signal feed through scheme gives lowest power. This paper compared the performance in terms of power by the existing flip-flop design and proposed flip-flop design.the existing flip flop design is explicit type pulse trigger flip flop, which use a pulse generator that is a single edge trigger pulse generator, But in proposed design double edge triggered pulse generator is used in which Both positive and negative edges are used to sample the D input at alternative clock edges [14]. Fig.1: Schematic of single edge pulse generator Fig. 2:Schematic of double edge pulse generator As in the single-edge triggered pulse generator NAND logic is used that gives output at the rise edge of the clock. Whereas the output takes the value of the input that is the clock pulse that contain 40ns pulse width in dual-edge triggered FF at both the rising edge and falling edge of the clock. The change in the output occurs only at the edge of clock, and if the input changes at other times, the output will be same. So in this paper first the input sources are designed that are pulse generator single edge triggered and double edge triggered. Double edge triggered pulse generator is designed using NMOS and operating voltage is 1V, and it consist 5 inverters Fig.3: O/p Waveform of single edge pulse generator ISSN: 2231-5381 http://www.ijettjournal.org Page 206

Fig.4:O/p Waveform of double edge pulse generator The output waveform of pulse generator shown above, that indicates that pulse is obtained in double edge trigger flip flop at together rising edge of clock pulse and falling edge of clock pulse in comparison to single edge trigger pulse generator generate pulse only rising edge of clock and it will share in a group of various transistor. Fig.6: O/P waveform of single edge trigger flip-flop The virtuoso is used as a simulation tool and target technology is the 90-nm CMOS. The design specification for pulse generator logic with pulse width of of 80 ps in pulse width. The pulse producers can do its job properly in all aspects to process bends with respect to the latch structures. Each P-FF design is good in performance when subject to the dissipation power of the circuit and power delay product. Fig.5: Schematic of Single edge trigger flip-flop In figure 5 schematic of explicit type pulse trigger flip-flop shown, which made up using cadence tool at 90 nm CMOS technology. In this circuit input source is single edge pulse generator circuit and circuit will work as edge is occur at the rising edge of clock pulse. Fig.7: Schematic of proposed flip-flop Proposed design performance has been evaluated at 1V and 5V, and checked its characteristics, that gives decrement in power from 1V to 5V then power will be constant at higher voltages. Frequency are ISSN: 2231-5381 http://www.ijettjournal.org Page 207

500MHz and noise is calculated by setting the frequency range till 1GHz. Fig.10: DC Characteristics of Proposed flip-flop Fig.8: Transfer curve of proposed flip-flop at 1V Transfer characteristics are plotted by setting input pulses. Firstly rising and falling edges are decided at 20ps and delay at 0. Pulse width selected according to the input voltage and sources of input, it also depends on circuit specification. So the pulse width is 80 ns and period is 40 ns. The design provides output by giving pulse to input source, that firstly designed for start the operation, for fair comparisons the power consumption of the data input. Schematic of both the design shown above having different input source, One in existing design operates on single pulse on rising edge of clock and the second schematic of proposed design works on dual pulse occurs on rising and falling edge of clock and saves half of the clock frequency. DC characteristics are shown of both the design which are necessary for the power calculation. IV. RESULT ANALYSIS Table 1 displays the comparison of power for proposed design and design of flip flop using single edge trigger pulse generator, at 90NM technology power of both the circuits are compared. Table 1: Comparison table for power Parameters Single edge trigger flipflop Proposed Design Power 5.437µW 4.73 µw Technology 90n.m 90nm Fig.9: DC Characteristics of Single edge flip-flop Transistors 24 24 Counts Rising Edge Single Double ISSN: 2231-5381 http://www.ijettjournal.org Page 208

6 5 4 3 2 1 0 single edge trigger flipflop proposed flip flop Fig.11: Comparison Chart of power After analysis of power performances, it is clear that power obtain from the proposed flip-flop design is less in comparison to the single edge trigger explicit type flip-flop design. Power degeneracy is an key factor to decide the circuit reliability and durability. As figure 11 displays the power dissipation of proposed double edge trigger flip-flop is less than the single edge trigger flip-flop, so that heat dissipation is also low and this condition avoid the circuit breakdown. V. CONCLUSION Flip flop are the important element when design the synchronous circuit. So that whole performance of synchronous circuit is directly depend on the flipflop circuit. The main elements which calculate the performances of the flip-flops and effect efficiency of synchronous circuit are power, delay, area and noise. So from these objectives this paper reveals the analysis and comparison of single edge trigger and double edge trigger flip-flop design. As the proposed design is modified so it gives better result and boost up the speed of the circuit by reducing the discharging path problem. Comparison is done on the basis of power. Double edge trigger explicit type flip-flop are require half of frequency as well as require a smaller amount of power than the single edge trigger flip-flop. Power consumption is proposed design then the single edge trigger flipflop. The power of proposed design is 13.3% less than the existing design. So this proposed design reducing the power with same transistor count. REFERENCES [1] Namrata Rapartiwar, Vinod Kapse, Tarun kumar Sahu, Performance Analysis Of Double Edge triggered D flip flop, International Journal of Advanced Research in Computer Engineering & Technology (IJARCET), Volume 3 Issue 5, pp- 1900-1903, May 2014. [2] Peiyi Zhao, Jason Mcneely, Weidong Kuang, Nan Wang, And Zhongfeng Wang, Design Of Sequential Elements For Low Power Clocking System, IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Volume 19, No. 5, pp-914-918, May 2011. [3] David Rennie, DavidLi, Manoj Sachdev, Bharat L. Bhuva, Srikanth Jagannathan, ShiJieWen, and Richard Wong, Performance, Metastability, and Soft-Error Robustness Tradeoffs for Flip-Flops in 40 nm CMOS, IEEE Transactions On Circuits And Systems I, Volume 59, No. 8,pp-1626-1633, August 2012. [4] Massimo Alioto, Elio Consoli, and Gaetano Palumbo, Analysis and Comparison in the Energy-Delay-Area Domain of Nanometer CMOS Flip-Flops: Part I Methodology and Design Strategies IEEE Transactions On Very Large Scale Integration (VLSI) Systems, Volume 19, No. 5, May 2011. [5] Ch.Sreedhar1, K Mariya Priyadarshini, Low Power and Reduce Area Dual Edge Pulse Triggered Flip-Flop Based on Signal Feed-Through Scheme, International Journal of Advanced Research in Electronics and Communication Engineering (IJARECE),Volume 3, Issue 11, pp-1709-1714, November 2014. [6] P. Zhao, J. McNeely, S. Venigalla, G. P. Kumar, M. Bayoumi, N. Wang, and L. Downey, Clocked-pseudo-NMOS flip-flops for level conversion in dual supply systems, IEEE Transaction on Very Large Scale Integr. (VLSI) Syst., Volume 17, No. 9, pp. 1196 1202, Sep. 2009. [7] M.-W. Phyu, W.-L. Goh, and K.-S. Yeo, A low-power static dual edge triggered flip-flop using an output-controlled discharge configuration, in Proc. IEEE Int. Symposium Circuits System, pp. 2429 2432, May 2005. [8] Upwinder Kaur and Rajesh Mehra, Low Power CMOS Counter using clock gated flip flop,international journal of Engineering and Advanced Technology,Vol-2,Issue-4,pp-796-798,April,2013 [9] Jyothi Bandi, K. Rakesh, Explicit Pulse Triggered Flip Flop Design based on a Signal Feed-Through Scheme, International Journal of Soft Computing and Engineering (IJSCE), ISSN: 2231-2307, Volume 4,Issue-5, November 2014. [10] Visvesh S. Sathe, Jerry C. Kao, And Marios C. Papaef thymiou, Resonant-Clock Latch-Based Design, IEEE Journal Of Solid-State Circuits, Volume 43, No. 4, pp-864-963, April 2008. [11] Peiyi Zhao, Tark K. Darwish, And Magdy A. Bayoumi, High-Performance And Low-Power Conditional Discharge Flip- Flop IEEE Transactions On Very Large Scale Integration (VLSI) Systems, vol. 12, no. 5,pp- 477-482, May 2004. [12] Xiaowen Wang and William H. Robinson, A Low-Power Double Edge-Triggered Flip-Flop With Transmission Gates And Clock Gating, IEEE Conference, pp-205-209, 2010. [13]Upwinder Kaur and Rajesh Mehra, Optimization of C,OS 8- bit Counter using SLA and Clock Gating Technique,International Journal of Recent Technology and Engineering, Vol -3 Issue -5, pp. 44-50, July 2013. [14] Tania Gupta, Dr. Rajesh Mehra, Low power explicit pulsed conditional discharge double edge triggered flip-flop, International Journal of Scientific and Engineering Research, Vol. 3, Issue 11, pp-1-6, November 2012. AUTHORS Pragati Gupta received the Bachelors of Technology degree in Electronics and Communication Engineering from Moradabad Institute of Technology, UPTU, Moradabad, India in 2010, and she is pursuing Masters of Engineering degree in Electronics and Communication Engineering from National Institute of Technical Teachers Training & Research, Panjab University, Chandigarh, India. She is an Assistant Professor with the Department of Electronics & Communication Engineering, ISSN: 2231-5381 http://www.ijettjournal.org Page 209

Moradabad Institute of Technology, Moradabad, India. Her current research and teaching interests are in Digital electronics and VLSI. Dr. Rajesh Mehra: Dr. Mehra is currently associated with Electronics and Communication Engineering Department of National Institute of Technical Teachers Training & Research, Chandigarh, India since 1996. He has earned his Doctor of Philosophy in Engineering & Technology and Master of Engineering from Panjab University, Chandigarh, India. He has completed his Bachelor of Technology from NIT, Jalandhar, India. Dr. Mehra has 20 years of academic and research experience. He has more than 350 papers to his credit which are published in refereed International Journals and Conferences. Dr. Mehra has guided 80 ME thesis and he is also guiding 02 PhD scholars. He has also authored one book on PLC & SCADA and developed 06 video films in VLSI area. His research areas are Advanced Digital Signal Processing, VLSI Design, FPGA System Design, Embedded System Design, and Wireless & Mobile Communication. Dr. Mehra is member of IEEE and ISTE. ISSN: 2231-5381 http://www.ijettjournal.org Page 210