Power Device Analysis in Design Flow for Smart Power Technologies

Similar documents
IC Layout Design of Decoders Using DSCH and Microwind Shaik Fazia Kausar MTech, Dr.K.V.Subba Reddy Institute of Technology.

International Research Journal of Engineering and Technology (IRJET) e-issn: Volume: 03 Issue: 07 July p-issn:

An Efficient IC Layout Design of Decoders and Its Applications

Monolithic Optoelectronic Integration of High- Voltage Power FETs and LEDs

Analog, Mixed-Signal, and Radio-Frequency (RF) Electronic Design Laboratory. Electrical and Computer Engineering Department UNC Charlotte

Behavioral Modeling of a Charge Pump Voltage Converter for SoC Functional Verification Purposes

Optimizing BNC PCB Footprint Designs for Digital Video Equipment

FDTD_SPICE Analysis of EMI and SSO of LSI ICs Using a Full Chip Macro Model

SA4NCCP 4-BIT FULL SERIAL ADDER

Technology Overview LTCC

The new MCX Phono Preamp optimizes the inclusion of moving coil step transformers in vinyl playback. RON SUTHERLAND

Good afternoon! My name is Swetha Mettala Gilla you can call me Swetha.

Innovative Fast Timing Design

Why Use the Cypress PSoC?

Integrated Circuit Design ELCT 701 (Winter 2017) Lecture 1: Introduction

Why FPGAs? FPGA Overview. Why FPGAs?

Achieving Faster Time to Tapeout with In-Design, Signoff-Quality Metal Fill

Sharif University of Technology. SoC: Introduction

Advancements in Acoustic Micro-Imaging Tuesday October 11th, 2016

data and is used in digital networks and storage devices. CRC s are easy to implement in binary

ELEC 4609 IC DESIGN TERM PROJECT: DYNAMIC PRSG v1.2

SEMICONDUCTOR TECHNOLOGY -CMOS-

Organic light emitting diode (OLED) displays

PCIe: EYE DIAGRAM ANALYSIS IN HYPERLYNX

Wafer Thinning and Thru-Silicon Vias

GS122-2L. About the speakers:

SEMICONDUCTOR TECHNOLOGY -CMOS-

EL302 DIGITAL INTEGRATED CIRCUITS LAB #3 CMOS EDGE TRIGGERED D FLIP-FLOP. Due İLKER KALYONCU, 10043

Practical De-embedding for Gigabit fixture. Ben Chia Senior Signal Integrity Consultant 5/17/2011

STMicroelectronics L6262S BCD-MOS IC Structural Analysis

IC Mask Design. Christopher Saint Judy Saint

Solutions to Embedded System Design Challenges Part II

RF V W-CDMA BAND 2 LINEAR PA MODULE

Generating Spectrally Rich Data Sets Using Adaptive Band Synthesis Interpolation

SNG-2150C User s Guide

Scan. This is a sample of the first 15 pages of the Scan chapter.

STMicroelectronics NAND128W3A2BN6E 128 Mbit NAND Flash Memory Structural Analysis

Product Brochure. June M5 Series. Metal Detector

UVM Testbench Structure and Coverage Improvement in a Mixed Signal Verification Environment by Mihajlo Katona, Head of Functional Verification, Frobas

Equivalence Checking using Assertion based Technique

CHAPTER 9. Actives Devices: Diodes, Transistors,Tubes

PRESS FOR SUCCESS. Meeting the Document Make-Ready Challenge

STMicroelectronics S550B1A CMOS Image Sensor Imager Process Report

1. Publishable summary

Micro-DCI 53ML5100 Manual Loader

InvenSense Fabless Model for the MEMS Industry

Digital Strobe Tuner. w/ On stage Display

EECS150 - Digital Design Lecture 2 - CMOS

Reconfigurable Neural Net Chip with 32K Connections

Failure Analysis Technology for Advanced Devices

Light Emitting Diodes

2. Depletion MOSFET (DE-MOSFET).

Timing Error Detection: An Adaptive Scheme To Combat Variability EE241 Final Report Nathan Narevsky and Richard Ott {nnarevsky,

Avoiding False Pass or False Fail

LEP400 Etch Depth Monitor Real-time, in-situ plasma etch depth monitoring and end point control plus co-linear wafer vision system

Fieldbus Testing with Online Physical Layer Diagnostics

Laboratory 9 Digital Circuits: Flip Flops, One-Shot, Shift Register, Ripple Counter

The Effect of Wire Length Minimization on Yield

Powering Collaboration and Innovation in the Simulation Design Flow Agilent EEsof Design Forum 2010

Benchtop Portability with ATE Performance

T sors, such that when the bias of a flip-flop circuit is

Multi-Shaped E-Beam Technology for Mask Writing

DESIGN AND IMPLEMENTATION OF SYNCHRONOUS 4-BIT UP COUNTER USING 180NM CMOS PROCESS TECHNOLOGY

Basic LabVIEW Programming Amit J Nimunkar, Sara Karle, Michele Lorenz, Emily Maslonkowski

ADVANCED MICRO DEVICES, 2 CADENCE DESIGN SYSTEMS

Lecture 1: Circuits & Layout

"CHOOSING A STATIC MIXER"

Design of Low Power D-Flip Flop Using True Single Phase Clock (TSPC)

A Ptolemy Based Optical Network Simulator

Electrical & Computer Engineering ECE 491. Introduction to VLSI. Report 1

Static Timing Analysis for Nanometer Designs

E X P E R I M E N T 1

Abstract. Keywords INTRODUCTION. Electron beam has been increasingly used for defect inspection in IC chip

STMicroelectronics Standard Technology offers at CMP in 2017 Deep Sub-Micron, SOI and SiGe Processes

Understanding PQR, DMOS, and PSNR Measurements

7 DESIGN ASPECTS OF IoT PCB DESIGNS JOHN MCMILLAN, MENTOR GRAPHICS

The Syscal family of resistivity meters. Designed for the surveys you do.

High Performance Microprocessor Design and Automation: Overview, Challenges and Opportunities IBM Corporation

Design for Testability

Perfecting the Package Bare and Overmolded Stacked Dies. Understanding Ultrasonic Technology for Advanced Package Inspection. A Sonix White Paper

Project 6: Latches and flip-flops

KRAMER ELECTRONICS LTD. USER MANUAL

A New Methodology for Analog/Mixed-Signal (AMS) SoC Design that Enables AMS Design Reuse and Achieves Full-Custom Performance

Data Acquisition Using LabVIEW

nmos transistor Basics of VLSI Design and Test Solution: CMOS pmos transistor CMOS Inverter First-Order DC Analysis CMOS Inverter: Transient Response

Digital Video Engineering Professional Certification Competencies

Exploratory Analysis of Operational Parameters of Controls

Case Study: Can Video Quality Testing be Scripted?

TA0311 TECHNICAL ARTICLE High Temperature Electronics 1 Introduction 2 Why the need for high-temperature semiconductors?

Product Brochure Version R&S RSC Step Attenuator Where precise signal levels count

Digital Integrated Circuits EECS 312

SC26 Magnetic Field Cancelling System

Electrical Sampling Modules Datasheet 80E11 80E11X1 80E10B 80E09B 80E08B 80E07B 80E04 80E03 80E03-NV

At-speed Testing of SOC ICs

White Paper. Mixed Signal Design & Verification Methodology for Complex SoCs

Triple RTD. On-board Digital Signal Processor. Linearization RTDs 20 Hz averaged outputs 16-bit precision comparator function.

Adding Analog and Mixed Signal Concerns to a Digital VLSI Course

TKK S ASIC-PIIRIEN SUUNNITTELU

Basics Of Digital Logic And Data Representation

Altera s Max+plus II Tutorial

Transcription:

Power Device Analysis in Design Flow for Smart Power Technologies A.Bogani, P.Cacciagrano, G.Ferre`, L.Paciaroni, M.Verga ST Microelectronics, via Tolomeo 1 Cornaredo 20010, Milano, Italy M.Ershov,Y.Feinberg and A.Tcherniaev Silicon Frontline Technology, 595 Millich Dr., Suite 206. Campbell, CA 95008, USA

The goal of this work This work presents a new design methodology for power device design using R3D software for metal interconnects simulation for power devices The novelty of the proposed methodology is in a deep integration of R3D with existing design environment This integration enables an automation and ease of use that make power device design, analysis, and optimization accessible for every designer As a results, higher quality designs can be accomplished in a much shorter period of time avoiding expensive re-spins

Overview Smart Power Technologies Power Device configuration of MOS transistors designed with large channel width and multiple metal layer stacks are commonly used to reduce device ON-resistance (Rdson). Metal5 thick signal Metal4 signal Metal3 signal Metal2 ground signal ground signal ground Metal1 ground signal ground signal ground SEM picture of metal stacks in a power component

Design Methodology request The complete simulation of the voltage and current distribution in such a complex layout is a complicated and time-consuming task STRONG REQUEST Design Methodology to replace expensive silicon runs and reduce the time to obtain a complete electrical analysis of the power structure from months to 4 hours

ST Micro choice for Power Analysis: R3D R3D is a software tool, developed by Silicon Frontline, for extraction, simulation, and analysis of metal interconnects of power semiconductor devices Rigorous efficient 3D field solver for current flow R3D reads in standard files (layout, technology, etc.), and simulates current flow and voltage distributions in metals, vias, and devices Device model: distributed resistors or SPICE elements Capable to simulate various device types MOS, DMOS, LDMOS, vertical DMOS, waffle-style, HEMTs R3D accuracy validated on over 150 various designs Adoption of R3D tool in power technology design flow allows to generate high-quality and error-free designs

R3D features and capabilities Automated Rdson value calculation (device + metal) Visualization of current density and voltage distributions Designing sense point or matched sense device Current density / Electromigration analysis Metal slotting optimization Optimization of metal, via, and wire bonds layouts What if and sensitivity analysis Tradeoff analysis: cost versus efficiency (Rdson) Layout design debug and verification Optimization of metal layouts at early design stages

The need for R3D integration into design flow While R3D can operate in a stand-alone mode, its integration into design flow offers significant advantages: Automation of data input, for multiple device types and technologies Minimization of human error (especially for novice or infrequent users) Shortening of learning curve for designers Possibility for R3D to be used by all designers within an organization Instead of being a tool for an expert user, R3D integrated into design flow becomes a standard design tool that any designer can use for debug, analysis, and optimization Example of automation: Instead of specifying low level information (meshing, metal and device resistivities, layout info, etc.) the user selects the technology name and metal option, and runs R3D in a push button approach

Evaluation results strong benefits Request from design: potential value on power border for a precise sensing 4-hours R3D automatic mesh creation & power simulation 6-months, manual schematic, thousand of elementary blocks to draw Car radio design: Full half-bridge power stage Source Example: analysis of T2 device Drain 0.01 0.02 Source potential along Y axis Zone of inaccuracy of ST model: offset 10mV Source Drain 0.03 0.04 0.05 Results from ST manual model Y direction on power metal border Very good results accuracy ( the tool underlines an inaccuracy of ST Model) in a not comparable time -> great benefit in analysis efforts and in recycle time

Design Flow complexity managing Design & run info supply Connected DB creation Back-end Technology usage Layout/Techno Mapping Results collection and visualization Necessary a GUI to drive the flow Design & run info Technology description DB creation R3D DB / technology mapping Runset info, total current Output file (potential & current distributions)

Design Flow GUI Automation of the whole flow Fully integrated in Design Framework environment Developed internally by STMicroelectronics

Flow linked to Power Generator Tool Power Generator is a STMicroelectronics Tool to generate in automatic way optimized power mos layouts. Two main flows: Power Generator Preview Complete Fast flow (few seconds) to generate a layout preview with only metal layers, no diffusion layers and contact/vias are drawn A time consuming (some hours) flow to obtain a complete power mos A power finger head on layout preview Power Analysis GUI Same power finger head on complete layout

Power Analysis in advance during design flow Power Analysis GUI Possibility to do the analysis in advance, in the design phase, before the verification step A power finger head on layout preview Total device resistance Potential and current density distributions Rdson sensitivity to resistive components

Methodology Results -1 Total current density on metal4 layer 1h of run Preview Layout 5h of run Complete Layout Very good accuracy on current density result in 1/5 of run time!!

Methodology Results -2 Potential value on metal4 layer 1h of run Preview Layout 5h of run Complete Layout The accuracy on potential computation is really acceptable, as the difference in total Ron= 1.05% and in total W=0.01%

Conclusions In STMicroelectronics a design methodology, using an external Tool, to save time for the development of the Power structures (from 20% till 80%) respect to manual actions was validated A simple and user-friendly Graphical User Interface to let the wide usage of this flow was given to design community The possibility to do the Power analysis on a simplified layout structure, for having valuable results in the early stage of design instead during the final verification step, is the other great facility for STMicroelectronics designers Special acknowledgement to Dario Passoni STMicroelectronics for ST Power Layout Generator development and the support to us during the activity