IDEO CELLULAR MATRIX 6 ideo Inputs - 8 ideo Outputs Internal Selectable YC Adders MHz Bandwidth @ -db Selectable 0./6.dB Gain FOR EACH Output High Impedance Switch for each Output (- state operation) Programmable Clamp Mode on each Input (sync bottom or average value) -60dB Crosstalk @ MHz Sub-address Capability I C Bus Control DIP0 (Plastic Package) ORDER CODE: TEA6 DESCRIPTION This device is intended for switching between video and chroma signals such as CBS, SHS, baseband CBS, MAC. Each input clamp mode, each output gain, all switching are controlled through the I C bus. The 8 outputs can be set separately in high impedance state, to enable parallel DC connection of several devices (up to ). SO0L (Plastic Micropackage) ORDER CODE: TEA6D Figure. Pin Connections IN 0 SDA 9 OUT IN 8 OUT SCL 7 OUT IN 6 OUT IN 6 OUT SUB 7 OUT 6 IN P IN 6 8 9 0 OUT 7 OUT 8 GND 6-0.eps September 00 /0
Figure. Block Diagram 6-0.eps Figure. Cellular Matrix Connections st/ addresses nd/ addresses CBS or C I C DECODER I C DECODER 6 INPUTS PROG. CLAMP 6 X 8 Full MATRIX IC ADDER 6 X 8 Full MATRIX IC 6 INPUTS 0dB 6dB STATE OUT 8 OUTPUTS LINES IC IC 6-0.eps /0
ABSOLUTE MAXIMUM RATINGS Symbol Parameter alue Unit Supply oltage I oltage at Pin i to GND 0, T oper Operating Ambient Temperature 0, + 70 o C T stg Storage Temperature -0, + 0 o C THERMAL DATA Symbol Parameter alue Unit R th (j-a) Junction-ambient Thermal Resistance Min. 80 o C/W ELECTRICAL CHARACTERISTICS ( = 8, T amb = oc, IN =, Gain = 6.dB, C load = 0pF, R load =.7kΩ ; Gain condition, clamp and -state are controlled by I C bus, unless otherwise specified) Symbol Parameter Test Conditions Min. Typ. Max. Unit SUPPLY Supply oltage 7. 8 8.8 I CC Supply Current 60 ma RR Supply oltage Rejection f = khz 0 6 db IDEO INPUTS (clamping at bottom sync level) IN Max. Signal Amplitude Clamp Active PP clamp Clamp Level Clamp Active.7. DC Input DC Level Clamp Inactive.7. I IN Leakage Current input connected to output µa I clamp Clamp Current clamp - 00m 0.9 ma IDEO OUTPUTS R OUT Output Resistance 0 W Z HI Output "off" Impedance no load 0 kω C HI C OUT in -state no load pf G oltage Gain f = 00kHz 0 0. db G oltage Gain f = 00kHz 6 6. 7 db sync Top Level Sync (Y or CBS) G = 6.dB, Clamp Active. bias B Output Mean Level (chroma) FUNCTIONAL DESCRIPTION G = 0.dB, Clamp Inactive G = 6.dB, Clamp Inactive Isolation "off" State f = MHz 60 db Crosstalk Attenuation between Channels f = MHz 0 60 db Bandwidth C load = 0pF, G = 6.dB at ± 0.dB at ± db at - db.. 0 MHz This device is controlled via the I C bus. addresses can be selected by a -level detector on Pin 7, thus enabling parallel connection of devices. ia the I C bus : The input signals can be clamped at their negative peak (top sync). The gain factor of the outputs can be selected between 0. and 6.dB. Each of the 6 inputs can be connected to the 8 outputs. Each output can individually be set in a high impedance state. Two internal SHS mixers will add the selected Y and C inputs. Two dedicated outputs will have the option to select this added signal also. /0
I C BUS CHARACTERISTICS Symbol Parameter Test Conditions Standard Mode Fast Mode Min. Max. Min. Max. Unit SCL IL Low Level Input oltage - 0. +. - 0. +. IH High Level Input oltage.0 + 0..0 + 0. I LI Input Leakage Current I = 0 to DD - 0 + 0-0 + 0 µa f SCL Clock Frequency 0 00 0 00 khz t R Input Rise Time. to 000 00 ns t F Input Fall Time. to 00 00 ns C I Input Capacitance 0 0 pf SDA IL Low Level Input oltage - 0. +. - 0. +. IH High Level Input oltage.0 + 0..0 + 0. I LI Input Leakage Current I = 0 to DD - 0 + 0-0 + 0 µa C I Input Capacitance 0 0 pf t R Input Rise Time. to 000 00 ns t F Input Fall Time. to 00 00 ns OL Low Level Output oltage I OL = ma 0. 0. t F Output Fall Time to. 0 0 ns C L Load Capacitance 00 00 pf TIMING t LOW Clock Low Period.7. µs t HIGH Clock High Period.0 0.6 µs t SU, DAT Data Set-up Time 0 00 ns t HD, DAT Data Hold Time 0 0 0 0 ns t SU, STO Set-up Time from Clock High to Stop.0 0.6 µs t BUF Start Set-up Time following a Stop.7. µs t HD, STA Start Hold Time.0 0.6 µs t SU, STA Start Set-up Time following Clock Low-to High Transition.7 0.6 µs Figure. I C Bus Timing SDA t BUF t LOW t f SCL t HD,STA t t r t t HD,DAT HIGH SU,DAT SDA t SU,STA t SU,STO 6-0.eps /0
I C BUS SELECTION I C Bus Slave Address TEA6 Address A6 A A A A A A0 R/W alue 0 0 0 A A0 0 I C Sub-Address Symbol Parameter Conditions Pin 7 oltage (Typ) Unit sub Slave address HEXA Sub-address (see note) A A0 90 0 0 GND 96 9 0 / 9 0 / Note: The first levels are defined by connecting the sub-address pin to the appropriate level. Sub-address will be selected when this pin is left open. st Data Byte Output Select nd Data Byte b7 b6 b b b b b b0 Selected a a a0 * * * * I Output 0 0 0 * * * * 0 OUT 0 0 * * * * 0 OUT 0 0 * * * * 0 OUT 0 * * * * 0 OUT 0 0 * * * * 0 OUT 0 * * * * 0 OUT6 0 * * * * 0 OUT7 * * * * 0 OUT8 Input Select Clamp Gain Mixer Tri-state b7 b6 b b b b b b0 Selected a a a0 * * * * I Output 0 0 0 * * * * IN 0 0 * * * * IN 0 0 * * * * IN 0 * * * * IN 0 0 * * * * IN 0 * * * * IN6 * * * 0 * * * Free * * * * * * Clamped * * * * 0 * * 0.dB * * * * * * 6.dB * * * * * 0 * Disabled * * * * * * Enabled * * * * * * 0 Low impedance * * * * * * Tri-state Power-on-Reset When active: outputs in -state, inputs are clamped Symbol Parameter Test Conditions Min. Typ. Max. Unit Start of Reset Incr.. Reset Decr.. End of Reset Incr.. /0
PIN CONFIGURATIONS Figure. ideo IN Clamp REF REF Clamp Pins - - 6-8 - 0 to Matrix 6-0.eps Figure 6. ideo OUT TRI-STATE TRI-STATE TRI-STATE From Matrix TRI-STATE TRISTATE TRISTATE Pins - - - 6-7 - 8-9 TRISTATE REF TRISTATE 6-06.eps Figure 7. PROG Pin Figure 8. Bus Inputs 7 0kΩ 0kΩ REF to CMOS Pins - ESD PROT. REF to CMOS X TIMES IN // 6-07.eps For SDA only ACKN 6-08.eps 6/0
Figure 9. Typical Application TEA6 (+8) 0nF µf 0µH 0nF.7kΩ.7kΩ Y C EXT SHS OUT SHS IN SHS IN Y C Y C x C C C C C C6 6 8 0 9 T E A 6 0 9 8 7 6.7kΩ CBS/Y C TO PIP PROCESSOR (CBS or Y+C) TO T PROCESSOR (CBS or YC) x I C SDA SCL 7 TUNER OUT (CBS) SCART (CBS IN) SCART (CBS IN) SCART (CBS IN) x C7 C8 C9 C0 C C 6 8 0 9 T E A 6 7 0 9 8 7 6 6x.7kΩ 0nF 0nF SCART (CBS OUT) SCART (CBS OUT) SCART (CBS OUT) Y COMB FILTER C.7kΩ (CBS) SHS / (Y+C) 6-09.eps 7/0
PACKAGE MECHANICAL DATA 0 PINS - PLASTIC DIP Figure 0. 0-Pin Package 8/0
PACKAGE MECHANICAL DATA (Cont d) 0 PINS - PLASTIC MICROPACKAGE Figure. 0-Pin Package 9/0
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