Lab 5 FPGA Design Flow Based on Aldec Active-HDL. Fast Reflex Game. Task 0 (tested during lab demonstration) Get familiar with the Tutorial on FPGA Design Flow based on Aldec Active-HDL. Be ready to perform every step of the design flow for an arbitrary circuit during the Lab 5 Demo. Task 1 (30%) Perform all steps of the FPGA Design Flow for your Top-Level Circuits from 1. Lab 4, Task 5, shown in Fig. 1. 2. Lab 4, Task 6, shown in Fig. 2. Please make sure to correctly set values of generics: 1. DD and k in the Debouncer, so they correspond to the debouncing period of about 10 ms. 2. k in the SSD_DRIVER, so it corresponds to the Refresh period in the range between 1 ms and 16 ms. Test both circuits experimentally, using Nexys 3 board, and verify that they operate correctly. If necessary, modify your VHDL code in order to correct your circuit operation. Fig. 1: Block Diagram of the Top-Level Circuit for Lab 4, Task 5.
Fig. 2: Block Diagram of the Top-Level Circuit for Lab 4, Task 6. Fig. 3: Block Diagram of CLK_RST_3.
Task 2 (20%) Modify your circuit from Lab 4, Task 6, by replacing the CLK_RST_2 unit with the CLK_RST_3 unit shown in Fig. 3. By changing values of the generics CLKFX_DIVIDE and CLKFX_MULTIPLY, set the clock frequency f clkfx to the value about 20-50% above the maximum clock frequency returned by the tools. Demonstrate experimentally that the circuit operates correctly for one clock frequency (100 MHz), but fails for the second clock frequency (higher than the maximum clock frequency returned by the tools). Observe signals CLOCK100 and CLKFX using oscilloscope for two versions of your circuit (with different values of the DCM_SP generics), in such a way that you can see clock signals with the frequencies of: A. f CLK = 100 MHz B. f CLK = maximum clock frequency returned by the tools C. f CLK = 10 MHz. Document your findings using digital photos. Discuss your observations. Task 3 (50%) Develop a VHDL code for the Fast Reflex Game, specified as follows: At the beginning of the game, the BCD Counter (displayed using a Seven Segment Display) is initialized to 10.00. After pressing the start_stop button (BTNS) the counter starts counting down every 0.01 second: 9.99, 9.98, 9.97,, 0.02, 0.01, 0.00, -0.01, -0.02 The goal is to press the start_stop button again as close as possible to the value 0.00. After the second press, the counter is stopped. The last obtained result can be a. stored with the press of the store button (BTNU) b. skipped with the press of the skip button (BTND). After performing these operations the counter is again initialized to 10.00. Only the last four stored results are remembered by the system. The minimum and the maximum absolute value of the last four stored results is calculated. The clear button (BTNL) clears the storage, and initializes the counter to 10.00.
The next_out button (BTNR) allows displaying 1. current value of the counter 2. the last stored result 3. the result with the minimum absolute value 4. the result with the maximum absolute value. After each press of the next_out button, the mode of display changes to the next one in the wrap- around fashion. The current mode is also indicated with an appropriate number of the rightmost LEDs turned on (1 for the current value of the counter, 2 for the last stored result, etc.). The simultaneous press of the buttons clear (BTNL) and skip (BTND) represents a soft reset. The meaning of the buttons is summarized in Fig. 4. Fig. 4: Meaning of buttons in the Fast Reflex Game.
Fig. 5: Top-level block diagram of the Fast Reflex Game. The block diagram of the top- level circuit is shown in Fig. 5. The circuit uses the following lower- level units: 1. BCD_CD: BCD Counter Down, capable of counting down from 10.00 to - 9.99 2. CU_mod_N: k- bit Counter Up mod N, generating a pulse at the output cout each time the value of the counter changes from N- 1 to 0. The generics k and N should be chosen in such a way that the pulse cout is generated every 0.01 second. 3. RSP: the Result Storage and Processing unit, capable of storing four last results. The circuit should also calculate the minimum and the maximum of absolute values of these results. The select_out signal should allow choosing among: a. the input result, b. the last result (i.e., the result stored most recently), c. the minimum of four stored results, and d. the maximum of four stored results. 4. BUTTON_UNIT: the circuit used to convert a press of each button into a single pulse of the duration of the clock period. 5. CLK_RST_1: simple circuit for generating clk and rst. 6. SSD_DRIVER: Seven Segment Display Driver 7. OUT_FORMAT: a simple circuit for preparing hex inputs to the SSD_DRIVER, and driving LEDs. 8. CONTROLLER: controller based on a finite state machine.
The detailed block diagrams of the circuits 1-6 are provided in the introductory lecture slides. The design of the OUT_FORMAT unit and the CONTROLLER is left up to you. Bonus Task (up to 33% of bonus points) Extend the Fast Reflex Game with additional features of your own invention. The number of points you receive will depend on the usefulness, originality, and complexity of additional features you implement. Deliverables: 1. For Tasks 1: A. A short report stating the status of your two circuits (Lab 4, Task 5 and Lab 4, Task 6) and listing all major changes introduced to your VHDL code in order to eliminate errors observed during experimental testing (after the circuit passed the functional simulation) B. Synthesizable VHDL code C. UCF file D. Resource utilization, minimum clock period, slack, and maximum clock frequency after placing & routing E. Configuration bitstream. 2. For Task 2: A. A short report describing your findings and observations, including photos of the oscilloscope screen B. Synthesizable VHDL code C. Testbench for CLK_RST3 D. UCF file E. Configuration bitstream. 3. For Task 3: A. Syntesizable VHDL code B. Testbench(es) C. UCF file D. Resource utilization, minimum clock period, slack, and maximum clock frequency after placing & routing E. Configuration bitstream.
Important Dates Hands-on Session and Introduction to the Experiment Deliverables Due Demo Due Wednesday Section Thursday Section 02/20/2013 02/21/2013 03/09/2013 03/10/2013 03/11-13/2013 03/11-13/2013