EEL37 Dr. Gugel Spring 26 Exam II Last Name First Open book/open notes, 9-minutes. Calculators permitted. Do not write on the back side of any pages. Page ) points Page 2) 22 points Page 3) 28 points Page ) 2 points Page 5) 6 points TOTAL out of Grade Review Information:. Deadline of request for grade review is the day the exam is returned. 2. Do not make any changes to problems in the test as this will be considered cheating. 3. Write only in this blocked area for a re-grade request.. Simply write the problem number that you would like re-graded. 3 Maximum.. You are given a single D Flip-Flop that has inputs: D, Clk and output: Q. Design a new D Flip-Flop using this device that has two additional inputs: CLR and SET. CLR and SET are synchronous clear and synchronous set. Note: If both CLR & SET are true, assume a synchronous set will occur. Show all circuitry required to design the new device assuming that the D Flip-Flop and any logic gates are available. Note: All signals are high true. ( pt.) D SET CLR Q Page Page Score =
2. You are given a microprocessor with a 2 bit address bus and an 8 bit data bus. The control bus consists of a RW.H (+Read/-Write) signal and a low true data strobe (DS.L). You are given any number of 6K x 8 ROMs and 28K x 8 SRAMs. Place 52K of RAM starting at 6H in the system memory map. Place 96K of ROM in the highest 96K of the system memory map. Show the required Rom & Ram memory devices below. Label all signals and use bus nomenclature where appropriate. Do not show the decode equations below. The decode equations will go in Problems #3 and #. (2 pt.) 3. Show the required decode logic equations for the ROM devices. Your decode signals should match those that you specified for the ROM memory above. (5 pt.). Show the required decode logic equations for the RAM devices. Your decode signals should match those that you specified for the SRAM memory above. (5 pt.) Page 2
5. What is the address range for ROM in the memory map? Hex (2 pt.) 6. What is the address range for the RAM in the memory map? Hex (2 pt.) 7. If all unused address lines on the ROMs are tied high in your circuit in #2, what are the program memory ranges available for each ROM when they are pulled out of the circuit and programmed via an EEPROM programmer? ( pt.) 8. Complete the following VOLTAGE timing diagram for the falling edge triggered JK Flip-Flop assuming asynchronous high-true SET and high-true CLR. Assume ZERO propagation delay. ( pt.) CLOCK SET L CLR L J H K H Q L 9. Using the design found in Appendix A, complete the logic timing diagram below. Assume that the design will be implemented in an EPROM and D Flip-Flops with tp => <=. ( pts.) Complete the Logic Timing Diagram Below: Fill in STATE, A, B & C with the DELAYs above State STATE W Z A B C Page 3
. Use the ASM Diagram in Appendix A. to complete the following problems. Assume one D Flip-Flop and one T Flip- Flop will be used for the state variables and that the output of the most significant D flip-flop is Q and the output of the least significant T flip-flop is Q. Fill out the next state LOGIC table for the design below. (2 pt.) W.L Z.L Q.H Q.H Q.H+ Q.H+ D.H T.H A.H B.L C.L. For the next state logic table above, assume that the design will now be implemented in an 6K x 8 EPROM and that the address lines will be tied as shown below. Show what must be programmed in EPROM for the lowest 8 locations. Don't cares should programmed as Zeros for grading purposes. (2 pt.) EPROM Circuit Below EPROM Memory Address & Contents Address (Hex) Data (Hex) Vcc A3: GND A:8 Vcc A7: W.L Z.L Q.H Q.H A3 A2 A A /CE /OE D D3 D2 D D D.H T.H A.H B.L C.L Page
2. A student is designing a fire alarm system that has two sensor inputs: Heat.L (H) and Smoke.L (S). The outputs to the system are Water_On.H (W) and Alarm.H (A). If the Heat sensor is true, water should be sprinkled in the room and the Alarm also turned on, both immediately. Water should be kept on for as long as Heat is true to put out the fire. If Heat is false and the Smoke sensor is true, just the Alarm should be on for at least 2 minutes and stay on if Smoke remains true. Note: Water on has no minimum time and should only be on when Heat = True to minimize water damage. Create a flow chart for this design. Clk = Min. (6 pt.). Given the ALU in Appendix B, Fill in the signals below for (2 + ) divided by 2 with the final answer in Register A. ( pt.) Note: Use X for unknown Register contents and X for don't care Inputs. tp = Zero and all answers in HEX! clock Input Bus MSA: MSB: MSC2: REG A Hex REG B C Hex REG C Hex Page 5
Appendix A. ASM Diagram for Problems 9 thru 2. State A Z C B State B X W, Z A C State 2 Page 6
Appendix B. ALU with Registered Output Bus INPUT Bus REGA Bus REGB Bus REGC Bus MSA MSA MUX A s MUX B s MSB MSB REGA Bus REG A REG B REGB Bus Combinatorial Logic MSC2: 3 MUX C s REG C () D-FFs MSA/MSB MSA/MSB Bus Selected as Input to REGA/B INPUT Bus (Input3:) REGA Bus (REGA3:) REGB Bus (REGB3:) REGC Bus (REGC3:) MSC2: (Most Significant Bit is on the left) => complement of REGA, result in REGC => REGA AND REGB, result in REGC => REGA OR REGB, result in REGC => REGA to REGC => REGB to REGC => shift REGA right one bit, result in REGC => shift REGA left one bit, result in REGC => REGA ADDED To REGB, result in REGC Page 7