Nan Ya NT5DS32M8AT-7K 256M DDR SDRAM

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Nan Ya NT5DS32M8AT-7K 256M DDR SDRAM Circuit Analysis 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel: 613.829.0414 Fax: 613.829.0515 www.chipworks.com

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Some of the information in this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. 2002 Chipworks Incorporated This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization's corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. 5936LS CAR-0212-001 Revision 1.0 Published: October 11, 2002 Revision 2.0 Published: December 2, 2002 Revision 3.0 Published: October 17, 2003 Revision 4.0 Published: January 8, 2004 Revision 5.0 Published: June 22, 2004 Revision 6.0 Published: November 9, 2004

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Table of Contents Introduction... Page 1 List of Figures... Page 2 Device Summary Sheet... Page 17 Top Level Diagram... Tab 1 Data Path... Tab 2 Address Path... Tab 3 Clocks... Tab 4 Voltage Generators... Tab 5 Row Redundancy... Tab 6 Column Redundancy... Tab 7 Test Modes... Tab 8 Mode Register... Tab 9 Self Refresh... Tab 10 Signal Naming Conventions and Symbol Definitions... Tab 11 Signal Cross-Reference List... Tab 12 About Chipworks... Tab 13

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 2 List of Figures 0.1.1 Package Markings 0.1.2 Package X-Ray 0.1.3 Pin Configuration 0.1.4 Die Markings 0.2.0 Die Photograph 0.2.1 Annotated Die Photograph 0.2.2 Die Architecture 0.3.1 MUX1 Definition 0.3.2 MUX2 Definition 0.3.3 MUX3 Definition 0.4.0 Level Shifted NAND Definition 0.5.0 Latency Counter Flip Flop 0.6.0 Comparator Cell Definition 0.7.0 D Flip-Flop 1 Definition 0.7.1 D Flip-Flop 2 Definition 0.7.2 D Flip-Flop 3 Definition 0.7.3 D Flip-Flop 1A Definition 0.7.4 D Flip-Flop 1B Definition 0.7.5 D Flip-Flop 1C Definition 0.7.6 D Flip-Flop 2A Definition 0.7.7 D Flip-Flop 3A Definition 0.7.8 D Flip-Flop 3B Definition 0.7.9 D Flip-Flop 4A Definition 0.7.10 D Flip-Flop 4B Definition 0.7.11 D Flip-Flop 4C Definition 0.7.12 D Flip-Flop 5 Definition 0.8.0 XOR and XNOR Definitions 0.9.0 Burst Cell Definition 0.10.0 DBSA & Write Driver Architecture 0.11.0 Block Decoding 0.12.0 Address Bitmap 0.13.0 Local Data Bus Access (for one bank) Rev. 3.0 10/15/03 9:25 AM

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 3 1.0.0 Top Level Diagram 2.0.0 Data Path 2.1.0 Memory Access 2.1.1 Cells and Bitline Sense Amplifiers 2.1.2 Data Bus Access 2.1.3 Data Bus Write Drivers 2.1.4 Data Bus Sense Amplifiers 2.1.5 Write Data Line Drivers 2.2.0 Data Output Switches 2.2.1 Data Output Switches 1 2.2.2 Data Output Switches 2 2.2.3 Data Output Switches 3 2.2.4 Data Output Switches 4 2.3.0 Data Input 2.4.0 Data Input Buffer 2.5.0 Data Input Latch 2.6.0 Data Input Steering 2.7.0 Data Input Switches 2.7.1 Data Input Switches 1 2.7.2 Data Input Switches 2 2.8.0 Read Data Line Drivers 2.9.0 Data Output Register 2.10.0 Data Output Buffer 2.11.0 Multibit Test 2.11.1 Multibit Test Comparator 1 2.11.2 Multibit Test Comparator 2 2.11.3 Multibit Test Comparator 3 2.11.4 Multibit Test Comparator 4

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 4 2.11.5 Multibit Test Output 3.0.0 Address Path 3.1.0 Address Input 3.1.1 Address Buffers 3.1.2 Bank Address Buffers 3.1.3 Address Multiplexer 3.1.4 Bank Address Latch 3.2.0 Row Address Path 3.2.1 Row Address Latches 3.3.0 Block Select 3.3.1 Block Predecoders 3.3.2 Block Decoder 3.3.3 X-Block Latches 3.3.4 Load Unlink Generator 3.3.5 Sense Clock Drivers 3.3.6 Bitline Precharge Generator 3.4.0 Row Decoders 3.4.1 Row Predecoders 1 3.4.2 Row Predecoders 2 3.4.3 Row Factor Predecoder 3.4.4 Row Factor Decoder 3.4.5 Wordline Drivers 3.5.0 Master Row Decoders 3.5.1 Master Row Decoders 1 3.5.2 Master Row Decoders 2 3.6.0 Column Address Path 3.7.0 Column Address Delay Line 3.7.1 Column Address Counter/Latch 3.7.2 Sequential Column Addresses (A1 & A2)

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 5 3.7.3 Interleaved Column Addresses (A1 & A2) 3.7.4 Column Addresses (A0 & A9) 3.7.5 Column Addresses (A3 to A8) 3.7.6 Column Address Latch (A9 & A11) 3.7.7 Column Address Counter Clocks 3.7.8 Column Address Counter Control 3.8.0 Column Address Counter 3.8.1 Counter Cell 3.9.0 Column Address Latches 3.9.1 Address Inverters 3.9.2 Secondary Column Predecoders 1 3.9.3 Secondary Column Predecoders 2 3.9.4 Primary Column Predecoders 1 3.9.5 Primary Column Predecoders 2 3.9.6 Column Decoders 3.10.0 Data Address Path 3.10.1 Data Path Decoders 3.10.2 Data Output Switches Control 1 3.10.3 Data Output Switches Control 2 3.10.4 Data Output Switch Register 3.11.0 Refresh Counter 3.11.1 Refresh Counter Cell 3.11.2 Refresh Counter Multiplexer 4.0.0 Clocks 4.1.0 Control Input Buffers 4.1.1 {RAS~} Buffer 4.1.2 RAS/~ Buffer 4.1.3 {CAS~} Buffer 4.1.4 CAS/~ Buffer

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 6 4.1.5 {WE~} Buffer 4.1.6 WE/~ Buffer 4.1.7 {CS~} Buffer 4.1.8 CS/~ Buffer 4.1.9 Chip Select Delay 4.1.10 {CKE~} Buffer 4.1.11 CKE Register 4.1.12 BUFEN~ Generator 4.2.0 Data Mask Input 4.2.1 {DM*} Buffer 4.2.2 {N/C} Buffer 4.2.3 DM* Register 4.2.4 DM* Register Clocks 4.2.5 Data Mask Latches 4.3.0 Internal Clock Generator 4.3.1 {CK/CK~} Buffer 4.3.2 {CK} Buffer 2 4.3.3 {CK} Buffer 3 4.3.4 Clock Generator 1 4.3.5 Clock Generator 2 4.3.6 Clock Generator 3 4.3.7 Clock Generator 4 4.3.8 Clock Generator 5 4.3.9 Clock Buffer Control 4.3.10 Clock Generator Enable 4.3.11 Delay Decoder 4.3.12 Clock Delay Cell 4.4.0 Command Decoders 4.4.1 Command Decoder 1 4.4.2 Command Decoder 2

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 7 4.5.0 Active Cycle Control 4.5.1 Bank Activate 4.5.2 Row Address Load 4.5.3 Active Cycle Monitor 4.5.4 ALLIDLE~ 4.5.5 Block Predecoder Precharge 4.6.0 Row Clocks 4.6.1 Row Clocks 1 4.6.2 Row Clocks 2 4.6.3 Row Clocks 3 4.6.4 Master Row Decoder Disable 4.6.5 Master & Row Factor Precharge 4.6.6 Block Decoder Selector 4.7.0 Column Clocks 4.7.1 Bank Selection 4.7.2 Bank Selection Register 4.7.3 Column Address Clock Generator 4.7.4 YCLKs Generator 4.7.5 Column Predecoder Enable 4.7.6 Data Mask Multiplexer 4.7.7 Write Mask Enable 4.7.8 Read Mask Enable 4.7.9 Read/Write Mask 4.7.10 DBSA & Write Driver Enable 4.7.11 Column Address Counter Burst Clock 4.8.0 Bank Clocks 4.8.1 Bank Clocks 1 4.8.2 Bank Clocks 2 4.8.3 Bank Clocks 3 4.8.4 Bank Clocks 4

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 8 4.8.5 Bank Clocks 5 4.8.6 Bank Clocks 6 4.8.7 Bank Clocks 7 4.8.8 Bank Clocks 8 4.8.9 Bank Clocks 9 4.9.0 Burst and Read/Write Clocks 4.9.1 Read/Write Clocks 4.9.2 Write Latch 4.9.3 Read/Write Pulse Generator 4.9.4 Write Clock Generator 4.9.5 Burst Length Counter 4.10.0 Pipeline Clocks 4.10.1 Latency Counter 4.10.2 Latency Counter 1 4.10.3 Latency Counter 2 4.10.4 Pulse Generator 4.10.5 Latency Counter Clock Input 4.10.6 Pipeline Clocks 1 4.10.7 Bank Activate Selection 4.10.8 Data Output Clock Enable 4.10.9 Data Output Clock Selection 4.10.10 Data Input Steering Selection 4.10.11 Pipeline Clocks 2 4.10.12 Precharge Control 1 4.10.13 Precharge Control 2 4.10.14 Precharge Control 3 4.10.15 Counter 4.10.16 Read/Write Clocks Reset 4.10.17 Data Path Clock Generator 4.11.0 Data Path Control

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 9 4.11.1 Data Path Clocks 4.11.2 Data Output Switch Enable 4.11.3 Write Data Line Driver Enable 4.11.4 Read Data Line Driver Enable 4.11.5 Register 4.11.6 Pulse Generator 4.12.0 Output Register Clocks 4.12.1 Data Output Register Clocks Control 4.12.2 Data Output Path Control 4.12.3 Sequencer 1 4.12.4 Sequencer 2 4.12.5 Data Output Clock Selection 4.13.0 DLL Top Level 4.14.0 DLL Clock Inputs 4.14.1 DLL Clock Multiplexer 4.14.2 Clock Multiplexer 4.15.0 DLL Delay Lines 4.15.1 Reset Pulse Generator 4.15.2 Delay Line 4.15.3 Programmable Delay Lines 4.15.4 Delay Lines 4.15.5 Phase Comparator 4.15.6 Delay Line Registers 4.15.7 Delay Line Decoder 4.16.0 Variable Clock Delay 4.16.1 Tapped Delay Line 4.16.2 DLL Multiplexer Control 4.16.3 Clock 32-to-1 Multiplexer 4.16.4 128-to-1 Multiplexer Output 4.17.0 DLL Counters

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 10 4.17.1 Counter 1 4.17.2 Counter 2 4.17.3 Counter 3 4.17.4 Counter 4 4.18.0 DLL Sequencer 4.18.1 Sequencer Cell 4.18.2 Sequencer Stage 2 4.19.0 DLL Control Circuits 4.19.1 DLL Set/Reset Generator 4.19.2 DLL Control Signals 1 4.19.3 DLL Control Signals 2 4.20.0 {DQS} Buffers 4.20.1 {DQS} Input Buffer 4.20.2 DQS Clock Generator 4.20.3 DQS Output Buffer Control 4.20.4 {DQS} Output Buffer 4.20.5 {DQS} Buffer Current Source 5.0.0 Voltage Generators 5.1.0 VBB Generator 5.1.1 VBB Detector 5.1.2 VBB Oscillators 5.1.3 VBB Pump 5.2.0 Internal VCC Generator 5.2.1 Internal VCC Regulator 1 5.2.2 Internal VCC Regulator 2 5.2.3 Internal VCC Regulator 3 5.2.4 Internal VCC Regulator 4 5.2.5 Internal VCC Control 5.3.0 Sense Voltage Generator

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 11 5.3.1 VSP Bias Generator 5.3.2 Sense Voltage Driver 5.3.3 Sense Voltage Regulator 5.3.4 Sense Voltage Control 5.4.0 VBLP & VCP Generators 5.4.1 VBLP Generator 5.4.2 VCP Generator 5.5.0 VPP Generator 5.5.1 VPP Oscillator 1 5.5.2 VPP Oscillator 2 5.5.3 VPP Pump 5.5.4 VPP Power-Up Pump 5.5.5 VPP Reference Generator 5.5.6 VPP Level Detector 1 5.5.7 VPP Level Detector 2 5.5.8 VPP Level Detector 3 5.5.9 VPP Detector Enable 5.6.0 Voltage Reference Sources 5.6.1 Bandgap Reference Generator 5.6.2 Mask Programmable Resistors 5.6.3 Programmable Current Source 5.6.4 Programmable Resistor 5.6.5 Programmable Reference Generator 5.6.6 Reference Generator 5.6.7 Voltage Reference Select 5.6.8 Voltage Multiplexer 5.6.9 Unused Reference Generator 5.7.0 Power-Up Circuitry 5.7.1 Power-Up Circuit 1 5.7.2 Power-Up Circuit 2

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 12 5.7.3 Power-Up Sequencer 5.7.4 Redundancy Power-Up 5.7.5 Redundancy Sequencer 5.7.6 Power-Up Level Shifter 5.8.0 LH3 Local Supply Generator 5.8.1 LH3 Local Supply Regulator 5.8.2 Programmable Reference Voltage 5.9.0 Voltage Test 5.9.1 Voltage Divider 5.9.2 Voltage Test Multiplexer 5.9.3 Level Shifter 5.10.0 Decoupling Circuitry 5.10.1 Mid-Point Control 6.0.0 Row Redundancy 6.1.0 Row Redundancy Block 6.1.1 Row Redundancy Programming 6.1.2 Master Fuse Latch 6.1.3 Address Fuse Latch 6.1.4 Selector 1 6.1.5 Master Row Decoder Enable 6.2.0 Redundant Master Row Decoder 6.3.0 Redundant Wordline Drivers 6.4.0 Redundancy Test Option 6.5.0 FUSEN~ Generator 6.6.0 Data Line Access 7.0.0 Column Redundancy 7.1.0 Fuse Redundancy Block 7.1.1 Fuse Programming

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 13 7.1.2 Fuse Programming Latches 7.1.3 Column Redundancy Programming Cell 7.1.4 Programming/Address Comparator 7.2.0 Redundancy Programming 7.3.0 Column Redundancy Predecoders 7.4.0 Column Redundancy Predecoders 2 7.5.0 Redundant Column Access 7.6.0 Column Redundancy Bank Select 7.7.0 Column Redundancy Control 1 7.8.0 Column Redundancy Control 2 7.9.0 Test Latch 8.0.0 Test Modes 8.1.0 Test Mode Decoders 8.2.0 Test Registers 8.2.1 Test Mode Predecoders 8.2.2 Test Mode Registers 8.2.3 Test Mode Register Control 8.3.0 Test Mode Reset 8.4.0 Programmable Fuses 8.4.1 Programmable Fuses 1 8.4.2 Programmable Fuses 2 8.4.3 Programmable Fuse Control 8.4.4 Programmable Fuse Control Circuit 8.4.5 Test Mode Address Decoder 8.4.6 Test Latch Addresses 8.5.0 Test Registers 8.5.1 Test Mode Register 1 8.5.2 Test Mode Register 2 8.5.3 Test Mode Register 3

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 14 8.5.4 Test Mode Register 4 8.5.5 Test Mode Register 5 8.5.6 Test Mode Register 6 8.5.7 Test Mode Register 7 8.5.8 Test Mode Register 8 8.5.9 Test Mode Register 9 8.5.10 Test Mode Switch 8.5.11 Test Mode Controls 8.5.12 Test Mode Register 10 8.6.0 Test Mode Registers 8.6.1 Second Stage Test Registers 8.6.2 Test Mode Registers 8.6.3 Test Mode Decoders 8.6.4 Test Mode Register 8.6.5 Test Mode Latches 8.6.6 Test Mode Control 8.6.7 Test Sequencer 8.6.8 Flip Flop 8.7.0 Test Mode Counter 8.7.1 Counter 8.7.2 Counter Control 8.7.3 Counter Latch 8.8.0 VDD Test Mode 8.9.0 Signature Circuit 8.10.0 Refresh Counter Test 9.0.0 Mode Register 9.1.0 Mode Register Set Decoder 9.2.0 Mode Register Set 9.3.0 Extended Mode Register Set

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 15 9.4.0 Mode Register 9.4.1 Mode Register Cells 1 9.4.2 Mode Register Cells 2 9.4.3 Burst Length Decoder 9.4.4 Latency Decoder 9.5.0 Extended Mode Register 9.5.1 Extended Mode Register Cells 1 9.5.2 Extended Mode Register Cells 2 9.5.3 Extended Mode Register Inverters 9.5.4 Extended Mode Decoder Enable 9.5.5 Extended Mode Register Decoder 9.5.6 DLL Enable 9.6.0 Test Clock Generator 10.0.0 Self Refresh 10.1.0 Refresh Control 10.2.0 Self Refresh Control 1 10.3.0 Self Refresh Control 2 10.4.0 Self Refresh Oscillator 10.5.0 Refresh Oscillator Latch 10.6.0 Self Refresh Timer 10.6.1 Self Refresh Timer Cell 10.7.0 Refresh Pulse Generator 10.8.0 Refresh Counter Enable A.1.0 Symbol Conventions 1 A.1.1 Symbol Conventions 2 A.2.0 Symbol Definitions 1 A.2.1 Symbol Definitions 2 A.2.2 Symbol Definitions 3 A.2.3 Symbol Definitions 4

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM Page 16 A.2.4 Symbol Definitions 5 A.2.5 Symbol Definitions 6 A.2.6 Symbol Definitions 7 A.3.0 Logic Gate Size Notation A.4.0 Transistor Size Notation A.5.0 Capacitor Size Notation

Nan Ya NT5DS32M8AT-7K 32Mx8 DDR SDRAM About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at 1-613-829-0414. Chipworks 1891 Robertson Road, Suite 500 Ottawa, Ontario K2H 5B7 Canada T 1-613-829-0414 F 1-613-829-0515 Web site: www.chipworks.com Email: info@chipworks.com Please send any feedback to feedback@chipworks.com

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