FDTD_SPICE Analysis of EMI and SSO of LSI ICs Using a Full Chip Macro Model Norio Matsui Applied Simulation Technology 2025 Gateway Place #318 San Jose, CA USA 95110 matsui@apsimtech.com Neven Orhanovic Applied Simulation Technology 2025 gateway Place #318 San Jose, CA USA 95110 neven@apsimtech.com Hiroshi Wabuka NEC Corporation 4-1-1, Miyazaki, Miyamae-ku, Kawasaki, Japan 216-8555 h-wabuka@bl.jp.nec.com Abstract A method of macro modeling power and ground circuits of an LSI IC taking into account internal gates has been proposed. Major contributors to Simultaneous Switching Output Noise (SSO) and Electromagnetic Interference (EMI) are the power and ground currents of clock circuits in internal gates which are modeled using simple Flip-Flop circuits by summing their gate widths and interconnection capacitances. Using such a macro model, methods for reducing SSO and EMI for such LSI chips are analyzed by FDTD_SPICE. It is shown that the major contributor to SSO and EMI is not I/O circuitry but internal gates. The most effective way to reduce such noise is to implement large decoupling capacitors into a chip. Keywords EMI, SSO, macro model, decoupling capacitors, LSI, FDTD, FDTD_SPICE, SPICE. INTRODUCTION As switching speed and integration of LSI ICs are increased, power and ground noise analysis becomes important, as well as signal integrity. Simultaneous switching output noise (SSO) and common mode Electromagnetic Interference (EMI) should be managed. Conventional signal integrity analysis widely uses I/O buffer models such as IBIS and/or SPICE. To accurately simulate SSO and EMI an I/O buffer model is not enough, because it does not describe power and ground system very well. A power and ground current model of LSI ICs is needed. Since power and ground rails and meshes in an LSI chip are connected to a large number of gates, the internal gate model becomes too large to be used for noise simulation. Therefore, SSO and EMI analysis needs a simplified macro model of LSI ICs. There are two methods to get LSI IC s macro model. The first one is obtained by direct measurement of radiation from LSI ICs [1]. Several methods have been proposed for standardization. Measurement is expensive and time consuming. It needs real ICs. The measurement is normally performed for one loading condition. It is very difficult to get a general model for power and ground currents taking into account loading effect by measurement. The other method is to use computers to automatically extract a macro model from LSI CAD database. One of the early works was proposed in [2]. This assumes triangle current waveforms. Since output impedance is not modeled, the loading effect of power and ground cannot be considered. We have developed a macro modeling system for LSI ICs that accesses the LSI CAD database and considers internal gates and I/O buffers [3]. Since the proposed model is based on SPICE transistor models, it automatically considers waveforms and power loading effect. Once an accurate LSI macro model is obtained by the computer program, we can apply it to SSO and EMI simulation considering imperfect power and ground planes which may have many via holes and slits. We apply an extracted macro model to investigate the effect of decoupling capacitors at various locations such as on board, on package, and on chip on SSO and EMI by using FDTD_SPICE. FDTD_SPICE is a powerful method for the time domain analysis of signal, power, and ground interconnections including nonlinear devices [4 7]. LSI MACRO MODELING USING CAD DATABASE As shown in Fig. 1, an LSI chip is decomposed into internal gates and I/O buffer circuits. Today s LSI ICs have millions of transistors. This number is too large to be used for system level noise simulation. We have developed an automated system to make a simplified macro model of an LSI IC. Figure 1. Typical CMOS LSI circuit. 0-7803-7264-6/02/$17.00 2002 IEEE 99
From our analysis of several CMOS LSI ICs, it is found that the major contributors to power ground switching are clock circuits which comprise about 10% of the internal gate circuits. The rest of the internal gates behave as static filter circuits between power and ground rails. Therefore, the main job in the macro modeling is to simplify the clock circuits. CMOS LSIs mostly use Flip-Flop circuits and inverters. Figure 2 illustrates current flows for two switching stages of a Flip-Flop. Two inverters flow current from VDD to VSS in turn. Figure 3. Summation of Flip-Flop circuits. Figure 2. Current Flow in a Flip-Flop circuit. The simplification process used in the program is described below. 1. First, the clock nets must be specified in the LSI CAD data base. 2. To choose only the clock circuits from the net list of the internal gates, the searching program must be stopped when finding the terminal circuits which are usually Flip-Flops. Therefore, the primitive Flip-Flop circuit names must be prepared before running. 3. All the Flip-Flop circuits connected to the same net are combined into one Flip-Flop circuit shown in Fig. 3. During this process the widths of all the p-ch transistors and all the n-ch transistors are summed, respectively (Fig. 4). As a result, summed p-ch and n-ch transistor widths become very large. All the interconnection capacitances in the CAD data base are also summed. 4. A Flip-Flop primitive circuit may consist of 4 to 40 transistors. This must be simplified to one or two inverters as shown in Fig. 5. The large power consuming transistors must be chosen in this simplification. 5. Similarly, the remaining non-clock circuits are modeled as one Flip-Flop with huge transistor widths. Since non-clock circuits are 50% on 50% off on the average, the resulting Flip-Flop is DC biased. Figure 4. Summation of P-ch and N-ch transistor widths. Figure 5. Two stage inverters simplify complex Flip-Flop. Finally, two or three Flip-Flop circuits are obtained as clock and non-clock macro models for the internal gates. A simplified LCR model of the IC package lead frame is added, resulting in a full chip macro model. Figure 6 shows a macro model of an LSI IC. For instance, 800,000 logic circuits can be converted into a macro model with detailed model (500 transistors) or simplified model (14 transistors) in a few minutes. There are tradeoffs among accuracy, speed, and convergence depending on the number of transistors used in the final macro model. Since all the primitive circuits were written in an internal SPICE, the MOS models were converted into IMIC format Table SPICE [8]. The simulated current waveform at power ports is shown in Fig. 7. 100
Figure 6. Final macro model described in SPICE using transistor models with huge gate widths. Figure 9. Comparison of power port currents of the LSI by magnetic probe. To confirm the accuracy of this macro model, we measured currents with a newly developed micro probe shown in Figure 8. The probe measures near magnetic fields. Figure 9 compares measured and simulated power port currents. Figure 7. Simulated current waveform of a 32-bit LSI (Current: A). Figure 8. Magnetic Probe and Test Board. ANALYSIS OF PCB SSO AND EMI WITH FULL CHIP MACRO MODEL USING FDTD_SPICE This section describes applications of the macro full chip model to Simultaneous Switching Output Noise and common mode Electromagnetic Interference using FDTD SPICE. Analysis method FDTD_SPICE is straightforward method for simulating 3D full-wave and nonlinear circuits in the time domain. The problem is partitioned into two parts. The first part is the nonlinear circuit part that is solved using SPICE and the second part is the linear distributed part that is solved using FDTD (Finite Difference Time Domain Method). Ports that connect the SPICE partition to the FDTD partition are chosen. The two methods are coupled through ports exchanging port voltage and current information at each time step. The procedure is illustrated in Fig. 10. We used this method for analyzing PCB and EMI, because FDTD_SPICE is very convenient for simulating complex imperfect power, ground, and signal traces with macro SPICE full chip models. 101
SSO Analysis The schematic of the simulated four layer board is illustrated in Fig. 12. We investigated the effect of decoupling capacitors on SSO (Power and Ground noise). Figure 10. FDTD_SPICE ports. Simulation model We made a simple numerical model for simulation. The board size is 210 mm 160 mm with four layers (signal power plane with a slit solid ground plane signal). The printed circuit board is modeled by FDTD and the LSI is modeled by SPICE. Two LSIs described in the former section are mounted on this board. The LSI has 40 output gates. Both output and internal gates are described in Table SPICE. The internal gates and output gates are clocked at 23MHz (44ns) and 15MHz (66ns), respectively. Figure 11 shows the no load current waveforms for these two parts. It should be noted that the currents from the internal gates are much higher than those of the I/O circuits. This is why conventional simulation using I/O buffer models has never succeeded in SSO or EMI analysis. Figure 12. Schematic of simulation model. Figures 13 and 14 show a typical simulation results for SSO and electric fields on the upper power plane. On board capacitor still has large noise which is measured by the peak to peak voltage of power bounce. On chip capacitor may drastically reduce the noise close to ideal ground. Figure 11. I/O and internal gate currents of an LSI. Figure 13. Typical SSO (Power Bounce) evaluation (Voltage: V). 102
Figure 14. Electric fields on a split power plane for on-board capacitor and on-chip capacitor. Figure 15 also compares the effect of a decoupling capacitor on SSO for on-board, on-package, and on-chip placements. From Fig. 16 it is found that decoupling capacitors should be located as close as possible to internal gates. In addition, even if decoupling capacitance values are increased, the SSO will not be reduced under certain values. This behavior may be caused by not removing board pattern and package inductances. Figure 16. Relationship between decoupling ca pacitor value and SSO. EMI Analysis The same model was used for common mode EMI simulation. EMI analysis using FDTD_SPICE is divided into two steps. First FDTD_SPICE extracts currents on the planes and traces. Then the extracted currents are used to calculate far fields [9]. The electric fields for the horizontal polarization are simulated for turn table height = 0.8 m, antenna height = 1 m, and the distance between turntable and antenna is 3 m with turn table rotation angles from 0 to 360 degrees. Figure 17 compares radiation patterns between the internal gate and the I/O circuits. This confirms the radiation from the internal gate currents are much higher than that of I/O circuits. Figure 15. Effect of decoupling capacitors at various locations on SSO. Figure 17. Comparison of radiation pattern from inner gates and from I/O circuits at 100MHz (5dB/µVm per ring). 103
Figure 18 also shows the effect of on-chip decoupling capacitors. On-chip decoupling capacitors are very effective in the elimination of common mode radiation. Although it is not shown, the inductance component of a decoupling capacitor (ESL) is also very important for the effective capacitance. As the capacitance value is increased, the ESL is also increases where the decoupling capacitors will not work as expected. Figure 18. Comparison of radiation pattern between no capacitors and on-chip capacitor. CONCLUSION Conventional signal integrity analysis has been performed using I/O buffer models such as IBIS, where perfect ground is assumed. In contrast, SSO or EMI are caused by power and ground currents of LSI ICs. Accurate analysis of SSO and EMI needs accurate LSI power and ground models. To simulate or analyze system level SSO and EMI, it is necessary to get a simple enough model with accurately represented internal gate currents along power and ground leads of the whole chip. We have developed a method to obtain a simple macro model for an LSI chip which has millions of transistors. It is found that the major contributors to power and ground currents are currents along clock gate nets, which represent 10% of all the gates, and that the rest of the gates behave as decoupling capacitors. A whole chip is modeled by a couple of Flip-Flop circuits with large gate widths and interconnection capacitances. The simulated currents of power and ground of an LSI processor show good agreement with the currents measured with a near field probe. Using an extracted macro model for the internal gate model, we investigated noise reduction techniques for LSI chips. Electric and magnetic fields, voltage and current distributions and waveforms, and far field EMI can be successfully simulated. To reduce both EMI and SSO, the most effective approach is to implement decoupling capacitors on the chip. The developed techniques can be applied to optimize the LSI performance by predicting noise for system level. REFERENCES [1] M. Coenen, On-chip Measures to Achieve EMC, 12 th International Zurich Symposium and Technical Exhibition on Electromagnetic Compatibility, pp.31-36, February, 1997. [2] K. Shimazaki, H. Tsujikawa, S. Kojima, and S. Hirano, LEMINGS: LSI s EMI-Noise Analysis with Gate Level Simulator, IEEE 1 st International Symposium on Quality Electronic Design, pp.129-136, March, 2000. [3] N. Matsui and H. Wabuka, LSI Power and Ground Model for EMI Simulation, IBIS Summit, January 2001. [4] W. Sui, D. A. Christensen, and C. H. Durney, Extending the Two-Dimensional FDTD Method to Hybrid Electromagnetic Systems with Active and Passive Lumped Elements, IEEE Trans. on Microwave Theory and Techniques, Vol. 40, No.4, pp. 724-730, April, 1992. [5] M. Picket-May, A. Taflove, and J. Baron, FD-TD Modeling of Digital Signal Propagation in 3-D Circuits With Passive and Active Loads, IEEE Trans. on Microwave Theory and Techniques, Vol. 42, No.8, pp. 1514-1523, August, 1994. [6] N. Orhanovic, R. Raghuram, and N. Matsui, Nonlinear Full Wave Time Domain Solutions using FDTD_SPICE for High Speed Digital and RF, DesignCon, January 2001. [7] N. Orhanovic and N. Matsui, Full Wave Signal and Power Integrity Analysis of Printed Circuit Boards Using 2D and 3D FDTD_SPICE Methods, DesignCon, January 2002. [8] R. Raghuram, Validation of EIAJ IMIC Models, IBIS Summit, December 1998. [9] N. Matsui, R. Raghuram, and D. Divekar, SPICE Based Analysis of Radiation from PCBs and Related Structures, International Symposium on Electronic Compatibility, pp. 320-325, August 1996. 104