Evaluation of Fibonacci Test Pattern Generator for Cost Effective IC Testing

Evaluation of Fibonacci Test Pattern Generator for Cost Effective IC Testing Md. Tanveer Ahmed, Liakot Ali Department of Information and Communication Technology Institute of Information and Communication Technology Bangladesh University of Engineering and Technology, Bangladesh cs_tanveer@yahoo.com Abstract- Integrated Circuits (ICs) are the key components in all modern electronic equipments. With the increase in complexities of ICs, it is a challenging issue to test ICs at low cost with reliable performance. In this paper we investigate the performance of IC. It is shown that Fibonacci Linear Feedback Shift Register (FLFSR) performs better in testing of IC. This paper presents a new architecture for test pattern generator that produces the highest fault coverage (FC) with minimum number of pseudo random test vectors. This paper focuses on the design and implementation of a 64-bit Fibonacci test pattern generator capable of generating sufficient long test pattern and conducting fault simulation experiments on International Symposium on Circuits and Systems (ISCAS) benchmark circuits. Test pattern generator is very important in VLSI Testing. By changing the seed and feedback connection, a set of test vectors was generated for different benchmark circuits. The objective was to produce Test Pattern with good randomness; then fault coverage will be better. Fault simulation was done using FSIM fault simulator. Keywords- Linear Feedback Shift Register (LFSR); Fibonacci Linear Feedback Shift Register (FLFSR); Galois Linear Feedback Shift Register (GLFSR); Fault Coverage (FC); Test Vector (TV) I. INTRODUCTION With the dramatic improvement of semiconductor technology, the design complexities and packing densities of ICs have exceedingly increased. In IC manufacturing, various physical defects may occur during numerous physical, chemical and thermal processes. With the increase of the complexities of VLSI circuit, testing problem has become more acute [1]. To achieve the IC testing at low cost with reliable performance, researchers have proposed different testing approaches [2-5], among which mixed mode technique outperforms all the other proposed techniques. In mixed mode technique, Circuit Under Test (CUT) is first subjected under pseudo-random testing mode and then at an optimum point of fault coverage it is switched to deterministic test mode. In mixed mode technique, pseudo-random test pattern generation and proper switching point from pseudo-random test mode to deterministic test mode are very important to make the testing process cost-effective. Recently, Fibonacci pseudo-random test pattern generator has been proved efficient in many cryptographic applications because of its better randomness [6]. Usually, Linear Feedback Shift Register (LFSR) and Cellular Automata Register (CAR) are popular in pseudo-random test pattern generation. Due to the limitations of integration and fabrication technology, previous researchers used 32-bit LFSR or CAR in designing IC tester or test processor chip. However, now integration technology has tremendously improved. In this project, a 64- bit Fibonacci test pattern generator, which is a modified version of LFSR, has been evaluated in VLSI testing. Fibonacci test pattern generator has already been used in many cryptographic applications and proved very much efficient. So, there are scopes of research to evaluate its effectiveness in VLSI testing. Fig. 1 Fault Coverage versus Random test vectors [16] - 28 -

A typical fault detection curve during fault simulation is shown in Fig. 1. When simulation begins, a large percentage of faults are detected in a short amount of time. However, as time goes on, the rate at which faults are detected decreases because the test patterns applied detect many faults that have already been detected. If these detected faults are not dropped, extra time is spent on resimulating these faults but the fault coverage remains the same. A. Basic Description II. LINEAR FEEDBACK SHIFT REGISTER (LFSR) LFSRs in the simplest definition are used as pseudorandom number generators. An LFSR with a well-chosen feedback function can produce a sequence of bits that appears random and has a very long cycle [9]. The initial value of the LFSR is called the seed. The bit positions in the LFSR state, which influences the input, are called taps. These are chosen based on the primitive polynomial. The arrangement of taps for feedback in an LFSR can be expressed in finite field arithmetic as a polynomial mod 2. This means that the coefficients of the polynomial must be 1's or 0's. This is called the feedback polynomial or the characteristic polynomial. For example, if the taps are at the 16th, 14th, 13th and 11th bits (as shown), the feedback polynomial is 1+x 11 +x 13 +x 14 +x 16. When properly configured for maximum length sequences, each state will be reached only once until every state has been reached. Once every state has been reached, the sequence will be repeated. The applications of LFSR include pseudorandom number generator, random pattern generator and analyzer, encryption/decryption and direct sequence spread spectrum for digital signal processing. There are two major implementations of LFSR, namely the Fibonacci LFSR (FLFSR) and Galois LFSR (GLFSR). Figs. 2.1 and 2.2 show these two types of LFSR each with characteristics polynomial P(x) =1 + c 1 x + c 2 x 2 + + c n x n. If a connection exists, then c i =1, otherwise c i =0. The Fibonacci implementation has logic in the feedback path, whereas the Galois implementation has an output that is fed back to selected points in the feed forward path. B. Galois Linear Feedback Shift Register (GLFSR) As shown in Fig. 2.1, the data flow is from left to right and the feedback path is from right to left. The polynomial increments from left to right with x 0 term (the "1" in the polynomial) as the first term. This is referred to as a Tap polynomial, as it indicates which taps are to be fed back from the shift register. Since the XOR gate is in the shift register path, the Galois implementation is also known as an in-line or modular type (M-type) LFSR Fig. 2.1 Structure of Galois LFSR Fig. 2.2 Structure of Fibonacci LFSR - 29 -

C. Fibonacci Linear Feedback Shift Register (FLFSR) In Fig. 2.2, the data flow is from left to right and the feedback path is from right to left, similar to the Galois implementation. However, in Fibonacci implementation polynomial decrements from left to right with X 0 as the last term in the polynomial. This polynomial is referred to as a Reciprocal Tap polynomial and the feedback taps are incrementally annotated from right to left along the shift register. Since the XOR gate is in the feedback path, the Fibonacci implementation is also known as an out-of-line or simple type (S-type) LFSR. In this study, this type of LFSR was focused on for the experiments. A. Test Pattern generation using FLFSR III. DESIGN AND IMPLEMENTATION First a 64-bit Fibonacci test pattern generator was designed using C programming language. It is user programmable in terms of tap position and seed. Since it is 64 bit, it is capable of generating sufficient long test pattern. Then, test pattern was generated for different benchmark circuits with respect to different seed values and different tap positions of the proposed pseudo-random pattern generator and was saved in different files. Then, fault simulation experiments were conducted using FSIM [8] fault simulator on the different benchmark circuits using the generated test pattern and respective fault coverage was recorded. Finally, the fault simulation results were compared with those of other researchers. B. Feedback Logic In order for an LFSR to iterate through its largest possible sequence of values, it must use a polynomial that will produce such a sequence. The tap positions shown in Fig. 3.1 produce maximum sequence lengths for the proposed 64-bitFLFSR [9]. The LFSR feedback function performs modulo-2 summation. These summations can be performed with either XOR or XNOR gates in the logic. The design uses the Fibonacci approach to implement test pattern generator. Figure 3.1 shows the feedback logic using XOR Fig. for the proposed 64-bit FLFSR with 4 taps. The outputs of the stages of Q64, Q63, Q61 and Q60 were XORed as shown in Fig. 3.1 and the output FB_Out was fed back to the first stage of the FLFSR. Q64 Q63 Q61 XOR inst XOR inst1 XOR inst2 FB_Out Q60 C. Illustration of the FLFSR working Fig. 3.1 Feedback Logic using XOR gates For simplicity, a simple 4-bit FLFSR is considered here. The output of stage 3 and 4 are XORed and fed back to the first stage of the FLFSR. The primitive polynomial for degree 4 is 1 + x 3 + x 4. This demonstrates the proposed test pattern generator. With the application of each clock, the value of each stage of the FLFSR is changed as follows. Assuming the initial value of the FLFSR is 0101. From Figure 3.2 (b), it is seen that the state of the FLFSR repeats after 2 4-1=15 clock cycles. (a) - 30 -

No. of Test Vectors (TV) % of Fault Coverage (FC) Journal of Computer Engineering and Informatics Apr. 2014, Vol. 2 Iss. 2, PP. 28-36 (b) Figure 3.2 (a) Block Diagram, (b) Truth table, (c) State diagramof 4-bit FLFSR with characteristics ploynomial 1 + x 3 + x 4 Note that in Fig. 3.2(a), the outputs of the 3 rd and 4 th stage of the LFSR are XORed and fed back to the first stage. Since the LFSR has four stages, the truth table in Fig. 3.2(b) shows that it has 15 different states. After the 15 th clock cycle the LFSR repeats its states. The 15 distinct states of the LFSR are depicted with the state diagram in Fig. 3.2(c). (c) IV. FAULT SIMULATION RESULTS Pseudo-random testing is a cost-effective means of testing VLSI circuits. Using Fibonacci pseudo-random test patterns, it is possible to achieve a maximum percentage of fault coverage by only applying fewer number of test vectors. This fact was verified in this Paper. The seed of an FLFSR is defined as the initial value of the stages of the FLFSR before starting to generate the test vectors. Forty different seeds were used to generate PRV sequences. The PRV sequences were applied to the benchmark circuits, and fault coverage versus number of PRV was measured with respect to every seed. For seed of the FLFSR in the experiment, one of the stages of the FLFSR was set to 1 and others to 0, and in this paper, 1 is mentioned as seed for simplicity. A lot of variations were done to improve the fault coverage. Figures 4.1, 4.2, 4.3, 4.4 present fault simulation results of the circuits c432.bench, c499.bench, c2670.bench and c3540.bench respectively for the primitive polynomials offering best fault coverage. Figure 4.1 shows that the fault detection capability of the PRV sequences for the benchmark circuit c432.bench varies with the seed of the FLFSR. It is possible to determine the best seed of the FLFSR for the benchmark circuits out of the given seeds. The best seed of the FLFSR produces the highest fault coverage using lowest number of PRV sequences. For example, seed position number 24 in Fig. 4.1 can be considered the best seed of the FLFSR for the benchmark circuit c432.bench. Similarly, seed position number 7 in Fig. 4.2, seed position number 7 in Fig. 4.3 and seed position number 7 in Fig. 4.4 are the best seeds of the FLFSR for the benchmark circuit c499.bench, c2670.bench and c3540.bench, respectively. Note that the best seed position in each figure is marked with an arrow symbol. The number of test vectors and the achieved fault coverage is also mentioned at those points. 400 350 300 250 200 150 100 50 0 TV = 224, FC = 98.47 No. of Test Vectors Fault Coverage 2 3 5 6 8 9 11 12 14 15 17 18 20 21 23 24 26 27 29 30 32 33 35 36 38 39 41 42 44 45 47 48 50 51 53 54 56 57 59 60 Position 99.5 99 98.5 98 97.5 97 96.5 96 95.5 Fig. 4.1 Fault simulation result of circuit c432.bench (for feedback polynomial 1+x 60 +x 61 +x 63 +x 64 ) - 31 -

No. of Test Vectors (TV) % of Fault Coverage (FC) No. of Test Vectors (TV) % of Fault Coverage (FC) No. of Test Vectors (TV) % of Fault Coverage (FC) Journal of Computer Engineering and Informatics Apr. 2014, Vol. 2 Iss. 2, PP. 28-36 700 600 500 400 300 200 100 0 TV = 352, FC = 98.15 No. of Test Vectors Fault Coverage 2 3 5 7 8 9 11 12 14 15 17 18 20 21 23 24 26 27 29 30 32 33 35 36 38 39 41 42 44 45 47 48 50 51 53 54 56 57 59 60 Position 99 98.8 98.6 98.4 98.2 98 97.8 97.6 97.4 97.2 Fig. 4.2 Fault simulation result of circuit c499.bench (for feedback polynomial 1+x 60 +x 61 +x 63 +x 64 ) 1200 1000 800 600 400 200 0 No. of Test Vectors Fault Coverage TV = 250, FC = 83.55 2 3 5 6 8 9 11 12 14 15 17 18 20 21 23 24 26 27 29 30 32 33 35 36 38 39 41 42 44 45 47 48 50 51 53 54 56 57 59 60 Position 85 84.5 84 83.5 83 82.5 82 81.5 81 80.5 Fig. 4.3 Fault simulation result of circuit c2670.bench (for feedback polynomial 1+x60+x61+x63+x64) 1200 1000 800 600 400 200 0 No. of Test Vectors TV = 540, FC = 91.80 Fault Coverage 2 3 5 6 8 9 11 12 14 15 17 18 20 21 23 24 26 27 29 30 32 33 35 36 38 39 41 42 44 45 47 48 50 51 53 54 56 57 59 60 Position 95.5 95 94.5 94 93.5 93 92.5 92 91.5 91 90.5 90 Fig. 4.4 Fault simulation result of circuit c3540.bench (for feedback polynomial 1+x+x3+x4+x64) Forty different seeds were used to generate PRV sequences. The PRV sequences were applied to the benchmark circuits and fault coverage (%) versus number of PRVs was measured with respect to every seed. Figure 4.5 shows the fault detection profile of the PRV sequences for the benchmark circuit c432.bench. Note that the x-axis of Fig. 4.5 contains 40 slots. Each slot contains 5 test vectors to present the curve simply. So, for the 40 slots, there are 200 test vectors. Fig. 4.5 Fault detection profile of PRV for the benchmark circuit c432.bench - 32 -

Figure 4.5 shows that the first few PRVs detected the maximum faults of the circuit c432.bench. Then the slope of the fault detection profile of the PRV rapidly decreased with the increase of the number of test vectors. More than 80 percent faults were detected using only 50 test vectors. These faults were ETD faults. After the detection of the ETD faults, much higher number of test vectors was needed to detect the remaining faults. These remaining faults were HTD faults and random resistant faults. These faults caused potential difficulties in achieving acceptable fault coverage in the pseudo-random testing of IC. Fault detection profiles of the PRV sequences for the rest of the benchmark circuits were similar to that as shown in Fig. 4.5. The figure clearly indicates that with the increase of the number of test vectors, increase of fault coverage sharply decreases and approximates zero. When the increment of fault coverage was very low or almost zero, the mode of test was switched from pseudo-random test to deterministic test. For example, in the simulation result as shown in Figure 4.1, when the number of PRV is 200 for circuit c432.bench, then it is appropriate to switch from the pseudo-random test mode to deterministic mode. Fault simulation results for the rest of the benchmark circuits followed the similar profile. To analyze the effect of reseeding and polynomial programmability on achieving full fault coverage, experiments were performed on different ISCAS85 benchmark circuits. Table 1 presents two samples of 64-degree primitive polynomial such as 1+x 60 +x 61 +x 63 +x 64 and 1+x+x 3 +x 4 +x 64 were chosen. For any of the primitive polynomials, the position of the seed was changed from first stage to last stage of the FLFSR and with respect to every bit position, a test vector file was generated. *FC= Fault Coverage *NTV=No. of Test Vectors ISCAS85 Benchmark Circuits TABLE 1 *FC COMPARISON OF TWO DIFFERENT PRIMITIVE POLYNOMIALS *NTV Polynomial1 (1+x+x 3 +x 4 +x 64 ) Polynomial2 (1+x 60 +x 61 +x 63 +x 64 ) c432 224 98.28 98.47 c499 352 97.89 98.15 c880 120 90.13 92.15 c1355 450 95.30 96.76 c1908 930 94.84 96.49 c2670 250 82.71 83.55 c3540 540 91.80 91.57 c5315 600 98.34 98.26 c6288 60 The screenshot of fault simulation result on the ISCAS85 benchmark circuits using the PRV sequences generated by the proposed FLFSR is given in Fig. 4.6. Figure 4.6 Screenshot of fault simulation result of circuit c432.bench (for feedback polynomial 1+x+x 3 +x 4 +x 64 ) - 33 -

Figure 4.6 shows the screenshot of fault simulation result of circuit c432.bench. First it shows the numbers of inputs, outputs, gates and the level of the circuit. The name of the test vector file, output1.test, is also shown. The figure shows that the percentage of fault coverage was 98.282 using 200 test vectors. Among the 524 faults, 515 faults were detected and the remaining 9 faults were undetected. It also shows the amount of memory used and the total CPU time required. Fault simulation experiments were conducted using FSIM digital fault simulator [8] on ISCAS85 benchmark circuits. Summary of the fault simulation results of the ISCAS85 benchmark circuits using the proposed 64-bit FLFSR is presented in Table 2. The table shows the total number of test vector including deterministic vectors required to achieve complete fault coverage for ISCAS benchmark circuit. It shows that 100% fault coverage can be achieved using the proposed technique. TABLE 2 SUMMARY OF FAULT SIMULATION RESULTS OF THE ISCAS85 BENCHMARK CIRCUITS USING THE PROPOSED TECHNIQUE ISCAS85 Benchmark Circuits Total Number of Faults Inserted Number of Test Vectors Random Deterministic Total Number of Test Vectors % Fault Coverage c432 802 200 9 209 100 c499 1306 190 25 215 100 c880 1428 120 61 181 100 c1355 1970 180 126 306 100 c1908 1282 880 69 949 100 c2670 2588 250 452 702 100 c3540 2988 540 281 821 100 c5315 5640 560 91 651 100 c6288 9804 60 414 101 100 V. COMPARISON Table 3 presents the summary of the above fault simulation results by FLFSR generated using FSIM. It also compares the results with those obtained from weighted random method used by other researchers. TABLE 3 COMPARISON OF FAULT SIMULATION RESULTS OF THE ISCAS85 BENCHMARK CIRCUITS WITH THOSE OF OTHER RESEARCHERS ISCAS85 Benchmark Circuits *NTV1 *NTV2 *NTV3 *NTV4 *NTV5 *NTV6 *NTV7 c432 209 214 224 352 320 512 1024 c499 215 225 512 - - - - c880 181 248 160 4544 416 260 1280 c1355 306 314 512 1248 1664 2244 2098 c1908 949 969 992 4608 2496 2308 5376 c2670 702 724 288-6240 10766 5888 c3540 821 271 640 1065 9504 12220 3840 c5315 651 388 640 1632 1950 1316 2048 c6288 101 234 64 - - - - *NTV1 = Number of test vectors required using 64-bit FLFSR based mixed-mode technique in the present work *NTV2 = Number of test vectors required using 32-bit GLFSR based mixed-mode technique [12] *NTV3 = Number of test vectors required using 32-bit LFSR based mixed-mode technique [1] *NTV4 = Number of test vectors using weighted random technique [17] *NTV5 = Number of test vectors using weighted random technique [18] *NTV6 = Number of test vectors using weighted random technique [19] *NTV7 = Number of test vectors using weighted random technique [20] Fault simulation results of the benchmark circuits c499.bench and c6288.bench from other researchers are not available. The sign in Table 4 indicates the unavailability of the actual data. The comparison showed that the proposed Fibonacci test pattern generator in mixed mode approach was capable of producing 100% fault coverage using much smaller number of test vectors than other researchers. - 34 -

A. Coefficient of Variation (CV) VI. BEST SEED DETERMINATION Coefficient of Variation (CV) is a relative measure in Statistics. This measure developed by Karl Pearson is the most commonly used measure of relative variation. It is used in such problems where comparing the variability of two or more than two series is needed. The series for which the coefficient of variation is greater is said to be more variable or conversely less consistent, less uniform, less stable, and less homogeneous. On the other hand, the series for which the coefficient of variation is less is said to be less variable or more consistent, more uniform, more stable, and more homogeneous. CV is obtained as follows: where = Standard Deviation and X = Arithmetic Mean. To measure the CV of a PRV sequence for a particular seed for a benchmark circuit, MATLAB R2012b was used. To compare the values of CVs of PRV sequences generated for different seeds, a number of different seeds were selected randomly. The CVs of PRV sequences for different seeds were compared. The result is given in Table 4. TABLE 4 CVS OF PRV SEQUENCES FOR DIFFERENT SEEDS FOR DIFFERENT BENCHMARK CIRCUITS, c432 c499 6 15 23 24 26 118.54 115.58 116.51 119.01 118.41 118.30 118.30 115.31 113.86 113.77 5 7 12 18 24 109.51 112.39 111.25 111.70 108.25 110.23 109.35 110.13 111.47 110.88 35 33 38 42 42 47 51 54 59 60 From Table 5 it is observed clearly that the value of CV of the PRV sequence is the maximum for the seed 24 for benchmark circuit c432.bench. Therefore, it can be concluded that the PRV sequence generated for seed 24 is more random as compared to other seeds. As a result, seed 24 for circuit c432.bench was determined as the best seed. In a similar way, seed 7 for circuit c499.bench was the best seed. Results of CVs for the rest of the benchmark circuits followed the similar profile. VII. CONCLUSIONS This paper highlights the design and implementation of a 64-bit Fibonacci test pattern generator capable of generating sufficient long test pattern. Experiments were carried out on different seeds and primitive polynomials to achieve highest percentage of fault coverage. In the simulation results, it was shown that by changing the seeds and feedback polynomial, fault coverage was improved with lower number of test vectors than using single polynomial and single seed. In the comparison section, it was shown that the proposed Fibonacci test pattern generator in mixed mode approach was capable of producing the highest fault coverage using much lower number of test vectors than other researchers. Moreover, the best seed and optimum switching point were examined by conducting fault simulation experiments on ISCAS benchmark circuits. Determination of the best seed was again verified by calculating the coefficient of variation of the random sequences that have been applied to the benchmark circuits. Based on the result in this paper, initiative can be taken for designing low cost IC Tester. ACKNOWLEDGMENT The author is grateful to IICT, BUET for providing facilities for the research, and all the reviewers for their excellent comments. REFERENCES [1] Liakot A., Roslina S., Ishak A., Alauddin M. A, Bambang S. S., Challenge and Directions for IC testing, Integration, the VLSI Journal, pp. 17-28, Vol. 37(1), Elsevier Science, Netherland, Feb. 2004. [2] Bardell P.H., McAnney W.H., Savir J., Built in Test for VLSI: Pseudorandom Techniques, New York: John Wiley & Sons, 1987. [3] Brglez F. et al. Hardware-based weighted random pattern generation for boundary-scan, Proc. of IEEE Int. Test Conf., pp. 264-274, Washington, USA, 1989. [4] Hellebrand S., Rajski J., Tarnick S., Venkataraman S., Courtois B., Built-in testfor circuits with scan based on reseeding of multiplepolynomial linear feedback shift registers, IEEE Transactions on Computers, Vol. 44(2), pp. 223 233,1995. [5] Koenemann, B., Mucha J. and Zwiehoff, G., Built-in Test for complex Digital Integrated circuits, IEEE Journal of Solid-State Circuits, Vol. SC-15(3), pp. 315-318,1980. - 35 -

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