HW 261: Logic Design Instructors: Prof. Hala Zayed Dr. Ahmed Shalaby http://www.bu.edu.eg/staff/halazayed14 http://bu.edu.eg/staff/ahmedshalaby14# Slide 1
Digital Fundamentals HAPTER Shift Registers Slide 2
Shift Registers Basic Shift Register Operations A shift register is an arrangement of flip-flops with important applications in storage and movement of data. Some basic data movements are illustrated here. Data in Data in Data out Data out Data in Data out Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out Data in Data in Data out Data out Serial in/parallel out Parallel in/parallel out Rotate right Rotate left Slide 3
Shift Registers Serial-in/Serial out Shift Register Shift registers are available in I form or can be constructed from discrete flip-flops as is shown here with a five-bit serial-in serial-out register. Each clock pulse will move an input bit to the next flip-flop. For example, a 1 is shown as it moves across. 1 1 1 1 1 Slide 4
Shift Registers Serial-in/Serial out Shift Register Slide 5
Shift Registers Serial in/parallel out Shift Register An application of shift registers is conversion of serial data to parallel form. Slide 6
Shift Registers Serial in/parallel out Shift Register Slide 7
Shift Registers Parallel in/serial out Shift Register An application of shift registers is conversion of parallel data to serial form. Slide 8
Shift Registers Parallel in/serial out Shift Register Slide 9
Shift Registers Parallel in/parallel out Shift Register Slide 10
Bidirectional Shift Register Shift Registers Bidirectional shift registers can shift the data in either direction using a RIGHT/LEFT input. Slide 11
Universal Shift Register Shift Registers A universal shift register has both serial and parallel input and output capability. The 74H194 is an example of a 4-bit bidirectional universal shift register. D 0 D 1 D 2 D 3 LR S 0 S 1 SR SER SL SER LK (1) (9) (10) (2) (7) (11) (3) (4) (5) (6) SRG 4 (15) (14) (13) (12) Q 0 Q 1 Q 2 Q 3 Slide 12
Shift Register Applications Shift Registers Shift registers can be used to delay a digital signal by a predetermined amount. An 8-bit serial in/serial out shift register has a 40 MHz clock. What is the total delay through the register? The delay for each clock is 1/40 MHz = 25 ns The total delay is 8 x 25 ns = 200 ns Data in LK Data in 25 ns LK 40 MHz A B SRG 8 Q 7 Q 7 Data out Data out t d = 200 ns Slide 13
Shift Registers Shift Register Applications A UART (Universal Asynchronous Receiver Transmitter) is a serial-toparallel converter and a parallel to serial converter. UARTs are commonly used in small systems where one device must communicate with another. Parallel data is converted to asynchronous serial form and transmitted. The serial data format is: LK Transmitter shift register Serial data out Transmitter data register Data bus Buffers LK Receiver data register Receiver shift register Serial data in Start Bit (0) D 7 D 6 D 5 D 4 D 3 D 2 D 1 D Stop Bits (1) 0 t Slide 14
Shift Register ounters Shift Registers Inputs Outputs D LK Q Q omments 1 1 0 SET 0 0 1 RESET Shift registers can form useful counters by recirculating a pattern of 0 s and 1 s. Two important shift register counters are the Johnson counter and the ring counter. The Johnson counter is useful when you need a sequence that changes by only one bit at a time but it has a limited number of states (2n, where n = number of stages). FF0 FF1 FF2 FF3 D 0 Q 0 D 1 Q 1 D 2 Q 2 D 3 Q 3 Q 3 Q 3 LK The Johnson counter can be made with a series of D flip-flops Slide 15
Johnson ounter Shift Registers Inputs Outputs J K LK Q Q omments 0 0 Q 0 Q 0 No change 0 1 0 1 RESET 1 0 1 0 SET 1 1 Toggle Q 0 Q 0 LK J 0 Q 0 J 1 Q 1 J 2 Q 2 J 3 FF0 FF1 FF2 FF3 Q K 0 Q 0 K 1 Q 1 K 2 Q 2 K 3 Q 3 or with a series of J-K flip flops. Here Q 3 and Q 3 are fed back to the J and K inputs with a twist. Q 3 Q 3 3 LK Q 0 Q 1 Q 2 Q 3 0 0 0 0 0 1 1 0 0 0 2 1 1 0 0 3 1 1 1 0 4 1 1 1 1 5 0 1 1 1 6 0 0 1 1 7 0 0 0 1 Slide 16
Ring ounter Shift Registers The ring counter can also be implemented with either D flip-flops or J-K flip-flops. Here is a 4-bit ring counter constructed from a series of D flip-flops. Notice the feedback. LK FF0 FF1 FF2 FF3 D 0 Q 0 D 1 Q 1 D 2 D 3 Q 2 Q 3 Q 3 Like the Johnson counter, it can also be implemented with J-K flip flops. J 0 Q 0 J 1 Q 1 J 2 Q 2 J 3 FF0 FF1 FF2 FF3 Q K 0 Q 0 K 1 Q 1 K 2 Q 2 K 3 Q 3 Q 3 Q 3 3 LK Slide 17
FF1 Q Shift Registers Ring ounter Redrawing the Ring counter (without the clock shown) FF0 shows why it is a ring. J 0 Q 0 The disadvantage to this counter is that it must be preloaded with the desired pattern (usually a single 0 or 1) and it has states number (n, where n = number of flip-flops. 3 FF3 J 3 Q 3 3 K3 Q 3 Q K 0 Q 0 K 1 Q 1 J 1 Q 1 On the other hand, it has the advantage of being self-decoding with a unique output for each state. 2 F F K 2 Q2 J 2 Q2 Slide 18
Ring ounter Shift Registers A common pattern for a ring counter is to load it with a single 1 or a single 0. The waveforms shown here are for an 8-bit ring counter with a single 1. LK 1 2 3 4 5 6 7 8 9 10 Q 0 Q 1 Q 2 Q 3 Q 4 Q 5 Q 6 Q 7 Slide 19
Shift Registers Basic Shift Register Operations A shift register is an arrangement of flip-flops with important applications in storage and movement of data. Some basic data movements are illustrated here. Data in Data in Data out Data out Data in Data out Serial in/shift right/serial out Serial in/shift left/serial out Parallel in/serial out Data in Data in Data out Data out Serial in/parallel out Parallel in/parallel out Rotate right Rotate left Slide 20
Application: Traffic Light ontroller Slide 21
Application: Traffic Light ontroller Slide 22