Sequential Logic Analysis and Synthesis Joseph Cavahagh Santa Clara University r & Francis TaylonSi Francis Group, Boca.Raton London New York \ CRC is an imprint of the Taylor & Francis Group, an informa business
CONTENTS Preface xi Chapter 1 Review of Combinational Logic 1 1.1 Number Systems 2 1.1.1 Binary Number System 3 1.1.2 Octal Number System 4 1.1.3 Decimal Number System 4 1.1.4 Hexadecimal Number System 5 1.2 Number Representations 8 1.2.1 Sign Magnitude 8 1.2.2 Diminished-Radix Complement 9 1.2.3 Radix Complement 10 1.3 Boolean Algebra 12 1.4 Minimization Techniques 18 1.4.1 Algebraic Minimization 19 1.4.2 Karnaugh Maps 20 1.4.3 Quine-McCluskey Algorithm 28 1.5 Logic Symbols 35 1.6 Analysis of Combinational Logic 37 1.7 Synthesis of Combinational Logic 42 1.8 Multiplexers 45 1.9 Decoders 47 1.10 Encoders 53. 1.11 Comparators 54 1.12 Storage Elements 56 1.12.1 SR Latch 57 1.12.2 D Flip-Flop 57 1.12.3 JK Flip-Flop 59 1.12.4 T Flip-Flop 60 1.13 Programmable Logic Devices 61 1.13.1 Programmable Read-Only Memories 61 1.13.2 Programmable Array Logic 64 1.13.3 Programmable Logic Array 67 1.14 Problems 69 Chapter 2 Analysis of Synchronous Sequential Machines 77 2.1 Sequential Circuits 78 2.1.1 Machine Alphabets 79 2.1.2 Formal Definition of a Synchronous Sequential Machine 82 '
viii Contents 2.2 Classes of Sequential Machines 89 2.2.1 Combinational Logic 89 2.2.2 Registers 93.,;. 5. 2.2.3 Counters 98 2.2.4 Moore Machines 105 2.2.5 Mealy Machines 110 2.2.6 Asynchronous Sequential Machines 121 2.2.7 Additional Definitions for Synchronous Sequential. Machines 123 2.3 Methods of Analysis 136 2.3.1. Next-State Table 136 2.3.2 Present-State Map 137 2.3.3 Next-State Map 137 2.3.4 Input Map 138 2.3.5 Output Map 140;,. -. 2.3.6 Timing Diagram 141.. 2.3.7 State Diagram 143 2.3.8 Analysis Examples 146 2.4 Complete and Incomplete Synchronous Sequential Machines 161 2.4.1 Complete Synchronous Sequential,Machines 161 2.4.2 Incomplete Synchronous Sequential Machines 162 2.5 Problems 166.. Chapter 3 Synthesis of Synchronous Sequential Machines 1181 3.1 Synthesis Procedure 182 3.1.1 Equivalent States 183 3.2 Synchronous Registers 197 3.2.1 Parallel-In, Parallel-Out Registers 197 3.2.2 Parallel-In, Serial-Out Registers 201 3.2.3'- Serial-Iri, Parallel-Out Registers 205 3.2.4 Serial-In^ Serial-Out Registers 208 3.2.5 Linear Feedback Shift Registers 212 3.2.6 Combinational Shifter 218 ' 3.3 Synchronous Counters 223 3.3.1 Modulo-8 Counter 223 3.3.2 Modulo-10 Counter234 ;, " V-.-,' 3.3.3 Johnson Counter 245 3.3.4 Binary-to-Gray Code Converter 248 3.4 Moore Machines 254,..-. : ; 3.5. Mealy Machines 277., : 3.6 Moore-Mealy Equivalence 298 b.. : 3.6.1 Mealy-to-Moore Transformation 298 3.6.2 Moore-to-Mealy Transformation 307 3.7 Output Glitches 307
Contents ix 3.7.1 Glitch Elimination Using State Code Assignment 312 3.7.2 Glitch Elimination Using Storage Elements 319 ' 3.7.3 Glitch Elimination Using Complemented Clock 323 3.7.4 Glitch Elimination Using Delayed Clock 326 3.7.5 Glitches and Output Maps 333 -...- 3.7.6 Compendium of Output Glitches 339 3.8 Problems 344 Chapter 4 Synthesis of Synchronous Sequential Machines 2 361 4.1 Multiplexers for 8 Next-State Logic 361 4.1.1 Linear-Select Multiplexers 363 4.1.2 Nonlinear-Select Multiplexers 377 4.2 Decoders for 1 Output Logic 400 4.3 Programmable Logic Devices 412 4.3.1 Programmable Read-Only Memory 413 4.3.2 Programmable Array Logic 421,' '..,.,.4.3.3 Programmable Logic Array 432.,.' 4-3.4 Field-Programmable Gate Array 437 > 4.4 > a Microprocessor-Controlled Sequential Machines 448, r..., 4.4..1 General Considerations 449,....,- 4.4.2 Mealy Machine Synthesis 453.-,. 4.4.3 Machine State Augmentation 461, 4.4.4 Moore and Mealy Outputs 466 4.4.5 System Architecture 467 4.4.6 Multiple Machines 477 4.5 Sequential Iterative Machines 481 4.6 Error Detection in Synchronous Sequential Machines 489 : ' : 4:7-"' Problems 500 ' " : - ' ; Chapter 5 Analysis of Asynchronous Sequential Machines 519 5.1 Introduction 520. 5.2 Fundamental-Mode Model 522 5.3.Methods of Analysis 526 5.4. ; Hazards 553 :. 5.4.1 Static Hazards 553.. 5.4.2 Dynamic Hazards 568 5.4.3 Essential Hazards 572 5.4.4 Multiple-Order Hazards 577 5.5 Oscillations 578 >,.,.., :,. 5.6 Races 582 ' ''''' ' ' 5.6.1 Noncritical Races 583, 5.6.2 Cycles 586
Contents 5.6.3 Critical Races 586 5.7 Problems 590 Chapter 6 Synthesis of Asynchronous Sequential Machines 607. 6.1 Introduction 608 6.2 Synthesis Procedure 610 6.2.1 State Diagram 612 6.2.2 Primitive Flow Table 616 6.2.3 Equivalent States 632 6.2.4 Merger Diagram 645 6.2.5 Merged Flow Table 656 6.2.6 Excitation' Maps and Equations 661 6.2.7 Output Maps and Equations 691 6.2.8 Logic Diagram 710 6.3 Synthesis Examples 716 6.3.1 Mealy Machine with Two Inputs and One Output 716 6.3.2 Mealy Machine with Two Inputs and One Output Using a Programmable Logic Array (PLA) 727 6.3.3 Moore Machine with One Input and One Output 735 6.3.4 Mealy Machine with Two Inputs and Two Outputs 741 6.3.5 Mealy Machine with Three Inputs and One Output 755 6.3.6 Mealy Machine with Two Inputs and Two Outputs 765 6.4 Problems 777 ' Chapter 7 Pulse-Mode Asynchronous Sequential Machines 807 7.1 Analysis Procedure 809 7.1.1 57? Latches as Storage Elements 810 7.1.2 57? Latches with D Flip-Flops as Storage Elements 817 7.2 Synthesis Procedure 823 7.2.1 SR Latches as Storage Elements 823 7.2.2 TFlip-Flops as Storage Elements 830 7.2.3 57?-r Flip-Flops as Storage Elements 836 7.2.4 57? Latches with D Flip-Flops as Storage Elements 844 7.3 Problems 850 Appendix Answers to Selected Problems 861 Index 889