Introduction to Sequential ogic Circuits (Class 8.1 10/16/12) CSE 2441 Introduction to igital ogic Fall 2012 Instructor Bill Carroll, Professor of CSE
Sequential circuit models Block diagram State diagrams and state tables Finite state machines (FSM) Types of sequential circuits Synchronous (clocked) Asynchronous Memory elements atches Flip-flops Registers and shift registers Generic devices Standard 7400-series devices Today s Topics
The Sequential Circuit Model (x 1,,x n ) Input (z 1,,z m ) Output (y 1,,y r ) Present State (state) (Y 1,,Y r ) Next State Figure 6.1 z i = g(x 1,,x n,y 1,,y r ) for i = 1,,m Yi = g(x 1,,x n,y 1,,y r ) for i = 1,,r
Types of Sequential Circuits Synchronous (clocked) circuits Asynchronous will not cover in CSE 2441 Pulse mode Fundamental mode
State Tables and State iagrams (Synchronous Circuits) Present state Input x Next state Present state y x/z Y Input/output y Y/z (a) (b) Next state/output Figure 6.2
Sequential Circuit Example (Finite State Machine Model) 0/1 A B Present state A B C (a) 1/1 (b) 0 1 0/1 0/0 1/0 1/0 0/0 1/1 x/z Input x /0 B/1 C/1 A/0 C/1 A/0 /0 B/1 Figure 6.3 C Given Input sequence x = 0110101100 Starting state A The machine behaves as follows t 0 1 2 3 4 5 6 7 8 9 10 x 0 1 1 0 1 0 1 1 0 0 y A B A B B A C C C Y B A B B A C C C z 0 1 0 0 1 1 0 1 1 1 Response Output sequence z = 0100110111 Final state C
Realization Using Flip-Flops
Synchronous Sequential Circuits x 1 x n... Combinational logic... z 1 z m y 1... y r... Y r Y 1 Memory Clock State changes occur in synchronization with the clock signal Typical memory devices flip-flops, JK flip-flops
Types of Memory Elements Synchronous circuits flip-flop JK flip-flop SR flip-flop T flip-flop Asynchronous circuits elay line (propagation delay) SR latch latch
Set-Reset (SR) atch Basic bistable, unclocked memory element Uses -- Memory in asynchronous circuits, component in clocked flip-flops Characteristic Equation Q* = S + R Q
Basic Clock Signal Terminology Positive edge Negative edge -Clock period- Positive edge low to high transitions Negative edge high to low transitions Clock period (t c ) time between two positive edges. Clock cycle same as clock period. uty cycle -- % of cycle that is in a high state (50% in above case) Clock frequency 1/t c
SN7474 ual Positive Edge-Triggered Flip-Flop Figure 6.23 Characteristic equation Q* = Figure 6.28
SN7476 ual Pulse-Triggered JK Flip-Flop Figure 6.25 Characteristic equation Q* = K Q + JQ Figure 6.27
Generic Shift Register Parallel in (Y) Parallel out (X) Serial in n-bit shift register Serial out (a) Preset control Shift pulse control Parallel in (Y) Parallel out (X) n-bit shift register Serial out Serial in n-bit shift register Preset control Shift pulse Shift pulse (b) control (c) control
SN74491A Serial-in, Serial-out Shift Register (12) A B (11) (9) Clock (a) (13) (14) Q Q NC 1 14 Q Inputs at t n Outputs at t n + 8 A B Q Q t n + 8 = Bit time after 8 low-to-high clock transitions t n = Reference bit time, clock low (b) NC NC NC V CC NC NC 2 3 4 5 6 7 13 12 11 10 9 8 Q A B GN Clock NC (c)
SN74164 Serial-in, Serial/Parallel-out Shift Register
SN74164 Function Table and Package A 1 14 VCC Inputs Outputs B 2 13 Q Clock A B QA QB É Q QA0 QB0 QAn QAn QAn Q0 QGn QGn QGn Q A QB QC 3 4 5 12 11 10 QG QF QE QA0, QB0, Q0 = levels of QA, QB, Q, respectively, before the indicated steady-state input conditions are established. QAn, QGn = levels of QA, QG, respectively, before the most recent transition of the clock (1-bit shift) Q GN 6 7 9 8 Clock (c) (d)
SN7496 5-bit Serial-in, Serial-out Shift Register Preset (8) enable Preset A (2) Output QA Preset Preset Preset Preset B C E (15) (3) Output QB (14) (4) Output QC (13) (6) Output Q (11) (7) Output QE (Serial output) (10) Serial input (9) Preset Preset Preset Preset Preset Clock (16) (1) (a) Presets Clock Serial input Preset enable A B C E QA QB Outputs QC Q QE Shift (b) Preset Shift
SN7496 Function Table and Package ayout Inputs Outputs Preset Enable A B Preset C E Clock Serial QA QB QC Q QE QA0 QA0 QB0 QB0 QB0 QAn QAn QC0 QC0 QBn QBn Q0 Q0 Q0 QCn QCn QE0 QE0 QA0, QB0, etc. = levels of QA, QB, etc., respectively, before the indicated steady-state input conditions are established. QAn, QBn, etc. = levels of QA, QB, etc., respectively, before the most recent transition of the clock. (c) Qn Qn Clock 1 16 CEAR A 2 15 QA B 3 14 QB C 4 13 QC VCC 5 12 GN 6 11 Q E 7 10 QE PRESET 8 9 SERIA (d)
SN74165 8-bit Serial/Parallel-In, Serial-out Shift register Inputs Internal outputs Output Parallel Clock Serial Clock inhibit a...h A... a QA0 QA0 b QB0 QAn QAn QB0 h Q0 QGn QGn Q0 Q QB QA Shift/ load (a) A Parallel inputs Shift/oad Clock inhibit Clock (10) Serial (11) S (1) (2) R B (12) S R C (13) S R (14) S R E (3) S R F (4) S R G (5) S R (6) S R (15) Q Q (9) (7) A Shift/oad Clock inhibit Clock (10) Serial (11) S (1) (2) R (15) (b) (c)
SN74165 Timing iagram Clock Clock inhibit Serial input Shift/load ata A B C E F G Output Q Output Q Serial shift oad Inhibit (d)
Serial Adder Unit Carry delay Q X C CR n-bit shift register ci-1 ci n-bit shift register xi yi FA Full adder si n-bit shift register Z Preset Shift Y
Serial Accumulator Preset X Q 0 n-bit shift register CR Shift ci FA si n-bit shift register Serial out Z (a)
Parallel Accumulator xn x2 x1... FA FA A Q Q Q CR... CR CR... Accumulate zn+1 zn z2 (b) z1