Researh Journal of pplied Sienes, Engineering and Tehnology 5(10): 2957-2963, 2013 ISSN: 2040-7459; e-issn: 2040-7467 Maxwell Sientifi Organization, 2013 Submitted: September 15, 2012 epted: Otober 31, 2012 Published: Marh 25, 2013 Designs and Implementations of Low-Leakage Digital Standard Cells ased on Gate- Length iasing Jindan Chen and Jianping Hu Institute of Ciruits and System, Ningbo University, Ningbo 315211, China bstrat: In this study, a minimum set of low-power digital standard ells for low-leakage appliations are developed and introdued into SMIC (Semiondutor Manufaturing International Corporation) 130 nm CMOS libraries, whih inlude basi logi gates suh as inverter, NND, NOR,, XNOR and flip-flop. The inverter, NND, NOR and flip-flop standard ells based on the gate-length biasing tehnique are proposed to ahieve low Energy Delay Produt (EDP). The and XNOR standard ells are optimized based on transistor-level. ll iruits are simulated with HSPICE at a SMIC 130nm CMOS tehnology by a 1.2V supply voltage. The proposed several standard ells attain large leakage redutions. mode-10 ounter is verified with the proposed standard ells by using ommerial ED tools. The leakage and total dynami power dissipations of the mode-10 ounter using the proposed standard ells provide a redution of 21.27 and 3.06%, respetively. The results indiate the proposed standard ells are a good hoose in low leakage appliations. Keywords: Digital standard ells, gate-length biasing tehniques integrated iruits, low-leakage designs INTRODUCTION Tehnology saling inreases the density and performane of integrated iruits, resulting in large power dissipations. With the growing uses of portable and wireless eletroni systems, energy-effiient designs have beome more and more important in VLSI hips (garwal et al., 2004). The total energy onsumption in a CMOS iruit inludes mostly two omponents: swithing energy due to harging and disharging for loads and stati energy dissipation that is aused by leakage urrents of MOS devies. efore the CMOS proess is saled into deep sub-miro proess, dynami energy loss has always dominated power onsumption, while leakage dissipation is little. The aggressive saling of devie dimensions and threshold voltage has signifiantly inreased leakage urrent exponentially, whih attrats extensive attentions. There are several leakage soures in nanometer CMOS proesses: sub-threshold leakage urrent, gate leakage urrent and band-to-band tunneling leakage urrent. In three leakage soures, the sub-threshold leakage is the dominant ontributor to total leakage at 130 nm and is foreast to remain so in the future, beause it inreases exponentially with threshold voltage (V th ) (Fallah and Pedram, 2005). Many leakage redution tehniques have been proposed reently at various design levels, suh as MTCMOS (Multi- Threshold CMOS) power-gating tehnique (Kao and Chandrakasan, 2001), DTCMOS (Dual Threshold CMOS) (Zhang et al., 2011), VTCMOS (Variable Threshold CMOS) (Peiravi and ssai, 2008) and GL (Gate-Length iasing) (Gupta et al., 2006) have been proposed in reent years and ahieved onsiderable energy savings. Low power, high speed and small area are three main objetives in IC design. Today s advaned designs require a areful balaning of many ompeting hallenges. PDP (Energy Delay Produt) metri provides a good ompromise between speed and delay, whih is written as: EDP = E (1) t delay Cell-based design flow has been widely used for digital hip designs with ommerial ED tools. In order to realize a low-power hip, standard ell libraries and IP (Intelletual Property) ores should be onstruted with low-power design tehniques. Many power redution tehniques have been proposed for standard ell libraries. Semiustom design methodologies were proposed with MTCMOS powergating standard ells (Kim and Shin, 2007. The authors presented low-leakage standard ell based SIC design methodologies for both stati CMOS and domino logi (Jayakumar and Khatri, 2007). The transistor-level DTCMOS was also used for low-leakage standard ells (Nagarajan et al., 2009). For a typial tehnology with a sub-threshold slope of 100mV/deade, eah 100mv redution in V th will ause an order of magnitude inrease in leakage urrents (Wang et al., 2006). In short hannel devies, with Corresponding uthor: Jianping Hu, Institute of Ciruits and System, Ningbo University, Ningbo 315211, China 2957
inreasing of the gate length, the threshold voltage inreases, so that the leakage dereases exponentially and delay inreases linearly. The Gate-Length iasing (GL) tehnology inreases the hannel length of transistors to alter the threshold voltage and redues leakage exponentially in both ative and standby modes, while delay inreases only linearly with the inreasing of the gate length (Hu and Wang, 2011). It is reported that small biases in hannel length of transistor an afford signifiant leakage savings with small performane impat (Heo and Shin, 2007). In this study, a minimum set of low-leakage digital standard ells are developed, whih inlude basi logi gates suh as inverter, NND, NOR,, XNOR and low-leakage power flip-flop. These standard ells are optimized to ahieve low Energy Delay Produt (EDP). The layout design, abstrat and standard-ell haraters of these standard ells are also desribed. In order to show energy effiieny of the proposed standard ells, a mode-10 ounter is verified with the proposed standard ells by using ommerial ED tools. The results indiate the proposed standard ells are a good hoose in low power design. LOW-POWER DESIGNS OF THE MINIMUM SET OF STNDRD CELLS asi logi gate ells with gate-length biasing: The basi gates suh as inverter, NND and NOR are important elements in digital iruits, sine they are largely used. However, basi logi gate standard ells used in most urrent CMOS proesses suh as SMIC 130 nm are mostly based on standard CMOS logi. We inrease the gate-length of basi logi gates inluding inverter, NND and NOR from 130 nm to 250 nm by 10 nm step. HSPICE simulations are arried out for the basi standard ells with Gate-Length iasing tehnology. The leakage dissipation and delay of the inverter are shown in Fig. 1. With inreasing of the gate length, the leakage power dereases exponentially and delay inreases linearly. Therefore, it is possible that the best EDP is ahieved by using hannel length biasing tehnology. The EDP of the inverter, NND and NOR ells are shown in Fig. 2. The results show that the basi standard ells with the GL tehnology have lower EDP than the SMIC one with the standard gate-length. The inverter, NND and NOR ells have the best EDP when their gate length is 0.18, 0.19 and 0.20 um, respetively. The inverter ell provides an EDP redution of 23.7%, thought its delay is slightly larger than the SMIC one. verage delay (ps) Fig. 1: Leakage power dissipation and delay of the inverter standard ell EDP (yws) 160 140 120 100 80 60 40 20 8000 7000 6000 5000 4000 3000 Fig. 2: EDP of the inverter, NND and NOR standard ells Leakage power verage delay 0.13 0.17 0.19 0.21 0.23 0.25 Gate length (um) Inverted NND NOR (a) iruit of the SMIC 160 140 120 100 0.13 0.17 0.19 0.21 0.23 0.25 Gate length (um) 80 60 40 20 Leakage power (pw) Low power and N iruits: In ommerial standard-ell library suh as the SMIC, the iruit is typially realized based on a TG logi struture with 12 transistors, as shown in Fig. 3a. The and XNOR strutures with 10 transistors used in this study are shown in Fig. 3b (Wang and Hu, 2011). eause of 2958 (b) and XNOR strutures used in this work Fig. 3: and XNOR iruits for the SMIC 130nm standard-ell library
Table 1: EDP omparisons of two standard-ells Cells Energy loss per swithing (fj) Propagation delay (ps) EDP (pjs) SMIC 41.28 78.3 3.232224 The proposed 26.96 89.1 2.402136 Table 2: Leakage power of three flip-flop ells (nw) DFFQX1 TGMS TGMS-GL 1.13 0.99 0.92 D n CK n 0.64/0.14 0.42/0.14 n 0.42/0.14 0.38 n n 0.64/0.14 0.26 0.18 Fig. 4: Flip-flop standard ell based on Transmission Gate Master-Slave Struture with Gate-Length iasing (TGMS-GL) Q in the TGMS flip-flop is inreased to 140nm (TGMS- GL). HSPICE simulations have been arried out for the three flip-flops ells (DFFQX1, TGMS and TGMS- GL). The power dissipations of the proposed flip-flop ell have been omprised with the other two ones, as shown in Fig. 5. Figure 5 show that the low-leakage flip-flop ell with GL has lower energy onsumption than the SMIC one. Compared with the SMIC standard ell, the lowleakage flip-flop ell has 19% energy saves. The leakage dissipations of the three flip-flop standard ells are shown in Table 2. TGMS-GL attains a power reduing of 19% ompared with the DFFQX1. LYOUT DESIGNING ND POST-LYOUT SIMULTIONS asi logi gate ells using GL: The layout of the proposed basi logi gate standard ells is shown in Fig. 6, whih inlude inverter, neither NND, NOR, and XNOR with GL. The metal lines are plaed horizontally at the top and the bottom for the power supply (VDD) and ground (VSS). ll of the layout heights of the standard ells are 3.69um that is the same as 130nm SMIC ones. The leakage power dissipations of the two inverter standard ells are shown in Table 3 by using post-layout simulations. The inverter ell with GL tehnology (INVX1_R) has a leakage redution of 41.61%, ompared with SMIC one (INVX1_SMIC13). The leakage power of NND and NOR standard ells are shown in Table 4. In Table 4, Fig. 5: Power dissipations of the three flip-flop ells their simple strutures, it is expeted that they have lower power than the SMIC 130nm one. The energy delay produt of the two ells is shown in Table 1. The results show that the has lower EDP than the SMIC one. The has 53% energy saves and provides an EDP redution of 34%, although its delay is slightly larger than the SMIC one. Low-leakage flip-flop with gate-length biasing: flip-flop is important element in digital iruits. The C 2 MOS flip-flop (DFFQX1) is used in the SMIC 130 nm standard-ell library. low-leakage power flip-flop standard ell based on Transmission Gate Master-Slave struture (TGMS) with GL tehnology is used to ahieve low energy delay produt in this study, as shown in Fig. 4 (Hu and Wang, 2011). The gate-length 2959 Table 3: Leakage power of inverter standard ell using post-layout simulations (pw) Input 0 1 verage INVX1_R 62.75 48.82 55.78 INVX1_SMIC13 71.52 96.31 83.91 Table 4: Leakage power of NND and NOR standard ells using post-layout simulations (pw) Input 00 01 10 11 verage NND2X1_SMIC13 31.65 112.51 129.83 132.47 101.61 NND2X1_R 22.40 64.95 71.19 78.75 59.32 NOR2X1_SMIC13 242.92 87.31 107.48 21.55 114.81 NOR2X1_R 131.24 48.9 48.29 20.34 62.19 Table 5: EDP omparisons of two standard ells using postlayout simulations Cell Energy loss per Delay (ps) EDP (pjs) swithing (fj) SMIC 60.08 99.9 6 The proposed 36.12 130 4.69 Table 6: The leakage power of two ells using post-layout simulations (pw) Cell = 10 = 00 = 01 = 11 verage SMIC 641.14 701.11 841.75 563.23 686.8075 The proposed 587.11 550.12 734.52 630.01 625.44
NND2X1_SMIC13, NOR2X1_SMIC13 are 130nm SMIC NND and NOR ells, respetively and NND2X1_R, NOR2X1_R are the proposed NND and NOR ells with the GL tehnology, respetively. Compared with the 130nm SMIC standard ells, the leakage power of the proposed NND and NOR ells with the GL tehnology are redued greatly. The EDP of the SIMC and proposed ells is ompared in Table 5 by using post-layout simulations. The results show that the proposed ell is better optimized than the SMIC one. The leakage power dissipations of the SIMC and proposed ell are shown in Table 6. The leakage of the proposed standard ell is lower than SMIC one expet for the state of = 11. Fig. 9: EDP omparisons of the three flip-flop ells using post-layout simulations Figure 7 shows the energy onsumption omparisons of the ells per swithing from 10MHz to 300MHz. The proposed ell performs lower energy onsumption than the SMIC one in all operation frequenies. Fig. 6: The layouts of the proposed basi logi gate standard ells for SMIC 130 nm Energy loss per swithing (fj) 60 50 40 30 20 10 SMIC Proposed 0 10 20 50 100 150 200 250 300 500 Operation frequeny (MHz) Fig. 7: Energy onsumption omparisons of the two ells using post-layout simulations Fig. 8: The layout of TGMS-GL Gate-length biasing flip-flop: The layout of the lowleakage flip-flop ell with GL is shown in Fig. 8. The metal lines are plaed horizontally at the top and the bottom for the power supply (VDD) and ground (VSS). The proposed low-leakage flip-flop with GL (TGMS- GL), Transmission Gate Master-Slave flip-flop without GL (TGMS) and SMIC flip-flop (DFFQX1) have the same layout areas with 6.9µm 3.69µm. The Energy Delay Produt (EDP) of the three flipflop ells are shown in Fig. 9 by using post-layout simulations. The results show that the low-leakage flipflop ell with GL has lower EDP than the SMIC one. Compared with the SMIC standard ell, the low-leakage flip-flop ell provides an EDP redution of 11.6%. STNDRD CELL DESIGNS In this setion, the design flow of the standard ells is presented. Taken an example, the standard-ell generation for the low-leakage flip-flop with GL (TGMS-GL) is presented in detail. The standard-ell design flow is shown in Fig. 10. The GDS database is generated by using the stream out funtion of IC5141. Then, the auto plae and route (P&R) library is reated using this GDS database. The layouts of the standard ells are verified by using the Calibre tool and spie netlists are generated from their layouts. The synthesis library is generated by using the liberty NCX and HSPICE. fter the layout design, the abstrat view should be reated in Library Exhange Format (LEF) for standard 2960
Stream out (*.gds) Layout P&R lib(*.lef) Library design bstrat Generator Verilog module ( *.v) Spie netlist Synopsys lib ( *.lib) Calibre xrc NCX&HSPICE Synthesis lib ( *.db) Library ompile set input_library../typial_1v225.lib set output_library typial_1v225_out.lib set model_file../model.typ set netlist_dir../netlists set simulator_exe ~/hspie/linux/hspie set templates true set output_templates true set input_template_dir onfig set timing true set power true set s_power false set ompat false set s_timing false set nlpm true set nldm true set variation_leakage false s e t Standard ell library Fig. 10: Design flow of the standard ells MCRO TGMS_GL CLSS CORE ; FOREIGN TGMS 0 0 ; ORIGIN 0.0000 0.0000 ; SIZE 6.9000 Y 3.6900 ; SYMMETRY X Y ; SITE SMC13SITE ; PIN CK DIRECTION INPUT ; USE CLOCK ; PORT LYER METL1 ; RECT 3.345 1.700 3.555 1.990; CK PIN D DIRECTION INPUT ; D PIN Q DIRECTION OUTPUT ; Q PIN VDD DIRECTION INOUT ; USE POWER ; VDD PIN VSS DIRECTION INOUT ; USE GROUND ; VSS TGMS_GL Fig. 11: LEF teh files of the low-leakage flip-flop standard ell ells. The generated abstrats are based on physial layout and logial data, proess tehnology information. It is used in plae of full layouts to improve the performane of plae-and-route tools, suh as Cadene Enounter. The LEF (Library Exhange Format) teh file an be read by the plae-and-route tools. Therefore, LEF teh files should be generated for standard ells. The LEF teh file of the flip-flop standard ell is show in Fig. 11. From the LEF file, we an see that all the all Pins are abstrated. In the LEF file, the size of the flip-flop ell is defined as 6.9 µm 3.69 µm. To perform haraterization, Liberty NCX is used to run iruit Fig. 12: Template files of the liberty NCX simulations for the library ells to determine the ell behavior. It writes out a desription of the ell harateristis in the Liberty format (.lib). The library an then be used for timing, power and noise analysis with various tools suh as Design Compile and Prime Time. In addition, Liberty NCX an onvert existing libraries from one format to another. For a haraterization task, the template file must speify the SPICE model file name, the SPICE net list diretory and the SPICE simulator exeutable, as shown in Fig. 12. The input and output library names should be also speified. fter the haraterization, we an get a library in the liberty format (.lib) that an be used for timing and power analysis with various tools suh as Design Compile. We an use the Library Compile tool from Synopsys apture this liberty (.lib) file and translates them into Synopsys internal database (.db) format for synthesis. MODE-10 COUNTER USING THE PROPOSED STNDRD CELLS In order to estimate power information, a mode-10 ounter is synthesized by using Design Compile. Figure 13 and 14 show the two synthesis results by using the SMIC 130 nm standard ells and the proposed standard ells, respetively. s shown in Fig. 13 and 14, the area of the two results is the same and the leakage power and the total dynami power of the mode-10 ounter using the proposed standard ells provide a redution of 21.27 and 3.06%, respetively. lthough the dynami power dissipation of the proposed standard ells only has a little redution, they an ahieve large total power savings beause of their low leakages. 2961
Fig. 13: Design ompile synthesis results of the mode-10 ounter using the SMIC 130nm standard ells Fig. 14: design ompile synthesis results of the mode-10 ounter using the proposed standard ells 2962
CONCLUSION Tehnology saling inreases the density and performane of integrated iruits, resulting in large power dissipations. Cell-based design flow has been widely used for digital hip designs with ommerial ED tools. In order to realize a low-power hip, lowpower standard ell libraries are important. In this study, a minimum set of low-power standard ells have been developed, whih inlude basi logi gates suh as inverter, NND, NOR,, XNOR and flip-flop. The proposed inverter, NND, NOR and flipflop standard ells are optimized to ahieve low energy delay produt (EDP) by using the gate-length biasing tehnique. The proposed and XNOR standard ells are optimized based on transistor-level. The proposed several standard ells attain large leakage redutions. mode-10 ounter is verified with the proposed standard ells by using ommerial ED tools. The leakage and total dynami power dissipations of the mode-10 ounter using the proposed standard ells provide a redution of 21.27 and 3.06%, respetively. The results indiate the proposed standard ells are a good hoose in low power design. CKNOWLEDGMENT This study was supported by the Key Program of National Natural Siene of China (No. 61131001), National Natural Siene Foundation of China (No. 61271137 and No. 61071049). REFERENCES garwal,., C.H. Kim, S. Mukhopadhyay and K. Roy, 2004. Leakage in nano-sale tehnologies: Mehanisms, impat and design onsiderations. Proeeding of the 41st nnual Design utomation Conferene, CM-IEEE, New York, US, pp: 6-11. Fallah, F. and M. Pedram, 2005. Standby and ative leakage urrent ontrol and minimization in CMOS VLSI iruits. IEICE T. Ele., E88-C(4): 509-519. Gupta, P.,.. Kahn, P. Sharma and D. Sylvester, 2006. Gate-length biasing for runtime-leakage ontrol. IEEE T. Comput. id. D., 25(8): 1475-1485. Heo, S. and Y.S. Shin, 2007. Minimizing leakage of sequential iruits through flip-flop skewing and tehnology mapping. J. Semiondu. Teh. Si., 7(4): 215-220. Hu, J.P. and J. Wang, 2011. Standard ell design of a low-leakage flip-flop with gate-length biasing. IEEE 9th International Conferene on SIC (SICON), 25-28 Ot., Ningbo, China, pp: 361-364. Jayakumar, N. and S.P. Khatri, 2007. preditably low-leakage SIC design style. IEEE T. VLSI Syst., 15(3): 276-285. Kao, J. and. Chandrakasan, 2001. MTCMOS sequential iruits. Proeeding of IEEE European Conferene on Solid State Ciruits, Neuhâtel, pp: 332-335. Kim, H.O. and Y. Shin, 2007. Semiustom design methodology of power gated iruits for low leakage appliations. IEEE T. Ciruit Syst., 54(6): 512-516. Nagarajan, C.S., L. Yuan, G. Qu and.g. Stamps, 2009. Leakage optimization using transistor-level dual threshold voltage ell library. Proeeding of 10th International Symposium On Quality Eletroni Design, Washington DC, US, pp: 62-67. Peiravi,. and M. ssai, 2008. novel iruit design tehnique to minimize sleep mode power onsumption due to leakage power in the sub-100 nm wide gates in CMOS tehnology. World ppl. Si. J., 4: 617-625. Wang, J. and J.P. Hu, 2011. Low power designs of and N standard ells. Let. Note Ele. Eng., 165: 947-954. Wang,.,.H. Calhoun and.p. Chandrakasan, 2006. Sub-Threshold Design for Ultra Low-Power Systems. Springer-Verlag, New York. Zhang, W.Q., L. Su, Y. Zhang, L.F. Li and J.P. Hu, 2011. Low-leakage flip-flops based on dualthreshold and multiple leakages redution tehniques. J. Ciruit Syst. Comput., 20(1): 147-162. 2963