October 11, 2005 Texas Instruments OMAP1510CGZG2 Dual-Core Processor Partial Circuit Analysis Table of Contents Introduction...Page 1 List of Figures...Page 4 Device Summary Sheet...Page 7 Schematics... Tab 1 Symbol and Signal Name Conventions... Tab 2 Signal Cross-Reference List... Tab 3 Report Evaluation... Tab 4 For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. Rev. F4.0
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Texas Instruments OMAP1510CGZG2 Dual-Core Processor Page 4 List of Figures 0.1.1 Package Markings 0.1.2 Package X-Ray 0.1.3 Die Markings 0.1.4a FESEM Image Poly 0.1.4b FESEM Image (High Magnification) Poly 0.2.0 Die Photograph 0.2.1 Annotated Die Photograph 0.2.2 Die Architecture 0.3.1 Buffer 1 Definition 0.3.2 Buffer 2 Definition 0.3.3 Buffer 3 Definition 0.3.4 Buffer 4 Definition 0.3.5 Buffer 5 Definition 0.3.6 DFF 1 Definition 0.3.7 DFF 2 Definition 0.3.8 DFF 3 Definition 0.3.9 DFF 4 Definition 0.3.10 DFF 5 Definition 0.3.11 DFF 6 Definition 0.3.12 DFF 7 Definition 0.3.13 DFF 8 Definition 0.3.14 DFF 9 Definition 0.3.15 Latch1 Definition 0.3.16 Latch2 Definition 0.3.17 Multiplexer 1 Definition 0.3.18 Multiplexer 2 Definition 0.3.19 Multiplexer 3 Definition 0.3.20 Multiplexer 4 Definition 0.3.21 XOR Definition Rev. 4.0 10/11/05 9:40 AM Y:\IRR\Texas_Instruments\OMAP1510CGZG2\CAR-0403-008\Rev_3.0\Report\figlist.doc
Texas Instruments OMAP1510CGZG2 Dual-Core Processor Page 5 2.0.0 Base Oscillator 3.0.0 Clock Selection (Partial) 4.0.0 48MHz APLL 4.1.0 Clock Input 4.2.0 Control Circuit 4.3.0 Phase Detector 4.4.0 Charge Pump 4.5.0 Low-pass Filter 4.6.0 Voltage Control Oscillator 4.7.0 Clock Divider with Output 4.7.1 Signal Drivers 4.7.2 Output Stage 4.8.0 Bias Current Generator 4.9.0 Clock Distribution 5.0.0 Reset Management Circuitry (Partial) 5.1.0 Input Buffer 5.2.0 Partial MPU_RST Input Circuitry 5.3.0 Partial Test Scan Chain Circuitry I 5.4.0 Output Buffer 5.4.1 Level Shifter 5.5.0 Partial RST_OUT Circuitry 5.6.0 Partial Test Circuitry 5.7.0 Partial Test Scan Chain Circuitry II 6.0.0 All-digital PLLs and Clock Management Modules 6.1.0 Input Circuit 6.2.0 Delay Loop Logic 6.3.0 Delay Controller 6.3.1 Delay String Registers 6.3.2 Delay String Decoder 6.3.3 IC Decoder Rev. 4.0 10/11/05 9:40 AM Y:\IRR\Texas_Instruments\OMAP1510CGZG2\CAR-0403-008\Rev_3.0\Report\figlist.doc
Texas Instruments OMAP1510CGZG2 Dual-Core Processor Page 6 6.3.4 IC Registers 6.3.5 Epsilon Controller 6.4.0 Variable Delay Stage 6.4.1 Delay Cell 6.4.2 Delay Line Switch 6.4.3 Variable Delay Line 6.5.0 Commutator 6.6.0 Preset Counter 6.7.0 Phase Detector 6.8.0 Main Clock Controller 6.8.1 Clock Logic I 6.8.2 Clock Logic II 6.8.3 Clock Logic III 6.8.4 Clock Logic IV 6.8.5 Clock Logic V 6.9.0 Clock Management 6.9.1 Clock Processing I 6.9.2 Clock Processing II 6.9.3 Clock Processing III 6.9.4 Clock Processing IV A.1.0 Symbol Conventions A.2.0 Symbol Definitions 1 A.2.1 Symbol Definitions 2 A.3.0 Logic Gate Size Notation A.4.0 Transistor Size Notation A.5.0 Capacitor Size Notation A.6.0 Resistor Size Notation Rev. 4.0 10/11/05 10:52 AM Y:\IRR\Texas_Instruments\OMAP1510CGZG2\CAR-0403-008\Report\figlist.doc
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