Description of the Synchronization and Link Board

Available on CMS information server CMS IN 2005/007 March 8, 2005 Description of the Synchronization and Link Board ECAL and HCAL Interface to the Regional Calorimeter Trigger Version 3.0 (SLB-S) PMC short format - final version N. Almeida, A. Jain, J. C. Silva, J. Varela 1 LIP-Lisbon Abstract This document presents the specifications of the SLB-S daughter board. 1 Also at CERN, Geveva. 1

Introduction This document contains the specifications of the Synchronization and Link Board PMC version 2.0 (SLB-S) used in the ECAL and HCAL detectors of the CMS experiment. The SLB-S is a PMC-like daughter board used in the ECAL TCC (Trigger Concentrator Card) and in the HCAL HTR (HCAL Trigger and Readout Board), which makes the interface to the Regional Calorimeter Trigger. Relative to the previous version (known has SLB-PMC), the SLB-S implements a smaller form factor to fit the needs of the ECAL and HCAL trigger board designs. The board is designed to be used in different detector partitions, where it can be fully (8 Trigger Towers) or partially used. In summary the SLB-S performs the following operations: a) Synchronization of the trigger data (with the granularity of one Trigger Tower) using the Sync-S circuits. b) Serial transmission of the trigger data to the Regional Trigger. This document is organized in two main parts. In the first part, the generic characteristics of the SLB-S board are introduced. In the second part we describe the functionality of the Sync-S circuit which implements the synchronization functions. Detailed technical information is given in annexes. 1. The SLB-S Board The SLB-S board is a custom mezzanine board that uses three 64 pin PMC like connectors to connect with the main board, using LVTTL standard (3V3), and a 14 pin MTD connector for the High Speed link output. Figure 1 shows a block diagram of the SLB-S board. The board consists mainly of two Sync-S circuits, each housed in an EPLD (Altera Cyclone EP1C6), a clock multiplier and a Vitesse Link circuit VSC7126 [7]. Each Sync-S circuit has 4 Sync Core corresponding to 4 Trigger Towers. The SLB-S board controller is embedded in one of the two Sync-S circuits. A low jitter clock multiplier (ICS670-01) is used to generate the 120 MHz clock, synchronised with the Rx_Clk, needed to feed data to the Vitesse circuit. The small dimension of the SLB-S (12,25cm x 3,8cm) allows to have up to 9 SLB-S housed vertically on a 9U format VME board (Figure 2). SYNC SYNC-S EDC mux 4 x 8-Bit Bus 120.24 MHz Clock 4 x 9 Bit Bus 40.08 MHz SYNC SYNC EDC mux 4 x 9 Bit Bus 40.08 MHz PMC connectors SYNC SYNC SYNC SYNC-S EDC mux VITESSE 7216 1.2 GB/s Output Copper Serial Links SYNC EDC mux SYNC Control Interface PMC connectors TTC BUS TTC_rx CLK Local_BUS RX_CLK RX_BCO SLB-S Controller (Embedded ) 120.24 MHz Clock, 15 ps jitter CLOCK Multiplier VITESSE ctrl interface JTAG 2 Figure 1 SLB-S Block Diagram

1.1 Input and Output Data The SLB-S receives data of up to 8 Trigger Towers at 40 MHz on two PMC 64-pin connectors, the minimum partition of the input data being one Trigger Tower. Input per Trigger Tower is 9-bit data, with 8 bits coding the tower transverse energy and 1 bit coding the fine-grain information [6]. The input data is stored on the rising edge of the TX_CLK (TTC_CLK_DES1 on the pinout description). Output data is synchronized using a common external 40 MHz clock, Rx_Clk, and a common bunch crossing zero signal, Rx_BC0. Data from two neighbour towers is arranged in 24-bit frames, after insertion of the Hamming code for error detection and the BC0 synchronization bit. Data frames are multiplexed on a 8-bit bus at 120 MHz and sent to the 4-channel serial link circuit Vitesse. The SLB-S has 4 high-speed differential PECL outputs from the Vitesse circuit. Each Vitesse output channel transmits the information of 2 Trigger Towers. Depending on the SLB-S configuration, a number of these outputs can be enabled or disabled to match the detector geometry. The output pin definitions as well as the bit map of the output words are defined in the CMS Calorimeter Trigger Primitive Generator to Level 1 Regional Trigger Interface documentation [6]. A description of the SLB-S connectors is found in Appendix B. 1.2 SLB-S Control Interfaces Figure 2 The SLB-S board (dual view). The SLB-S has three control interfaces: 1) a programmable communication interface for board configuration and monitoring; 2) an interface to the TTC broadcast commands; 3) Rx_BC0 and Rx_Clk inputs. These interfaces use the third PMC 64-pin connector. 1.2.1 Programmable Communication Interface The SLB-S implements a communication protocol similar to the Motorola interface protocol that mainly uses a Chip Select signal, a Read\Write Flag, a Local Data Bus port and an Address port. The following protocol rules should be used to access the circuit: 1) To read data from the Sync circuit, set the address, set R\W signal on READ ( 1 ), and get data on the Local Bus one clock before the rising edge of the Chip Select (active low). 2) To write data to the Sync circuit, set the address, set R\W signal on WRITE (zero), and data present on the local bus will be stored on the falling edge of the Chip Select signal ( 0 ). 3) When Chip Select is not active, the Local Data Bus port is on tri-state. 4) To access the parameters of each individual Sync circuit an Access Phase is need. A detailed description of the SLB-S communication method is described on Appendix D. 3

1.2.2 TTC Interface The SLB-S receives the TTC Broadcast Bus (plus strobes and clocks). The TTC broadcast commands recognized by the SLB-S (start, stop, BC0, resync) are decoded in the TTC Command Decoder embedded in the Sync-S circuits. 1.2.3 Rx_BC0 and Rx_Clk Inputs The trigger primitive data of all Trigger Towers on both ECAL and HCAL detectors must be sent on the same clock period to the Regional Trigger despite of the relative phase between them when arriving at the trigger boards. The spread in time of the transmitter end should be as close to 0ns as possible. For this task the Sync-S circuits rely on a common pulse, Rx_BC0, strobed by a common clock, Rx_Clk that will enable trigger primitive data to be sent to the RT crates from all the Sync-S circuits in a same clock period. The Rx_BC0 and Rx_Clk are generated and time adjusted on a common board and distributed in differential logic by equal length cables to each trigger board. The Rx_Clk is the clock source of the Vitesse circuit and shall have the smallest possible jitter (Vitesse specifies 100ps jitter pk-pk) as to reduce the BER of the Vitesse link to the minimum. 1. 3 JTAG Port and Board Identification Almost all of the components used on the SLB-S board have JTAG Boundary Scan pins for tests and reprogrammability purposes and are connected on a unique JTAG.4 Board Identification. In total, 1210 SLBs will be produced, including 25% of spare modules. The production is equally distributed by ECAL and HCAL detectors. Each board is identified by a serial number, coded in 11 bits: 5 MSB code the production panel (28 in total), while the 6 LSB code each SLB inside the panel (44 in total). The serial number is printed out in the board and can be retrieved by VME access to an internal register (see Table 5 in Appendix D). 4

2. The Synchronization Circuit (Sync-S) The synchronization of the calorimeter trigger data uses a dedicated circuit, the Sync-S based on the previous Sync Tx/Rx [3,4]. This version of the Sync circuit has been implemented on an ALTERA Cyclone EP1C6 and includes 4 identical Sync Core blocks on a PQFP 240-pin package, each dedicated to the synchronization of one trigger tower. A description of the trigger synchronization method used here is given in [1] and [2]. Sync Core (1 of 4) SYNC TX BLOCK Sync Data Generator Accumulator Threshold SYNC RX BLOCK INPUT DATA BUS: 8-bit Energy + 1-bit FG DATA Tx_Clk Input MUX BIST Sync FIFO EDC Encoder Data Out MUX Tx_BC0 TX Sync Error SYNC CMD Decoder Clr_FIFO Data/Sync Flag Rx_Clk 120.24MHz clock JTAG Communication Interfaces TTC BUS TTC_rx CLK Local_BUS RX_CLK RX_BCO SYNC CONTROLLER (embedded) (status reg., address dec., conf. reg., command reg.,tx_bc0 delays, Vitesse ctrl, etc) Vitesse Control Figure 3 Block diagram of the Sync-S circuit The Sync-S circuit (see figure 3) is composed of 4 Sync Core blocks, the EDC and Output Multiplexer block and the Control block. The Sync Core blocks perform the basic synchronization functions, described in detail in the following sections. The EDC and Output Multiplexer block combines the output of two Sync Core adding Hamming error detection bits and multiplexes the generated 24-bit word into three 8-bit words at 120 MHz using an external clock multiplier, as required by the external Vitesse link. The Control block is responsible to handle the TTC fast commands, to control the external Vitesse links and to provide access to the circuit registers. The circuit is also equipped with JTAG logic implementing boundary scan cells and built-in self-test capabilities. 2.1 Synchronization Core The Sync Core (see figure 3) is divided in two main blocks. The SyncTx block is responsible for flagging the bunch zero data and for the accumulation of the bunch profile histogram. The SyncRx block contains the synchronization FIFO. Both blocks have Sync error counters that monitor the BC0 and clock stability. In the TX block, the Sync Data Generator sends internal synchronization data (counter) during the LHC gaps and the Input Multiplexer switches between real data and synchronization data (synchronously to Tx_BC0 signal). In test mode, the Data Generator is capable of sending out data patterns (counter or fixed pattern). The Accumulator accumulates a histogram of the trigger tower occupancy per bunch crossing (synchronization histogram). The histogram is increment at the current bunch crossing if the input trigger tower energy is above a programmable threshold. In the Rx block, the Synchronization FIFO provides the main synchronization function. Its input is driven by the Tx_Clock (Tx_Clk) and its output by the Rx_Clk. The Sync Command Decoder decodes the internal synchronization data produced by the Tx block to identify the Clear FIFO command. At each orbit gap the FIFO is cleared and the first word written after the gap corresponds to the first active bunch in the orbit. The 5

timing of the Tx_BC0 signal controls the opening of write access in the FIFO. Correspondingly, at FIFO output, the opening of read access is determined by the Rx_BC0 timing. A programmable number of cycles after Tx_BC0, an internal Tx_SOG (Start-Of-Gap) is generated to inhibit FIFO write access, and correspondingly a Rx_SOG signal inhibits read access. Inter-channel synchronization is achieved by careful adjustment of the Tx_BC0 and Rx_BC0 signals: The synchronism between Tx_BC0 and the incoming data is monitored by the Accumulator content, guaranteeing that the histogram gaps are in the expected positions; The Rx_BC0 signal is distributed synchronously to all channels to guarantee that all FIFOs are read at the same time. A summary of the Sync-S blocks and functions is given in Table 1. Block Sync Tx Block Identification of Bunch Crossing 0 Sync Rx Block EDC Encoder Sync Data Generator Input Multiplexer Accumulator Sync Cmd Decoder Synchronization FIFO Output Multiplexer TTC Decoder Control block JTAG/BIST block Generates synchronization/test data Function Switches between real data and synchronization/test data Accumulates the synchronization histogram (1024 positions x 11bits) Data Synchronization Decodes Clear FIFO command Synchronization buffer 128 x 9-bit Encodes the Hamming code bits Multiplexes output data at 120 MHz Decodes TTC commands. Checks synchronization errors. Perform all the control operations; access to registers and FIFOs and readout of the accumulator content. Vitesse link control. Implements boundary scan cells and built-in self-test capabilities Table 1 - List of the main blocks of the Sync-S circuit and its functionality 3. Operation Modes The Sync-S circuit has two Operation Modes: the Synchronization Mode and the Test Mode. The operation mode is common to the eight Sync Core in the two Sync-S of the SLB-S. The operation mode can be programmed differently in the Tx and Rx blocks. A Test Mode in one block can be combined with a Synchronization Mode in the other block. Default is Synchronization mode for both Tx and Rx blocks. 3.1 Synchronization Mode In this section we describe the operation of the Sync Core in synchronization mode. The eight Sync Core of the SLB-S perform the same operations however at different timings. In fact, each Sync Core receives its own Tx_BC0-n signal. The signals Tx_BC0-n are generated by the TTC Command Decoder. Individual programmable adjustment of the Tx_BC0-n timing in the TTC Command Decoder is possible. In the following for simplicity we omit the index n in the signal notation. In Synchronization Mode the following operations are performed: in the Tx block: the Running State is initiated by the Start command: the Tx block starts inputting data at the next Tx_BC0. data is taken from the Tx Input Data Bus and is strobed by the rising edge of the Tx_Clk. 6

the Input Multiplexer is controlled by the TTC Command Decoder. Upon generation of the signal Tx_BC0, the Input Multiplexer is switched to Tx Input Data and the Data/Sync Flag is set to the Data level in the next Tx_Clk period. Upon generation of the Command Tx_SOG (Start Of Gap), the Multiplexer is switched to Synchronization Data and the Data/Sync Flag is set to the Sync level, in the next Tx_Clk period. outside the GAP period and in parallel with the basic data flow the Accumulator operation is enabled. the Running State is finished by the Stop command: the Tx block stops outputting data at the next Tx_SOG and changes to Idle state. in the Rx block: the Running State is initiated by the Start command: the Rx block starts inputting data at the next Data/Sync Flag transition to Data level. at each period, the Tx_Clk strobes the Data and the Data/Sync Flag at the Rx Input Data Bus. If the Data/Sync Flag has the Data level, the Input Data is written in the FIFO. If the Data/Sync Flag has the Sync level, the Input Data is decoded to identify Clear FIFO command and no data is written into the FIFO. Disable FIFO Input is performed when the Flag changes from Data to Sync level, and Enable FIFO Input is performed when the Flag changes from Sync to Data level. the FIFO read access is controlled by the Rx_BC0 signal and is decoupled from the FIFO write access. Upon reception of the Rx_BC0, FIFO Outputs are enabled, so that in the next Rx_Clk period data can be extracted from the FIFO. Upon generation of the command Rx_SOG (internal generation), the FIFO Outputs are disabled, so that in the next Rx_Clk period data can not be extracted from the FIFO and the Output Data Bus is at zero level. While reading data, if the command Clear FIFO is issued the FIFO read access must be disabled and the Output Data Bus put at zero level and read operations will only be processed with the next Rx_BC0. The Rx_Block generates the Data/Sync Output Flag which is synchronous with the bunch crossing zero (last bunch in the gap). The following cycle, the data present in the Output Data Bus must correspond to the first active bunch in the orbit (bunch number 1) The data present on the Output Data Bus must be valid on the rising edge of the Rx_Clk (which must be centered with the data word period). the Running State is finished by the Stop command: the circuit stops sending data (puts zeros ) at the next Rx_SOG and changes to Idle state. 3.2 Test Mode In Test Mode the following operations are performed: Tx block Test Modes: a) Counter Sync Data the test is initiated by the Start command: the Tx block starts sending data at the next Tx_BC0. the Tx block sends the Counter Sync Data generated by the Synchronization Data Generator (the Multiplexer is locked to Synchronization Data); the Tx_BC0 doesn t affect the Multiplexer, but resets the Synchronization Data Generator and sets the Data/Sync Flag to the Data level; the Tx_SOG doesn t affect the Multiplexer, but resets the Synchronization Data Generator and sets the Data/Sync Flag to the Sync level the counter is reset to zero at each Tx_BC0 and Tx_SOG. Between Tx_SOG and Tx_BC0 (gap duration) the Synchronization Data Generator generates Counter Sync Data during the test the Accumulator is active. 7

the test is finished by the Stop command: the Tx block stops sending data at the next Tx_SOG and changes to Idle state. b) Constant Sync Data the test is initiated by the Start command: the Tx block starts sending data at the next Tx_BC0. the Tx block sends the Constant Sync Data generated by the Synchronization Data Generator between Tx_BC0 and Tx_SOG (the Multiplexer is locked to Synchronization Data); the Tx_BC0 doesn t affect the Multiplexer, but resets the Synchronization Data Generator and sets the Data/Sync Flag to the Data level; the Tx_SOG doesn t affect the Multiplexer, but resets the Synchronization Data Generator and sets the Data/Sync Flag to the Sync level between Tx_SOG and Tx_BC0 (gap duration) the Synchronization Data Generator generates Counter Sync Data. during the test the Accumulator is active. the test is finished by the Stop command: the Tx block stops sending data at the next Tx_SOG and changes to Idle state. Rx block Test Modes: FIFO filling - the test is initiated by the Start command: the Rx block starts input data to the FIFO at the next transition of Data/Sync Flag to the Data level. - the FIFO output is disabled and the circuit stops automatically at FIFO full and changes to Idle State. The data in the FIFO is then available for readout. 4. Synchronization Functions 4.1 Accumulator Each Sync Core has a RAM space of 1024 x 11 bits used to implement the synchronization accumulator. The accumulator views the first 1024 bunch crossings (clock cycles) relative to the Tx_BC0 signal and ignores the other crossings in the orbit. This is considered enough to establish in a statistical basis and in a relatively short time the synchronization of BC0 with the trigger data. At every clock cycle, two operations are performed: 1) The value of the Trigger Tower energy (8-bit data word in the Input Data Bus) is compared to a programmable threshold (coded in the Energy Threshold register). If the energy is above the threshold the content of the Accumulator at the current address is incremented. When a given accumulator address reaches the maximum counting, further increments at that address are inhibited 2) The current address is incremented preparing the Accumulator for the next cycle. The following rules apply to the Accumulator operation: a) The eight Accumulators in the SLB-S can be individually addressed. b) The Accumulator operation is initiated by the Start command and it starts operating at the next Tx_BC0. Upon reception of the Tx_BC0, the Accumulator address is reset and the Accumulator logic prepares to start operating in the next clock period. c) The Accumulator is ended with the Stop command; the Accumulator stops on the next Tx_SOG. 8

d) A Clear Accumulator command can be issued at any moment without interfering with the circuit operation. e) The Accumulator content can be read at any time, without disturbing the normal data path. To read the Accumulator a Start Read Accumulator command must be issued first. Then the desired number of read cycles is performed and finally an End Read Accumulator command is issued in order to take the accumulator back to normal operation. Figure 4: Example of the contents of the accumulator. The contents the Accumulator should reflect the holes on the LHC bunch structure and the position of the Tx_BC0 command relative to the orbit. The BC0 coarse adjustment is selected in the TTCci module [9]. Additional adjustments per Sync Core can be done at the level of the TTC Decoder. 4.2 Synchronization FIFO 4.2.1 Sync Command Decoder When the Data/Sync Flag is at the Sync level, the Input Data is decoded to identify the Clear FIFO command. The value of the Input Data Word that is to be identified as Clear FIFO shall be programmable in the Clear FIFO Register. This allows adjusting the position of the clear FIFO operation in the Gap, placing it after an eventual Calibration Trigger (issued at a fixed cycle inside the gap). 4.2.2 Sync FIFO The behavior of the Synchronization FIFO is independent of the relative phase between Rx_Clk and Tx_Clk. For all phase relations, the circuit latency between data input and output is stable. The circuit tests the situations of FIFO Full at each write cycle and of FIFO Empty at each read cycle. If any of these situations are identified the relevant bits are set in the Status Register. The FIFO Full and FIFO Empty bits are reset by the Reset command (see section 6.) The maximum capacity of the FIFO is 128 x 9-bit words. 9

4.2.3 FIFO Readout For test purposes, the FIFO content can be accessed through the local control bus. 4.2.4 FIFO Latency Register The time intervals in clock cycles (latency) between the Tx_BC0-n and the Rx_BC0 are counted and stored in the Latency Registers. After a Start command, the Latency Counter is enabled in the next Tx_BC0 and when the circuit receives the Rx_BC0 signal the value of the counter is stored in the FIFO Latency Register. The value of this register is the time difference in number of clocks between both signals. The value of the FIFO Latency Register is updated every Rx_BC0 and is reset at Power-on or after a Reset or a Clear command. The FIFO Latency Register allows to monitor the Rx_BC0 timing. Rx_BC0 must arrive after all Tx_BC0 in the system, but on the other hand the latency of the synchronization FIFO should be minimized. 5. Output Functions 5.1 Channel Merging and EDC Encoding At the output of the Sync Core blocks, the EDC Encoder block merges two 9-bit words of two trigger towers in a 24-bit word by adding a 5-bit Hamming code and the Data/Sync Output Flag. The EDC Encoder generates the Hamming code as defined on the CMS IN 2001/016 [6]. The EDC bits c0-c5 are computed with the following algorithm: c0= NOT(XOR(d0,d1,d3,d4,d6,d8,d10,d11,d13,d15,d17)) c1= NOT(XOR(d0,d2,d3,d5,d6,d9,d10, d12,d13,d16,d17)) c2= NOT(XOR(d1,d2,d3,d7,d8,d9,d10,d14,d15,d16,d17)) c3= NOT(XOR(d4,d5,d6,d7,d8,d9,d10,d18)) c4= NOT(XOR(d11,d12,d13,d14,d15,d16,d17,d18)) 5.2 Output Multiplexing The 24-bit words described in the previous section and corresponding to two trigger towers are transmitted at 40 MHz to the Regional Calorimeter Trigger using the Vitesse link VSC7126. In order to match the VSC7126 specifications, the 24-bit word is multiplexed in an 8-bit output bus at 120 MHz using an external clock multiplier. The Data/Sync Output Flag transmitted every orbit synchronously to bunch zero is used at reception to set the synchronization of the three 8-bit words in the 24-bit frame and to verify the overall alignment of the trigger data. In the latest firmware of the SLB there are 2 extra 120 MHz words before start sending data. This was required by the Regional Trigger group in order to align their data on the input ASICs correctly. 5.3 Output link Each SLB sends the data of the 8 Trigger Towers to the Regional trigger receiver boards using a 4 channel high-speed link circuit from the Vitesse, VSC7126 [7]. The Vitesse receives 8bit data words @ 120MHz from the output multiplexer on the sync circuits (see 5.2). The 120MHz refclk for the Vitesse has to be free of jitter, so we have implemented an external PLL circuitry using the ICS670-01 [10] form ICS, to multiply the 40.08MHz clock (Rx_Clk) and maintain this clock clean of jitter. The Vitesse can be seen as 4 channel independent high speed links; in our design we used the four channels in parallel. We use the same rising edge of the reference clock to latch the data. The Vitesse is controlled by the embedded Sync Controller circuitry. All link operations (Resync cycle, Align data) can be executed and are documented (please refer to the Vitesse documentation [7]). 10

6. Fast Control and Error Detection Functions 6.1 TTC Decoder The Sync-S circuit receives the TTC broadcast bus, broadcast strobes and clock from an external TTCrx circuit [8]. The TTC Decoder in the Sync-S circuit recognizes the following TTC broadcast commands [9]: Hard Reset, Event Counter Reset, Start, Stop, Resync and BC0 (interpreted as Tx_BC0). For each command, the Sync-S circuit executes the following actions: Hard Reset: Performs a Clear of the Sync Circuit. TTC command only. Clears all state machines and counters, maintains the configuration values. Similar to a VME CLEAR or RESET. BC0 Start: Change the circuit state to Running (see section 3.1). The Start command can also be issued in the Control Lines. Stop: Change the circuit state to Idle (see section 3.1). The Stop command can also be issued in the Control Lines. Resync: Initiates a re-synchronization cycle. Behaves like a STOP, Vitesse Link goes to IDLE in the next SOG. Event Counter Reset: Finishes the re-synchronization cycle. Behaves like a START, Vitesse link goes to DATA on the next BC0: Generates the signal Tx_BC0-n for each Sync Core, a programmable number of clocks after BC0. These delays are stored in the Tx_BC0-n Delay registers. Generates also the signals Tx_SOG-n a programmable number of clocks after the Tx_BC0-n, between 0 and 3563. This value is stored in the SOG Delay Register. Table 13 defines the values of the TTC broadcast command decoder. The Sync-S circuit receives the external signal Rx_BC0 and the clock Rx_Clk. The function of these signals was described in section 1.2.3. 6.2 Synchronization Error Counters Two counters, associated to Tx_BC0 and Rx_BC0, are used to monitor either a BC0 missed or a clock missed during an orbit interval. These counters count the number of clock cycles between consecutive BC0 signals. When receiving the BC0, the circuit checks if the number of clocks is equal to the expected number of cycles in one orbit (3564). Any difference to this number results in incrementing the corresponding error counter and setting a status error flag. 11

7. Programmable Control 7.1 Circuit States The circuit has the following states: Running State: The circuit is in operation, sending data to the Output Data Bus. Configuration registers can not be accessed. Status registers and counters can be read. The Accumulator can be read. To simplify the implementation, the write access of the Accumulator is inhibited during the read operation. Idle State: The circuit is blind to the Input Data Bus and puts zero data in the Output Data Bus. All Registers, Counters and Accumulator can be accessed. JTAG operations are allowed. Start and Stop commands are used to change the circuit state. 7.2 Circuit Initialization After power-on and before sending a Start to the Sync circuit, configuration parameters must be initialised in order to setup the circuit for proper operation. These registers have a power-on default value that can be used for immediate operation.. To load a new configuration, global parameters (operation mode, SOG Delay, Accumulator Threshold, Clear FIFO Code and TTC Codes) must be set with identical values in both Sync-S circuits, while the remaining parameters (Tx_BC0 Delays and Constant Sync Data Codes) must be set individually for each Sync Core circuit. An HARD RESET command issued by the TTC does not change the values of these parameters. 7.2 RESYNC procedure When necessary the Trigger system can require a resynchronisation procedure. The Trigger system issues a RESYNC broadcast command followed by an Event Counter Reset broadcast command. When the SLB Controller decodes a RESYNC command the Sync Circuits will be stopped and the Vitesse put on transmitting IDLE characters on the next Start of Gap (SOG). When the SLB Controller decodes a Event Counter Reset command the Sync circuits will be started and the Vitesse put on DATA on the next BC0. 7.3 Control and Address Registers The circuit has three sets of registers to view and control the internal status and activity: Status Register, Configuration Register and Command Register. A detailed description of these registers is given in Appendix C. 12

References [1] CMS Note 1996/011, J. Varela, "A Method for Synchronization of the Trigger Data". [2] CMS CR/1997-017, J. Varela, L. Berger, R. Nobrega, A. Pierce, J.C. Silva, Trigger Synchronization circuits in CMS [3] CMS IN-1997/009, J.C. Silva, J.Varela, Specifications of the prototype trigger synchronization Tx/Rx circuits [4] CMS IN-2000/005, J.C. Silva, J. Varela, Technical Specifications of the ECAL Trigger Synchronization and Link Board Prototype [5] CMS IN-2000/006, J. Varela et al., Synchronization of the ECAL Data [6] CMS IN/2001-016, CMS Calorimeter Trigger Primitive Generator to L1Regional Trigger Interface [7] Vitesse Semiconductor Corporation, VSC7216 datasheet. [8] TTCrx Reference Manual, RD12 Working Document, J. Christiansen, A. Marchioro, P. Moreira [9] CMS NOTE-2002/033, J. Varela et al., CMS L1 Trigger Control System [10] ICS 670-01 datashet 13

Appendix A Inputs and Outputs SLB-S Input/Output Name # lines Comments 8 Input Data Bus 72 8 x 9 data bits Output Data Bus 4 4 x 1.2GBs Serial Link. TTC_CLK_DES1 1 40.08 MHz TTC_Broadcast Bus 8 TTC Broadcast Bus, Broadcast Strobe, and BCR Rx_CLK_INT (p, n) 2 Differential (LVDS, LVPECL) 40.08 MHz Rx BC0_INT (p, n) 2 Differential (LVDS, LVPECL) 1 bunch duration, LHC Orbit frequency LOCAL BUS INTERFACE 26 Address (7) and Data (16) lines; Chip Select, Read/Write JTAG BUS 4 TDI, TDO, TCK, TMS Table 2 SLB-S Input and Outputs. Sync-S Input/Output Name # lines Comments 4 Input Data Bus 36 4 x 9 data bits Output Data Bus 16 2 x 18 data bits (d0-d17) EDC 4..0 (22..18) Data Sync Flag (23) (muxed on 3 x 8 bit words @120MHz) Tx_Clock (TTC_Clk) 1 40.08 MHz TTC_Broadcast Bus 8 TTC Broadcast Bus, Broadcast Strobe, and BCR Rx Clock (*) 1 40.08 MHz Rx BC0 (*) 1 1 bunch duration, LHC Orbit frequency Rx_CLK_120 1 Rx Clock for the MUX operation, Locked on the Rx_CLK. Control Lines 26 Address (7) and Data (16) lines; Reset, Chip Select, Read/Write Vitesse Control Interface 12 C/DA, C/DB, C/DC, C/DD, WSENA, WSENB, WSENC, WSEND, KCHAR, DUAL, ENDEC, BIST Vitesse Error Inputs 4 TBERRA, TBERRB, TBERRC, TBERRD (*) common to all Sync circuit blocks Table 3- List of Input and Output lines in the Sync circuit. 14

Appendix B SLB-S slots pin assignments and PCB dimensions All the SLB-S slot connectors are male, CERN Number 09.55.40.064.7 PMC IEEE 1386 MALE 64P Figure 4: Max PCB Dimensions. The TOP side of the SLB-S faces the motherboard. 15

Appendix C High Speed Cable connections (MDR 14 Pins to High Density D15 (SVGA) connector) SLB Side (MDR 14) RT_RX Side (HD Sub-D15) Name / pin Name / pin CH A+ 8 CH A+ 2 CH A 9 CH A 1 CH B+ CH B - CH C+ 2 1 7 Kerpen Megaline cable CH CH B - CH C+ 12 11 15 CH C 6 CH C 14 CH D+ 13 CH D+ 5 CH D 14 CH D 4 All Others to ground 16

Appendix D Communication Protocol The communication with the SLB-S uses the local bus and protocol described in section 1.2.1. The board that houses the SLB-S (TCC or HTR board) is responsible for decoding the VME accesses directed to the SLB-S mezzanines and for generating the appropriate SLB-S control signals. In particular, it should generate the Local Chip Select (Local_CS) signal (Active Low) and present to the SLB-S the address lines (A[6..0]) and the 16 bits of the data bus. The SLB-S control accesses are either global or specific of a particular Sync Core (one out of eight). Therefore, the access method comprises first a selection phase (global or specific) and then the access phase. If the access is to be performed to the embedded Sync Controller only (LSB or MSB) there is no need for a Selection phase. If the access is to an individual Sync circuit then we have first to perform a Selection phase. After decoding which SLB-S component that is going to be accessed, (presenting the Local_CS) the SLB controller has to select what Sync Core is going to be accessed (selection phase) and on the next cycle(s) access the register(s) of the selected Sync Core. There are therefore registers common to all Sync Cores (see table 5) and registers specific of each Sync Core (table 9). The result of the operations can be verified on two Status Registers (one for each embedded Sync Controller) and one (eight) individual Status Registers (table 12). Description of the Tables contents Here we briefly describe the contents of the Tables. Each table describes the address used for each register access and the number of data bits needed for the corresponding address (bit field) and the access allowed (read/write). Table 4: Address Region Partition: allows to select if the access to the Sync Circuits registers is individual or Global. Table 5: Global Sync Address: The address table for all the registers / functions that are global (in bold the common addresses to both Sync Cores) Table 6: Configuration Register: Access of the configuration of the Sync Cores. Sets the Sync s operation mode. Table 7: Command Registers: Implemented Commands in the Sync Cores. Globally executed (letters in bold). Table 8: Individual Sync Address table: Address table of the existing registers for each Sync Core. Table 9: Disable/Enable Sync Channels. Default is Enable. Disable puts zero on the data path. Table 10 : SYNC LSB Status Registers. Displays the status of the SLB LSB controller. Table 11 : SYNC MSB Status Registers. Displays the status of the SLB MSB controller.. Table 12: Sync Status Register. Display the Status of each Sync Core. Same for the 8 channels. Table 13- TTC Broadcast Bus command decoder. 17

Appendix D Address Tables a) Sync Circuit controller related tables: Address Address Address Description [ 6] [ 5..4] [3..0] 1 H 00 H 0 to 3 Internal Sync selector [Sync #1 to # 4] 1 H 01 H 0 to 3 Internal Sync selector [Sync #5 to # 8] 1 H 10 See table 5 SYNC LSB Controller 1 H 11 See table 5 SYNC MSB Controller 0 H * See table 8 For Selected Sync only (access phase) Comments: Bit 4 selects the SYNC controller to be accessed (*) maintain bit 4 level for selected sync Bit 5 selects between Sync Cores or Sync Controller Bit 6 selects between Selection or Access cycles (needed for Sync circuits access) Table 4 Address Regions Partition Address [3..0] R/W Size (bits) Description 0 R 16 Status Register 1 W 7 Command Register (GLOBAL) 2 R/W 6 Configuration Register 3 R/W 7 Clear FIFO Register (default value is 16) 4 R/W 8 Energy Threshold Register (default value is 3) 5 R/W 12 Start Of Gap Delay Register (default value is 3437) 6 R/W 4 Enable Sync Channels (table 9) 7 to A R/W 6 TTC Command Decoder values B R 16 TX Sync Error Counter (Sync LSB ONLY) C R 16 RX Sync Error Counter (Sync LSB ONLY) D R 16 (8+8) Vitesse Link Error Counter (channel A) (channel B) (Sync LSB ONLY) E R 16 (8+8) Vitesse Link Error Counter (channel C) (channel D) (Sync LSB ONLY) F R 11 SLB Serial Number (Sync LSB ONLY) BOLD: (address # 0 to #A) Common to both Sync Controllers 18

Exception : Command register is global, no SYNC Selection is made Table5 Sync Controller Address table (both, LSB-MSB) BIT Command 0 Clear (Hot Reset) 1 Start 2 Stop 3 Resync 4 Clear FIFO 5 Vitesse Resync 6 Vitesse Align Data Table 7 Command Register (GLOBAL commands to both Sync Controllers) BIT Sync Tx/Rx Description (0/1) 0 Enabled Sync TT #1 (or TT #5) Disabled / Enabled 1 Enabled Sync TT #2 (or TT #6) Disabled / Enabled 2 Enabled Sync TT #3 (or TT #7) Disabled / Enabled 3 Enabled Sync TT #4 (or TT #8) Disabled / Enabled Table 9 : Enabled Sync Channels (by default all channels are enabled) ADD[4..0] TTC Signal TTC DECODER REG [5..0] (default values) 7 STOP H 0A 8 START H 0B 9 BC0 H 0C A RESYNC H 0D B Hard Reset H 1F C Ev_Counter_Reset H 01 Table 13: TTC bus decoder. 19

BIT Sync Tx/Rx Description (0/1) 0 Enabled Sync TT #1 Disabled / Enabled 1 Enabled Sync TT #2 Disabled / Enabled 2 Enabled Sync TT #3 Disabled / Enabled 3 Enabled Sync TT #4 Disabled / Enabled 4 Tx Operation Mode (GLOBAL) TEST / SYNC 5 TX test mode Constant/Counter 6 Rx Operation Mode (GLOBAL) FIFO FILLING / SYNC 7 Status IDLE/ RUNNING 8 Tx Sync Errors Errors Tx Sync Signals 9 Rx Sync Errors Errors Rx Sync Signals A Vitesse Errors Errors on Vitesse TX side (A to D) Table 10 SYNC LSB Status Register BIT Sync Tx/Rx Description (0/1) 0 Enabled Sync TT #5 Disabled / Enabled 1 Enabled Sync TT #6 Disabled / Enabled 2 Enabled Sync TT #7 Disabled / Enabled 3 Enabled Sync TT #8 Disabled / Enabled 4 Tx Operation Mode (GLOBAL) TEST / SYNC 5 TX test mode Constant/Counter 6 Rx Operation Mode (GLOBAL) FIFO FILLING / SYNC 7 Status IDLE/ RUNNING Table 11 SYNC MSB Status Register 20

b) Individual Sync Core related tables: BIT Operation Description (0/1) 0 Tx Operation Mode Test / Sync 1 Tx Data Sync Generator Constant Sync / Counter Sync 2 Rx Operation Mode Fifo_Filling / Sync Table6 Configuration Register (by default the circuits operate in Sync mode) Address [3..0] R/W Size (bits) Description (default) 0 R 16 Status Register 1 R/W 9 Constant Sync Data (Sync Core id : 1 to 8) 2 R 1024 x 11 Read Accumulator 3 R 128 x 9 Read FIFO 4 R 12 FIFO Latency Register 5 R/W 4 Tx_BC0_Delay Register (0) 6 W - Start Read Accumulator 7 W - End Read Accumulator 8 W - Clear Accumulator Table 8 Individual Sync Address table BIT Sync Tx/Rx Description (0/1) 0 State Idle/Running 1 Tx Operation Mode Test / Sync 2 Tx Test mode Constant Sync / Counter Sync 3 Rx Operation Mode Fifo_Filling / Sync 4 Enable Accumulator not Enabled / Enabled 5 Threshold Not Incrementing / Incrementing 6 Full FIFO not full / full 7 Empty FIFO not empty / empty Table 12 SYNC Status Register 21