INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATION ENGINEERING & TECHNOLOGY (IJECET) International Journal of Electronics and Communication Engineering & Technology (IJECET), ISSN 0976 6464(Print) ISSN 0976 6472(Online) Special Issue (November, 2013), pp. 144-149 IAEME: www.iaeme.com/ijecet.asp Journal Impact Factor (2013): 5.8896 (Calculated by GISI) www.jifactor.com IJECET I A E M E Design and Analysis of CNTFET Based D Flip-Flop Sneh Lata Murotiya 1, Anu Gupta 2 Electrical and Electronics Department, BITS Pilani, India 1snehlata@pilani.bits-pilani.ac.in, 2 anug@pilani.bits-pilani.ac.in ABSTRACT: Carbon Nanotube Field-Effect Transistor (CNTFET) with 1-D band structure providing an excellent current driving capability on account of ballistic transport operation has proved to be a promising alternative to the conventional CMOS technology. This paper presents a design, performance evaluation and comparative analysis of CNTFET based negative edge triggered D-Flip flop (DFF). This DFF is designed using pass transistor logic style with single clock phase, and includes reset function also. HSPICE simulation result shows that the presented DFF consumes significantly lower power and delay than its CMOS counterpart at 32 nm technology. The reported result also shows that the proposed DFF based gray counter and linear feedback shift register (LFSR) achieves 96% and 97% performance improvement over CMOS designs in terms of Power delay product (PDP). KEYWORDS: Carbon nano tube (CNT) field effect transistor (CNTFET), D Flip-flop (DFF), Gray counter, Linear feedback shift register (LFSR), Power delay product (PDP) I. INTRODUCTION The scaling of current CMOS technology to nanoscale range leads to various critical challenges and reliability issues which will considerably reduce the potential of CMOS technology for high performance applications in near future. To handle these issues, such as electron tunneling through short channels and thin insulator films, variations in device structure and doping, the increased leakage currents and high power dissipation, scientists and researchers are working towards new alternatives to replace bulk CMOS process [1]. Carbon nano tube field effect transistor (CNTFET) could be one promising and superior alternative, due to its resemblance with MOSFET in terms of intrinsic attributes and also due to its various superior characteristics [2]. In CNTFET, the carrier velocity is almost double due to high mobility on account of ballistic transport operation with 1-D band structure, than that of MOSFET. In a planar gate structure, the p-cntfet produces 1500 A/m of the ON-current per unit width at a gate overdrive of 0.6 V while p-mosfet produces only 500 A/m at the same gate overdrive. This ON-current advantage comes from the high gate capacitance and improved channel transport. Since an effective gate capacitance per unit width is twice than that of MOSFET, the compatibility with B K Birla Institute of Engineering & Technology (BKBIET), Pilani, India Page 144
high- k gate dielectric becomes a great advantage for CNTFET. In addition, CNTFET has about four times higher trans-conductance with respect to MOSFET [3]. Apart from the mentioned advantages, it has also some challenges like growth and positioning of single wall CNTs, chirality control, fabrication process and mass production technologies etc. However, encouraging researches are being pursued to handle these challenges in time to time [4]. Flip-flops (FFs) are used extensively as basic storage elements in all kinds of digital systems. In particular, modern digital designs which implement intensive pipelining techniques employ many FFs-rich modules. Further, the power consumption of the clock system, which consists of clock distribution networks and storage elements, is as high as 20% 45% of the total system power [5]. Therefore, fast and low power FFs are required for high performance systems. In this paper, CNTFETs based negative edge-triggered DFF designed using pass transistor logic style, is presented. This DFF uses single clock phase and implements reset function also. Few circuits such as gray counter and LFSR are also implemented. The reported results show that the presented CNTFET-based designs achieve great improvements in terms of speed and power compared to their CMOS counterpart. II. CARBON NANO TUBE FIELD EFFECT TRANSISTOR (CNTFET) CNTFET is a type of field-effect transistor that utilizes single wall carbon nano tubes (SWCNTs) as the channel material instead of bulk silicon used in the traditional MOSFET structure. A SWCNT is a nanotube formed by rolling a single sheet of graphite. It can either be metallic or semiconducting depends on the chirality vector (n1, n2), i.e. the direction in which the graphite sheet is rolled. If n1-n2 is a multiple of 3, SWCNT is metallic or else it is semiconducting [5]. Fig.1 shows the schematic of CNTFET [6]. In this device, intrinsic region of CNTs act as a carrier channel, which is turned on or off electrically via the gate electrode. The heavily doped nano tube regions act as both source/drain extension region and the local interconnect between two adjacent devices. A high k dielectric is used as the gate oxide, to provide better gate control. As the gate bias is applied, the barrier height is modulated and delivers more on current. The quasi-1d device structure gives better gate electrostatics control over the gate region and reduces resistance in the channel region which results in minimization of power and energy consumption. Since electrons are confined to narrow tubes only, the carrier mobility goes up substantially compared to MOSFET [6]. These features make CNTFET a suitable candidate for high performance and low power digital applications. Fig. 1: schematic of CNTFET (a) 3d structure (b) cross section view B K Birla Institute of Engineering & Technology (BKBIET), Pilani, India Page 145
The channel width of CNTFET depends on the number of CNTs and pitch value which is the distance between the centers of two adjoining CNTs under the same gate. Its approximate value can be determined using equation (1) [6]: W min Wmin, N S (1) Where Wmin is the minimum gate width, N is the number of tubes and S is the pitch. Further, the threshold voltage of the transistor depends on the diameter of the CNT. It can be approximated to the first order as the half band gap and can be estimated as follows [6]: V th Eg 1 av 0.436 (2) 2e 3 ed D ( nm) CNT CNT Where a (= 0.249 nm) is the Carbon-Carbon atom distance, e is unit electron charge, Vπ (=3.033 ev) is the Carbon π-π bond energy in the tight bonding model and DCNT is CNT diameter which is determined by the chirality vector (n1, n2). This paper utilizes CNTFETs with chirality vector of (19, 0). III. CNTFET BASED DFF & ITS APPLICATIONS A. Proposed Negative Edge Triggered DFF The most compact implementation of edge triggered DFF is based on inverters and pass transistors as shown in Fig. 2.This DFF combines a pair of D latches in Master and slave configuration. The edge triggered latch consists of two chained inverters with one PMOS loop transistor. When Clk =0, input transistor N1 is OFF and two cross coupled inverters of the master latch, having transistors P1, P2, N2 and N3, are in memory state because loop transistor P5 is ON. If Clk = 1, N1 is ON and this latch is transparent for the input Din. Other two chain inverters having transistors P3, P4, N4, N5, and loop transistor N8 of the slave latch acts in opposite way. For the reset of DFF, master and slave latches are connected to ground using transistors N6 and N7.This negative edge triggered DFF simply invert the clock input such that all the actions are performed at falling edge of Clk. As shown in Fig. 2, the presented DFF runs on a single clock while the conventional pass transistor based DFF uses dual clock (clock and its complement). The application examples of this proposed DFF are described in next two subsections. Fig. 2: Schematic of a CNTFET-based negative edge triggered D flip flop B K Birla Institute of Engineering & Technology (BKBIET), Pilani, India Page 146
B. Gray Counter The main applications of DFF are registers and counters. A counter is essentially a register that goes through a predetermined sequence of states. The gray counter generates a n bit gray Code.The advantages of gray code over the straight binary number sequence is efficient and glitch free operation as it changes only one bit at a time. When Gray codes are used in computers to address program memory, the computer uses less power because fewer address lines change as the program counter advances. Gray codes are widely used to facilitate error correction in digital communications such as digital terrestrial television and some cable TV systems. In addition, they also work as a high speed decoder due to less decoding logic. A 4-bit gray counter based on above described DFFs and logic gates, is implemented using conventional method [7]. Simulation results show that only one bit in the code group changes at the negative edge of the clock, when going from one number to the next. C. Linear feedback shift register (LFSR) Linear feedback shift register (LFSR) is a type of shift register which is modeled in such a way that input bit is a linear function of its previous states [7]. In this register, some of the outputs are combined in exclusive-or configuration to form a feedback mechanism.. A LFSR can be formed by performing exclusive-or on the outputs of two or more of the flip-flops together and feeding those outputs back into the input of one of the flip flops. In this paper, a four bit LFSR is implemented using four presented DFFs in series with the third and fourth one connected back to the first one via a XOR gate. The initial values are seeded in this register by using the reset functionality of proposed DFF. LFSR is used in a variety of applications such as Built-in-self test (BIST), error correction code, cryptography, fast digital counters and pseudorandom numbers and pseudo-noise sequences generator in communication systems. D. Results and Observations In this section, the proposed DFF is analyzed and evaluated using HSPICE simulator with Stanford model of 32nm CNTFET [6]. This model includes non-idealities such as scattering, parasitic effects and CNT charge screening effects and so on. In addition, it provides accurate predictions of dynamic and transient performance with more than 90% accuracy [8]. The simulated transient waveform of proposed DFF is shown in Fig. 3. It is clearly seen from Fig. 3 that the DFF samples input data Din at negative edge of the Clk signal, which confirms the correct functionality of DFF. For comparative analysis with CMOS technology, simulations are performed with PTM High Performance 32nm Metal Gate / High-K / Strained-Si based CMOS model [9]. For fair comparison, equivalent transistor size ratios are used. Simulations are performed at room temperature, at 100MHz clock frequency with rise time and fall time of 1ps, and at 0.9 V supply voltage with 10fF output load. Comparison of DFF on the propagation delay, average power dissipation and setup time, is shown in Table 1. Propagation delay from clock to Q (DClk-Q) has been calculated as the mean of Low to High and High to Low transitions. Total Delay is computed by the summation of DClk-Q and Setup time. Table 1 shows that power dissipation and propogation delay of CNTFET DFF is less than that of CMOS DFF by a factor of 4.6 and 2.9 respectively. Hence, these results show the superiority of CNTFET in every aspect. B K Birla Institute of Engineering & Technology (BKBIET), Pilani, India Page 147
Fig. 3: transient waveforms for CNTFET based negative edge triggered DFF Design Metrics CNTFET DFF CMOS DFF DClk-Q (ps) 87.7 250 Setup Time (ps) 90.0 260 Total Delay (ps) 177.7 510 Average Power 0.26 1.20 (µw) Hold Time 2.50 77.0 Table 1: Different design metrics for CNTFET and CMOS DFF Simulations are also carried out on gray counter as well as LFSR. The sample transient waveforms of one stage of 4-bit LFSR is shown in Fig. 4 which confirms its correct operation of serial shifting with feedback function, at negative clock edge. The propagation delay and average power dissipation of gray counter and LFSR circuits are shown in Table 2. The results show that the propagation delay and power dissipation of CNTFET based designs are less than CMOS designs. Fig. 4: Transient waveforms for CNTFET based 4-bit LFSR Circuits Power consumption (µw) Maximum operating frequency (GHz) GRAY CNTFET 0.93 6.60 GRAY CMOS 9.05 2.85 LFSR CNTFET 0.61 8.00 LFSR CMOS 8.88 3.30 Table 2: Different design metrics for CNTFET and CMOS based circuits B K Birla Institute of Engineering & Technology (BKBIET), Pilani, India Page 148
IV. CONCLUSION This paper has presented the performance assessment of edge triggered DFF for silicon based CMOS as well as carbon nano-tube technologies. The comparative analysis of DFF has shown that its CNTFET implementation achieves great improvements in terms of speed and power with respect to CMOS implementation. As application examples of proposed DFF, gray counter and LFSR have been also designed. Simulation results have shown that these circuits have low power dissipation and high performance and therefore, outperform their CMOS counterparts. The observed results reveal that CNTFET has potential to replace CMOS for low power and high performance applications in near future. REFERENCES [1] K. Roy, S. Mukhopadhyay, and H. Meimand-Mehmoodi, Leakage current mechanisms and leakage reduction techniques in deep-submicron CMOS circuits, IEEE Proc., 2003, 305 327. [2] I. O Connor, J. Liu, F. Gaffiot, F. Pregaldiny, C. Lallement, C. Maneux, J. Goguet, S. Fregonese, T. Zimmer, L. Anghel, and R. Leveugle, CNTFET Modeling and Reconfigurable Logic-Circuit Design, IEEE Transactions on Circuits and Systems I: Regular Papers, 54, 2007, 2365 2379. [3] H.-S. Wong, Beyond the conventional transistor: Solid-State Electronics, 4, 2004, 755-762. [4] W. Chuan, R. Koungmin, B. Alexander, Z. Jialu, and Z. Chongwu, Metal Contact Engineering and Registration-Free Fabrication of Complementary Metal-Oxide Semiconductor Integrated Circuits Using Aligned Carbon Nanotubes, ACS Nano, 5, 2011,1147 1153. [5] H. Kawaguchi and T. Sakurai, A reduced clock-swing flip-flop (RCSFF) for 63% power reduction, IEEE J. Solid-State Circuits, 33(5), 1998, 807 811. [6] Stanford University CNTFET Model website [Online]. Available: http://nano.stanford.edu/model.php?id=23 [7] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd Ed. Englewood Cliffs, NJ: Prentice- Hall, 2002. [8] Jie Deng, H.-S.P. Wong, A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application Part II: Full Device Model and Circuit PerformanceBenchmarking, IEEE Trans. Electron Devices, 54(12), 2007, 3195 3205. [9] Berkeley Predictive Technology Model website [Online]. Available: http://www.eas.asu.edu/~ptm/. B K Birla Institute of Engineering & Technology (BKBIET), Pilani, India Page 149