Based on slides/material by Topic 4 K. Masselos http://cas.ee.ic.ac.uk/~kostas J. Rabaey http://bwrc.eecs.berkeley.edu/classes/icbook/instructors.html igital Integrated Circuits: A esign Perspective, Prentice Hall ing Peter Y. K. Cheung epartment of Electrical & Electronic Engineering Imperial College London. Harris http://www.cmosvlsi.com/coursematerials.html Weste and Harris, CMOS VL esign: A Circuits and Systems Perspective, Addison Wesley Recommended Reading: J. Rabaey et. al. igital Integrated Circuits: A esign Perspective : esign Methodology Insert H URL: http://www.ee.ic.ac.uk/pcheung Weste and Harris, CMOS VL esign: A Circuits and Systems Perspective : Chapter 9 Topic 4 - Topic 4-2 ing Verification ing is one of the most expensive parts of chips verification accounts for > 5% of design effort for many chips ebug time after fabrication has enormous opportunity cost Shipping defective parts can sink a company Example: Intel FIV bug error not caught until > M units shipped Recall cost $45M (!!!) oes the chip simulate correctly? Usually done at HL level Verification engineers write test bench for HL Can t test all cases Look for corner cases Try to break logic design Ex: 32-bit adder all combinations of corner cases as inputs:,, 2, 2 3 -, -, -2 3, a few random numbers Good tests require ingenuity Topic 4-3 Topic 4-4
Silicon ebug Shmoo Plots the first chips back from fabrication If you are lucky, they work the first time If not bugs vs. electrical failures Most chip failures are logic bugs from inadequate simulation Some are electrical failures Crosstalk ynamic nodes: leakage, charge sharing Ratio failures A few are tool or methodology failures (e.g. RC) How to diagnose failures? Hard to access chips Picoprobes Electron beam Laser voltage probing Built-in self-test Shmoo plots Vary voltage, frequency Look for cause of electrical failures Fix the bugs and fabricate a corrected chip Topic 4-5 Topic 4-6 Manufacturing Validation and of Manufactured Circuits A speck of dust on a wafer is sufficient to kill chip Yield of any chip is < % Must test chips after manufacturing before delivery to customers to only ship good parts Manufacturing testers are very expensive Minimize time on tester Careful selection of test vectors Goals of esign-for- (FT) Make testing of manufactured part swift and comprehensive FT Mantra Provide controllability and observability Components of FT strategy Provide circuitry to enable test Provide test patterns that guarantee reasonable coverage Topic 4-7 Topic 4-8
Classification ability iagnostic test used in chip/board debugging defect localization go/no go or production test Used in chip production N inputs Module K outputs N inputs Module K outputs Parametric test x e [v,i] versus x e [,] check parameters such as NM, Vt, tp, T M state regs (a) function (b) Sequential engine 2 N patterns 2 N+M patterns Exhaustive test is impossible or unpractical Topic 4-9 Topic 4 - Controllability/Observability esign the chip to increase observability and controllability Circuits: controllable and observable - relatively easy to determine test patterns If each register could be observed and controlled, test problem reduces to testing combinational logic between registers. Sequential Circuits: State! Turn into combinational circuits or use self-test Better yet, logic blocks could enter test mode where they generate test patterns and report the results automatically. Memory: requires complex patterns Use self-test Topic 4 - Topic 4-2
Generating and Validating -Vectors Fault Models Automatic test-pattern generation (ATPG) for given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output majority of available tools: combinational networks only sequential ATPG available from academic research Fault simulation determines test coverage of proposed test-vector set simulates correct network in parallel with faulty networks Both require adequate models of faults in CMOS integrated circuits Most Popular - Stuck - at model sa (output) sa (input) x α γ x2 β Covers almost all (other) occurring faults, such as opens and shorts. Z x3 α, γ : x sa β : x sa or x2 sa γ : Z sa Topic 4-3 Topic 4-4 Problem with stuck-at model: CMOS open fault Problem with stuck-at model: CMOS short fault x x2 x x2 Z C A B Causes short circuit between Vdd and GN for A=C=, B= Sequential effect Needs two vectors to ensure detection! A B C Possible approach: Supply Current Measurement (I) but: not applicable for gigascale integration Other options: use stuck-open or stuck-short models This requires fault-simulation and analysis at the switch or transistor level - Very expensive! Topic 4-5 Topic 4-6
Pattern Generation Path Sensitization Manufacturing test ideally would check every node in the circuit to prove it is not stuck. Apply the smallest sequence of test vectors necessary to prove each node is not stuck. Good observability and controllability reduces number of test vectors required for manufacturing test. Reduces the cost of testing Motivates design-for-test Goals: etermine input pattern that makes a fault controllable (triggers the fault, and makes its impact visible at the output nodes) Fault enabling Fault propagation sa Out Techniques Used: -algorithm, Podem Topic 4-7 Topic 4-8 Example Approaches SA SA A 3 {} {} A 2 {} {} A {} {} A {} {} n {} {} n2 {} {} n3 {} {} Y {} {} A 3 A 2 A A n2 n n3 Y Ad-hoc testing Scan-based Self- Problem is getting harder increasing complexity and heterogeneous combination of modules in systemon-a-chip. Advanced packaging and assembly techniques extend problem to the board level Minimum set: {,,,,, } Topic 4-9 Topic 4-2
Ad-hoc Scan Memory Memory data address test data select Processor Processor I/O bus I/O bus Inserting multiplexer improves testability address Convert each flip-flop to a scan register Only costs one extra multiplexer Normal mode: flip-flops behave as usual Scan mode: flip-flops behave as shift register Contents of flops can be scanned out and new values scanned in inputs scan-in Flop Flop Flop Flop Cloud Flop Flop Flop Flop SCAN Cloud CLK Flop Flop Flop Flop Flop outputs scan out Topic 4-2 Topic 4-22 Scan-based Scannable Flip-flops SCAN ScanIn ScanOut (a) SCAN CLK X In Register A Register B Out (b) d SCAN d d X s (c) s s Topic 4-23 Topic 4-24
Polarity-Hold SRL (Shift-Register Latch) Scan-based Operation System ata System Clock Scan ata Shift A Clock C A L ScanIn In Latch Out In Latch Out In 2 Latch Out 2 In 3 Latch Out 3 ScanOut SO Shift B Clock B L2 SO φ Introduced at IBM and set as company policy φ 2 N cycles scan-in cycle evaluation N cycles scan-out Topic 4-25 Topic 4-26 Scan-Path ing Boundary Scan A REG[] REG[2] + REG[4] B REG[] REG[3] SCANIN ing boards is also difficult Need to verify solder joints are good rive a pin to, then to Check that all connected pins get the values Through-hold boards used bed of nails SMT and BGA boards cannot easily contact pins Build capability of observing and controlling pins into each chip to make board test easier COMPIN COMP REG[5] SCANOUT OUT Partial-Scan can be more effective for pipelined datapaths Topic 4-27 Topic 4-28
Boundary Scan (JTAG) Boundary Scan Example Printed-circuit board Packaged IC Package Interconnect Scan-in Scan-out si so scan path normal interconnect CHIP B CHIP C Serial ata Out CHIP A CHIP Bonding Pad Board testing becomes as problematic as chip testing IO pad and Boundary Scan Cell Serial ata In Topic 4-29 Topic 4-3 Boundary Scan Interface Built-in Self-test Boundary scan is accessed through five pins TCK: test clock TMS: test mode select TI: test data in TO: test data out TRST*: test reset (optional) Built-in self-test lets blocks test themselves Generate pseudo-random inputs to comb. logic Combine outputs into a syndrome With high probability, block is fault-free if it produces the expected syndrome Chips with internal scan chains can access the chains through boundary scan for unified test strategy. Topic 4-3 Topic 4-32
Self-test PRSG (Sub)-Circuit Linear Feedback Shift Register Shift register with input taken from XOR of state Pseudo-Random Sequence Generator Stimulus Generator Under Response Analyzer Step Controller 2 3 Rapidly becoming more important with increasing chip-complexity and larger modules 4 5 6 7 (repeats) Topic 4-33 Topic 4-34 Linear-Feedback Shift Register (LFSR) Signature Analysis R R R In Counter S S S 2 R Counts transitions on single-bit stream Compression in time Pseudo-Random Pattern Generator Topic 4-35 Topic 4-36
BILBO BILBO Application B 2 B ScanIn ScanOut ScanIn mux R R R ScanOut S S S2 In BILBO-A BILBO-B Out B B Operation mode Normal Scan Pattern generation or Signature analysis Reset Topic 4-37 Topic 4-38 BILBO Memory Self- Built-in Block Observer Combine scan with PRSG & signature analysis C[] C[] [] [] [2] [] [] [2] / SO FSM data-in address & Memory Under data-out Signature Analysis R/W control PRSG Cloud Signature Analyzer MOE C[] C[] Scan Reset Normal Patterns: Writing/Reading s, s, Walking s, s Galloping s, s Topic 4-39 Topic 4-4
Low Cost ing osterics If you don t have a multimillion dollar tester: Build a breadboard with LE s and switches Hook up a logic analyzer and pattern generator Or use a low-cost functional chip tester Ex: osterics functional chip tester esigned by clinic teams and avid iaz at HMC Reads your IRM test vectors, applies them to your chip, and reports assertion failures Topic 4-4 Topic 4-42 Summary Think about testing from the beginning Simulate as you go Plan for test after fabrication If you don t test it, it won t work! (Guaranteed) Topic 4-43