SDI II MegaCore Function SDI II MegaCore Function 1 Innovation Drive San Jose, CA 95134 www.altera.com UG-01125-1.0 Document last updated for Altera Complete Design Suite version: Document publication date: 12.1 November 2012 Feedback Subscribe
2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered November 2012 Altera Corporation SDI II MegaCore Function
Contents SDI II MegaCore Function Quick Reference Chapter 1. SDI II MegaCore Function Overview General Description..................................................................... 1 1 SMPTE372 Support................................................................... 1 2 Level A to Level B conversion........................................................ 1 2 Level B to Level A conversion........................................................ 1 3 Resource Utilization..................................................................... 1 4 Chapter 2. Getting Started Installation and Licensing................................................................ 2 1 OpenCore Plus Evaluation............................................................. 2 1 Design Walkthrough..................................................................... 2 2 Creating a New Quartus II Project....................................................... 2 2 Launching MegaWizard Plug-In Manager................................................ 2 3 Parameterizing the MegaCore Function.................................................. 2 3 Generating a Design Example and Simulation Testbench................................... 2 3 Design Examples................................................................... 2 4 Simulating the Design................................................................. 2 8 Compiling the Design.................................................................... 2 9 Programming a Device................................................................... 2 9 Design Reference........................................................................ 2 9 MegaCore Parameters................................................................. 2 9 MegaCore Component Files........................................................... 2 11 Video Pattern Generator Signals....................................................... 2 11 Transceiver Reconfiguration Controller Signals.......................................... 2 12 Chapter 3. Functional Description Protocol................................................................................ 3 1 Transmitter.......................................................................... 3 1 Receiver............................................................................. 3 4 Transceiver............................................................................. 3 8 Submodules............................................................................ 3 8 Insert Line........................................................................... 3 9 Insert/Check CRC.................................................................... 3 9 Insert VPID......................................................................... 3 Match TRS.......................................................................... 3 11 Scrambler........................................................................... 3 12 Tx Sample.......................................................................... 3 12 Clock Enable Generator............................................................... 3 12 Rx Sample.......................................................................... 3 13 Detect Video Standard................................................................ 3 14 Detect 1 & 1/1.001 Rates.............................................................. 3 14 Transceiver Controller................................................................ 3 15 Descrambler......................................................................... 3 16 TRS Aligner......................................................................... 3 16 3Gb Demux......................................................................... 3 17 Extract Line......................................................................... 3 17 November 2012 Altera Corporation SDI II MegaCore Function
iv Contents Extract VPID........................................................................ 3 17 Detect Format....................................................................... 3 17 Sync Streams........................................................................ 3 18 Clocking Scheme....................................................................... 3 19 Oversampling Rate................................................................... 3 19 Signals................................................................................ 3 19 Additional Information Document Revision History........................................................... Info 1 How to Contact Altera................................................................ Info 1 Typographic Conventions............................................................. Info 1 SDI II MegaCore Function November 2012 Altera Corporation
SDI II MegaCore Function Quick Reference The Altera Serial Digital Interface (SDI) II MegaCore function is the next generation SDI intellectual property (IP). The SDI II MegaCore function is part of the MegaCore IP Library, which is distributed with the Quartus II software and downloadable from the Altera website at www.altera.com. 1 For system requirements and installation instructions, refer to Altera Software Installation & Licensing. The table below lists a brief information about the SDI II MegaCore function. Item Release Information Version 12.1 Release Date November 2012 Ordering Code IP-SDI-II Product ID(s) 0111 Vendor ID 6AF7 IP Information SDI Data Rate Support Description 270-Mbps SD-SDI, as defined by SMPTE259M specification 1.485-Gbps or 1.4835-Gbps HD-SDI, as defined by SMPTE292M specification 2.97-Gbps or 2.967-Gbps 3G-SDI, as defined by SMPTE424M specification Dual link HD-SDI, as defined by SMPTE372M specification Dual standard support for SD-SDI and HD-SDI Triple standard support for SD-SDI, HD-SDI, and 3G-SDI SMPTE425M level A support (direct source image formatting) SMPTE425M level B support (dual link mapping) 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. ISO 9001:2008 Registered November 2012 Altera Corporation SDI II MegaCore Function
I 2 SDI II MegaCore Function Quick Reference Item Features Device Family Support Design Tools Description Multiple SDI standards and video formats Video payload identification (VPID) packet insertion and extraction Clock enable generator Video rate detection Cyclical redundancy check (CRC) encoding and decoding (HD only) Line number (LN) insertion and extraction (HD only) Word scrambling and descrambling Word alignment Transmitter clock multiplexer (optional) Framing and extraction of video timing signals Dual link data stream synchronization (HD only) IPUTF compliance core (hw.tcl) IEEE encryption for functional simulation Transceiver dynamic reconfiguration Dynamic generation of simulation testbench Dynamic generation of design example entity OpenCore Plus evaluation Arria V and Stratix V FPGA devices Refer to the What s New in Altera IP page of the Altera website for detailed information. MegaWizard Plug-In Manager in the Quartus II software for design creation and compilation ModelSim -Altera software for design simulation or synthesis SDI II MegaCore Function November 2012 Altera Corporation
1. SDI II MegaCore Function Overview The SDI II MegaCore function implements a transmitter, receiver, or full-duplex SDI at standard definition (SD), high definition (HD), or 3 gigabits per second (3G) rate as defined by the Society of Motion Picture and Television Engineers (SMPTE). The SDI II MegaCore function supports dual standard (SD-SDI and HD-SDI) and triple standard (SD-SDI, HD-SDI, and 3G-SDI). These modes provide automatic receiver rate detection and transceiver dynamic reconfiguration. The SDI II MegaCore function highlights the following new features: Supports 28 nm devices (Stratix V and Arria V in Quartus II version 12.1) and beyond IPUTF compliance core (hw.tcl) IEEE encryption for functional simulation Dynamic generation of user simulation testbench that matches the IP configuration Dynamic generation of design example that serves as common entity for simulation and hardware verification General Description The SMPTE defines a SDI standard that is widely used as an interconnect between equipment in video production facilities. The SDI II MegaCore function can handle the following SDI data rates: 270 megabits per second (Mbps) SD-SDI, as defined by SMPTE259M-1997 -Bit 4:2:2 Component Serial Digital Interface 1.485 gigabits per second (Gbps) or 1.4835-Gbps HD-SDI, as defined by SMPTE292M-1998 Bit-Serial Digital Interface for High Definition Television Systems 2.97-Gbps or 2.967-Gbps 3G SDI, as defined by SMPTE424M Dual link HD-SDI, as defined by SMPTE372M-Dual Link 1.5Gb/s Digital Interface for 1920 80 and 2048 80 Picture Formats Dual standard support for SD-SDI and HD-SDI Triple standard support for SD-SDI, HD-SDI, and 3G-SDI SMPTE425M level A support (direct source image formatting) SMPTE425M level B support (dual link mapping) November 2012 Altera Corporation SDI II MegaCore Function
1 2 Chapter 1: SDI II MegaCore Function Overview General Description Table 1 1 lists the SDI standard support for various devices. Table 1 1. SDI Standard Support (1) SDI Standard Device Family SD-SDI HD-SDI 3G-SDI HD-SDI Dual Link (2) Dual Standard Triple Standard Arria V v v v v v v Stratix V v v v v v v Notes to Table 1 1: (1) All standards require a transceiver-based or GX device. (2) The HD-SDI dual link supports timing difference up to 40 ns between link A and link B, fulfilling the SMPTE372M requirement. SMPTE372 Support Recording studios support HD 80p format by using a dual-link connection (SMPTE372) from cameras to the mixing and recording equipment. The SMPTE 372 specification defines a way of interconnecting digital video equipment with a dual link HD-SDI (link A and link B), based upon the SMPTE292 specification data structure. The total data rate of the dual link connection is 2.97 Gbps or 2.97/1.001 Gbps. Level A is defined as a direct source image mapping while level B is defined as 2 x SMPTE292 HD-SDI mapping (including SMPTE372 dual link mapping). Level A to Level B conversion To interface between HD dual link receiver and 3G-SDI single link transmitter equipment, perform a level A to level B conversion. This conversion takes either two 1.485 Gbps dual link signals or two separate co-timed HD signals and combines them into a single 3G-SDI stream. Figure 1 1 shows the level A to level B conversion. Figure 1 1. Conversion of Two HD-SDI Data Streams to 3G-SDI Level B Data Data Stream 1 3FFh(C1) 3FFh(Y1) 000h(C1) 000h(Y1) 000h(C1) 000h(Y1) XYZ(C1) XYZ(Y1) LN0(C1) LN0(Y1) LN1(C1) LN1(Y1) Multiplexing Data Stream 2 3FFh(C2) 3FFh(Y2) 000h(C2) 000h(Y2) 000h(C2) 000h(Y2) XYZ(C2) XYZ(Y2) LN0(C2) LN0(Y2) LN1(C2) LN1(Y2) 3G-SDI Level B Interleaved Stream 3FFh(C2) 3FFh(C1) 3FFh(Y2) 3FFh(Y1) 000h(C2) 000h(C1) 000h(Y2) 000h(Y1) XYZ(C2) XYZ(C1) XYZ(Y2) XYZ(Y1) LN0(C2) LN0(C1) LN0(Y2) LN0(Y1) LN1(C2) LN1(C1) LN1(Y2) LN1(Y1) SDI II MegaCore Function November 2012 Altera Corporation
Chapter 1: SDI II MegaCore Function Overview 1 3 General Description Figure 1 2 shows a block diagram of the level A to level B conversion. Figure 1 2. Implementation of Level A to Level B Conversion HD Dual-Link Receiver rx_clkout (74.25 MHz) Sync Stream HD Link A Transceiver Protocol FIFO rxdataa rxdataa rdreq HD Link B Transceiver rxdatab Protocol rxdatab FIFO rx_clkin_smpte372 (148.5 MHz) rx_clkout_b (74.25 MHz) Divide Clock rdreq rdclk_3gb_div2 = 1H1L1H1L rx_dataout[19:0] xcvr_refclk (74.25 MHz) rx_clkout (74.25 MHz) rxdataa[19:0] rxdataa[9:0] rx_clkout_b (74.25 MHz) rxdatab[19:0] rxdatab[9:0] Y1 Y1 Y1 Y1 C1 C1 C1 C1 Y2 Y2 Y2 Y2 C2 C2 C2 C2 rx_clkin_smpte372 (148.5 MHz) rdclk_3gb_div2 rx_dataout[19:0] rx_dataout[9:0] C1 Y1 C1 Y1 C1 Y1 C1 Y1 C2 Y2 C2 Y2 C2 Y2 C2 Y2 Level B to Level A conversion To interface between 3-Gbps single link receiver and HD dual link transmitter equipment, perform a level B to level A conversion. This conversion takes a single 3G-SDI signal and separates the signal into two 1.485 Gbps signals, which can either be a dual link 80p signal or two separate co-timed HD data streams. Figure 1 3 shows the level B to level A conversion. Figure 1 3. Conversion of 3G-SDI Level B Data To Two HD-SDI Data Streams 3FFh(C2) 3FFh(C1) 3FFh(Y2) 3FFh(Y1) 000h(C2) 000h(C1) 000h(Y2) 000h(Y1) XYZ(C2) XYZ(C1) XYZ(Y2) XYZ(Y1) LN0(C2) LN0(C1) LN0(Y2) LN0(Y1) LN1(C2) LN1(C1) LN1(Y2) LN1(Y1) 3G-SDI Level B Interleaved Stream Demux Data Stream 1 Data Stream 2 3FFh(C1) 3FFh(Y1) 000h(C1) 000h(Y1) 3FFh(C2) 3FFh(Y2) 000h(C2) 000h(Y2) 000h(C1) 000h(Y1) 000h(C2) 000h(Y2) XYZ(C1) XYZ(Y1) LN0(C1) LN0(Y1) LN1(C1) LN1(Y1) XYZ(C2) XYZ(Y2) LN0(C2) LN0(Y2) LN1(C2) LN1(Y2) HD-SDI Link A (-bit) HD-SDI Link B (-bit) November 2012 Altera Corporation SDI II MegaCore Function
1 4 Chapter 1: SDI II MegaCore Function Overview Resource Utilization Figure 1 4 shows a block diagram of the level B to level A conversion. Figure 1 4. Implementation of Level B to Level A Conversion 3-GB Receiver rx_clkout (148.5 MHz) 3-GB Signal Transceiver rxdata Protocol rxdata[19:0] rx_trs 3-GB Demux rx_dataout[19:0] rx_dataout_b[19:0] FIFO wrreq rx_clkin_smpte372 (148.5 MHz) rx_dataout[19:0] rx_dataout_b[19:0] rdclk_3gb_div2 = 1H1L1H1L xcvr_refclk (148.5 MHz) rx_clkout (148.5 MHz) rx_trs rx_clkout (148.5 MHz) rxdata[19:0] rxdata[9:0] rx_trs C1 Y1 C1 Y1 C1 Y1 C1 Y1 C2 Y2 C2 Y2 C2 Y2 C2 Y2 rx_clkdiv2 rx_dataout[19:0] rx_dataout[9:0] rx_dataout_b[19:0] rx_dataout_b[9:0] rx_clkin_smpte372 (74.25 MHz) Y1 Y1 Y1 Y1 C1 C1 C1 C1 Y2 Y2 Y2 Y2 C2 C2 C2 C2 Resource Utilization Table 1 2 lists the typical resource utilization for each functional submodule of the SDI II MegaCore function with the Quartus II software, version 12.1. 1 The resource utilization of the MegaCore function is based on the bidirectional interface settings unless otherwise specified. Table 1 2. Resource Utilization For Each Submodule (Part 1 of 2) Submodule Combinational ALUTs Logic Registers Block Memory Bits Insert Line 13 11 0 Insert CRC 44 29 0 Insert VPID 4 78 0 Tx Match TRS 25 16 0 Scrambler 54 31 0 Tx Sample 123 24 0 Generate Clock Enable 7 5 0 Rx Sample 241 135 0 Detect Video Standard 84 74 0 Detect 1 and 1/1.001 Rates 76 67 0 Transceiver Controller 200 140 0 Descrambler 40 31 0 SDI II MegaCore Function November 2012 Altera Corporation
Chapter 1: SDI II MegaCore Function Overview 1 5 Resource Utilization Table 1 2. Resource Utilization For Each Submodule (Part 2 of 2) Submodule Combinational ALUTs Logic Registers Block Memory Bits TRS Aligner 446 597 0 Rx Match TRS 20 16 0 3Gb Demux 29 94 0 3Gb Demux (level B to level A conversion) 158 321,752 Extract Line 3 18 0 Check CRC 41 19 0 Extract VPID 81 114 0 Detect Format 264 169 0 Sync Streams 141 185 1,312 Sync Streams (level A to level B conversion) 205 376 2,336 November 2012 Altera Corporation SDI II MegaCore Function
1 6 Chapter 1: SDI II MegaCore Function Overview Resource Utilization SDI II MegaCore Function November 2012 Altera Corporation
2. Getting Started Installation and Licensing To evaluate the SDI II MegaCore function using the OpenCore Plus feature, follow these steps in your design flow: 1. Install the SDI II MegaCore function. 2. Create a custom variation of the SDI II MegaCore function. 3. Implement the rest of your design using the design entry method of your choice. 4. Use the IP functional simulation model to verify the operation of your design. 5. Compile your design in the Quartus II software. You can also generate an OpenCore Plus time-limited programming file, which you can use to verify the operation of your design in hardware. 1 For more information on IP functional simulation models, refer to the Simulating Altera Designs chapter in volume 3 of the Quartus II Handbook. The default installation directory for the SDI II MegaCore function on Windows is c:\altera\<version>; on Linux, it is /opt/altera<version>. You can obtain a license for the MegaCore function only when you are completely satisfied with its functionality and performance, and want to take your design to production. After you purchase a license for the SDI II MegaCore function, follow these steps: 1. Set up licensing. 2. Generate a programming file for the Altera device or devices on your board. 3. Program the Altera device or devices with the completed design. OpenCore Plus Evaluation With Altera s free OpenCore Plus evaluation feature, you can perform the following actions: Simulate the behavior of a megafunction (Altera MegaCore function or AMPP SM megafunction) within your system. Verify the functionality of your design and quickly evaluate its size and speed with ease. Generate time-limited device programming files for designs that include MegaCore functions. Program a device and verify your design in hardware. f For more information about OpenCore Plus hardware evaluation using the SDI, refer to OpenCore Plus Time-Out Behavior on page 3 38 and AN 320: OpenCore Plus Evaluation of Megafunctions. November 2012 Altera Corporation SDI II MegaCore Function
2 2 Chapter 2: Getting Started Design Walkthrough Design Walkthrough This walkthrough explains how to create an SDI II MegaCore function design using the MegaWizard Plug-In Manager and the Quartus II software. After you generate a custom variation of the SDI II MegaCore function, you can incorporate it into your overall project. This walkthrough requires the following steps: 1. Creating a New Quartus II Project 2. Launching MegaWizard Plug-In Manager 3. Parameterizing the MegaCore Function 4. Generating a Design Example and Simulation Testbench 5. Simulating the Design Creating a New Quartus II Project Table 2 1. Creating a New Quartus II Project From the Windows Start menu, choose Programs > Altera > Quartus II <version> to run the Quartus II software. Alternatively, you can use the Quartus II Web Edition software. You need to create a new Quartus II project with the New Project Wizard, which specifies the working directory for the project, assigns the project name, and designates the name of the top-level design entity. On the File menu, click New Project Wizard. To create a new project, follow the steps in Table 2 1. Click Next to move to the following pages. Step Page Field and Entry Note 1 2 3 New Project Wizard: Introduction New Project Wizard: Directory, Name, Top-Level Entity New Project Wizard: Add Files (1) N/A Directory: c:\altera\projects\sdi_project Project name: project Top-level entity: project File name: <path>\ip\altera\sdi_ii The introduction page does not display if you turned it off previously. This is an example for the directory name. This walkthrough uses project for the project name. The Quartus II software automatically specifies a top-level design entity that has the same name as the project. This walkthrough assumes that the names are the same. <path> is the directory in which you installed the SDI II MegaCore function. 4 New Project Wizard: Family & Device Settings Family Choose your target device family from the list. 5 EDA Tool Settings Tool Name Choose the tools you want to use from the list. Note to Table 2 1: (1) You must add the user libraries if you installed the MegaCore IP Library in a different directory from where you installed the Quartus II software. The last page in the New Project Wizard shows the summary your settings. Click Finish to complete the Quartus II project creation. SDI II MegaCore Function November 2012 Altera Corporation
Chapter 2: Getting Started 2 3 Design Walkthrough Launching MegaWizard Plug-In Manager To launch the MegaWizard Plug-In Manager in the Quartus II software, follow these steps: 1. On the Tools menu, click MegaWizard Plug-In Manager. 2. Select Create a new custom megafunction variation and click Next. 3. Select your target device family from the list. 4. Expand the Interfaces > SDI folder and click SDI II <version>. 5. Select the output file type for your design; the wizard supports VHDL and Verilog HDL. 6. Affix a variation name for the MegaCore function output files <project path>\<variation name>. The MegaWizard Plug-In Manager shows the project path that you specified in the New Project Wizard. 7. Click Next to display the SDI II MegaCore function parameter editor. Parameterizing the MegaCore Function To parameterize your MegaCore function, follow these steps: 1. Select the video standard. 2. Select Bidirectional, Transmitter, or Receiver interface direction. 3. Select Combined, Transceiver, or Protocol. 4. Turn on the necessary receiver options. 5. Turn on the necessary transmitter options. 6. Click Finish. For more information about the parameters, refer to MegaCore Parameters on page 2 9. Generating a Design Example and Simulation Testbench After parameterizing your MegaCore function, the Quartus II software prompts you with a message, which indicates that you can also generate a design example, in addition to generating the MegaCore component files. To generate a design example, check the Generate Example Design option to create the following entities: design example serves as a common entity for simulation and hardware verification. simulation testbench consists of the design example entity and other non-synthesizable components. The testbench components are parameterized according to your selection to demonstrate various features. 1 Generating a design example can significantly increase processing time. November 2012 Altera Corporation SDI II MegaCore Function
2 4 Chapter 2: Getting Started Design Walkthrough Design Examples Figure 2 1 illustrates the generated design example entity and simulation testbench. The design example entity is synthesizable and consists of a video pattern generator, reconfiguration IP, reconfiguration management, loopback path, and various SDI blocks occupying two transceiver channels. One of the SDI block is the device under test (DUT), which is configured according to your parameterization. The rest of the SDI blocks are test instances for a complete serial loopback simulation. For example, if you choose to generate SDI RX, the software instantiates an SDI TX block to serve as a video source. The loopback block (SDI duplex) is always instantiated in the design example for parallel loopback demonstration. Figure 2 1. Design Example Entity and Simulation Testbench Testbench Design Example Loopback Path Ch0 Loopback (SDI Duplex) Transceiver Reconfiguration Controller Reconfiguration Management/Router RX Checker Ch1 Test (SDI RX) Test Control Pattern Generator Ch1 DUT (SDI TX) TX Checker Data SDI II MegaCore Function Control Transceiver Reconfiguration Controller SDI II MegaCore Function November 2012 Altera Corporation
Chapter 2: Getting Started 2 5 Design Walkthrough Figure 2 2 illustrates the generated design example entity and simulation testbench if you choose to generate HD SDI dual link receiver with level A to level B conversion option enabled. Figure 2 2. Design Example Entity and Simulation Testbench for Level A to Level B Conversion Testbench Design Example Loopback Path Ch0 Loopback (SDI Duplex) Transceiver Reconfiguration Controller Reconfiguration Management/Router Test Control Pattern Generator Ch1 Test (HD DL SDI TX) Loopback Path Ch1 DUT (HD DL SDI RX) A to B Ch2 Test (3-Gb SDI TX) RX Checker Ch2 Test (3-Gb SDI RX) TX Checker Data Control SDI II MegaCore Function Transceiver Reconfiguration Controller November 2012 Altera Corporation SDI II MegaCore Function
2 6 Chapter 2: Getting Started Design Walkthrough Figure 2 3 illustrates the generated design example entity and simulation testbench when you choose to generate 3G SDI or triple rate SDI receiver with level B to level A conversion option enabled. Figure 2 3. Design Example Entity and Simulation Testbench for Level B to Level A Conversion Testbench Design Example Loopback Path Ch0 Loopback (SDI Duplex) Transceiver Reconfiguration Controller Reconfiguration Management/Router Test Control Pattern Generator Ch1 Test (3-Gb SDI TX) Loopback Path Ch1 DUT (3-Gb SDI RX) B to A Ch2 Test (HD DL SDI TX) RX Checker Ch2 Test (HD DL SDI RX) TX Checker Data Control SDI II MegaCore Function Transceiver Reconfiguration Controller SDI II MegaCore Function November 2012 Altera Corporation
Chapter 2: Getting Started 2 7 Design Walkthrough Video Pattern Generator The video pattern generator generates a colorbar or pathological pattern. The colorbar pattern is preferable for image generation while the pathological pattern can stress the PLL and cable equalizer of attached video equipment. You can configure the video pattern generator to generate various video formats. Table 2 2 lists the examples of how to configure the video pattern generator signals to generate a video format you desire. Table 2 2. Generate Various Video Formats Using Video Pattern Generator Video Signal Interface Format pattgen_tx_std pattgen_tx_format pattgen_dl_mapping Example 1: Generate 80i video format 80i60 HD-SDI 2'b01 4'b00 1'b0 80i60x2 HD-SDI dual link 2'b01 4'b00 1'b0 3Gb 2'b 4'b00 1'b0 Example 2: Generate 80p video format 80p30 HD-SDI 2'b01 4'b10 1'b0 80p30x2 HD-SDI dual link 2'b01 4'b10 1'b0 80p60 HD-SDI dual link 2'b01 4'b10 1'b1 3Ga 2'b11 4'b10 1'b0 3Gb 2'b 4'b10 1'b1 f For more information about the video pattern generator signals, refer to Video Pattern Generator Signals on page 2 11. Transceiver Reconfiguration Controller The dual and triple rate SDI receivers (or receivers of duplex SDIs) require the transceiver dynamic reconfiguration feature to perform auto detection and locking to different SDI video rates. Transceiver dynamic reconfiguration reconfigures the transceivers to support the three SDI video standards (SD, HD and 3G). The dual and triple rate SDI use 11 times oversampling for receiving SD-SDI standard. Hence, you require only two transceiver configurations as the rates for 3G-SDI and SD-SDI are the same. To perform transceiver dynamic reconfiguration, you need the transceiver reconfiguration controller and reconfiguration management/router blocks. The transceiver reconfiguration controller allows you to change the device transceiver settings at any time. Any portion of the transceiver can be selectively reconfigured. Each portion of the reconfiguration requires a read-modify-write operation (read first, then write), in such a way by modifying only the appropriate bits in a register and not changing other bits. Prior to this operation, you must define the logical channel number and the streamer module mode. November 2012 Altera Corporation SDI II MegaCore Function
2 8 Chapter 2: Getting Started Design Walkthrough You can perform the transceiver dynamic reconfiguration in these modes: streamer module mode 1 (manual mode) execute a series of Avalon-MM write operation to change the transceiver settings. In this mode, you can execute a write operation directly from the reconfiguration management/router interface to the device transceiver registers. streamer module mode 0 use the.mif files to change the transceiver settings. f For more information about the transceiver reconfiguration controller streamer module, refer to the Altera Transceiver PHY IP Core. For read operation, after defining the logical channel number and the streamer module mode, follow these steps: 1. Define the transceiver register offset in the offset register. 2. Read the data register. Toggle the read process by setting bit 1 of the control and status register (CSR) to logic 1. Once the busy bit in the CSR is cleared to logic 0, it indicates that the read operation is complete and the required data should be available for reading. For write operation, after setting the logical channel number and the streamer module mode, follow these steps: 1. Define the transceiver register offset (in which the data will be written to) in the offset register. 2. Write the data to the data register. Toggle the write process by setting bit 0 of the CSR to logic 1. Once the busy bit in the CSR is cleared to logic 0, it indicates that the transceiver register offset modification is successful. f For more information about the transceiver reconfiguration controller signals, refer to Transceiver Reconfiguration Controller Signals on page 2 12. Simulating the Design After design generation, the files located in the <variation name>_example_design/sdi_ii/simulation directory are available for you to simulate your design. To simulate the design using the ModelSim -Altera simulator, follow these steps: 1. Start the ModelSim-Altera simulator. 2. On the File menu, click Change Directory > Select <variation name>_example_design/sdi_ii/simulation 3. On the File menu, click Load > Macro file. Select run_sim.tcl. This file compiles the design and runs the simulation automatically, providing a pass/fail indication on completion. SDI II MegaCore Function November 2012 Altera Corporation
Chapter 2: Getting Started 2 9 Compiling the Design Compiling the Design You can use the Quartus II software to compile your design. For instructions about performing compilation, refer to Quartus II Help. You can find the design examples of a SDI II MegaCore function in the <variation name>_example_design/sdi_ii/example_design/sdi_ii_0001_example_desi gn directory. For the design example illustrations, refer to Design Examples on page 2 4. 1 To create a new project using a generated design example, follow the steps in Creating a New Quartus II Project on page 2 2 and add the design example.qip file in step 3. Programming a Device After compiling the design example, you can program your targeted Altera device to verify the design in hardware. With Altera's free OpenCore Plus evaluation feature, you can evaluate the SDI II MegaCore function before you obtain a license. OpenCore Plus evaluation allows you to generate an IP functional simulation model and produce a time-limited programming file. f For more information about OpenCore Plus hardware evaluation using the SDIIIMegaCore function, refer to AN 320: OpenCore Plus Evaluation of Megafunctions. Design Reference This section lists the parameters, signals, and files to help you configure your design. MegaCore Parameters Table 2 3 lists the parameters available in the SDI II MegaCore function. Table 2 3. SDI II MegaCore Function Parameters Parameter Value Description Configuration Options Video Standard SD SDI, HD SDI, 3G SDI, HD SDI Dual Link, Dual Standard, Triple Standard Sets the video standard. SD-SDI disables option for line insertion and extraction, and CRC generation and extraction HD-SDI enables option for in line insertion and extraction and CRC generation and extraction Dual or triple standard SDI includes the processing blocks for both SD-SDI and HD-SDI standards. Logics for bypass paths and to automatically switch between the input standards are included. November 2012 Altera Corporation SDI II MegaCore Function
2 Chapter 2: Getting Started Design Reference Table 2 3. SDI II MegaCore Function Parameters Parameter Value Description Direction Transceiver and/or Protocol Receiver Options Increase error tolerance level CRC error output Extract Video Payload ID (SMPTE 352M) Convert level A to level B (SMPTE 372M) Convert level B to level A (SMPTE 372M) Transmitter Options Two times oversample mode for HD-SDI Insert Video Payload ID (SMPTE 352M) Bidirectional, Receiver, Transmitter Combined, Transceiver, Protocol On Off On Off On Off On Off On Off On Off On Off Sets the port direction. The selection enables or disables the receiver and transmitter supporting logic appropriately. Bidirectional instantiates the transceiver (altera_xcvr_custom) in duplex mode. Receiver and transmitter instantiates the transceiver (altera_xcvr_custom) in a separate receiver and transmitter mode respectively. Selects the components. Transceiver includes tx/rx_phy_mgmt/phy_adapter and hard transceiver. This option is useful if you would like to use the same transceiver component to support both SDI and ASI. Protocol On: Error tolerance level = 15 Off: Error tolerance level = 4 Turn on this option to increase the error tolerance level for consecutive missed end of active videos (EAVs), start of active videos (SAVs), or erroneous frames. On: CRC monitoring (Not applicable for SD-SDI mode) Off: No CRC monitoring (saves logic) On: Extract VPID Off: No VPID extraction (saves logic) It is compulsory to turn on this option for 3G-SDI, HD SDI dual link, and triple standard modes. The extracted VPID is required for consistent detection of the 80p format. It is compulsory to turn on this option for the design example demonstration when you enable either the Convert level A to level B (SMPTE 372M) or Convert level B to level A (SMPTE 372M) option. On: Convert level A (direct image format mapping) to level B (2 x SMPTE 292M HD- SDI mapping, including SMPTE 372M dual link mapping) for HD dual link receiver output. Off: No conversion This option is only available for HD-SDI dual link receiver. On: Convert level B (2 x SMPTE 292M HD-SDI mapping including SMPTE 372M dual link mapping) to level A (direct image format mapping) for 3G-SDI or triple standard SDI receiver output. Off: No conversion This option is only available for 3G-SDI and triple standard SDI receiver. On: Run the hard transceiver at twice the rate with improved jitter performance. This requires a 148.5-MHz or 148.35-MHz transceiver reference clock, xcvr_refclk. Off: No two times oversampling This option is only available for HD-SDI standard. On: Insert VPID Off: No VPID insertion (saves logic) SDI II MegaCore Function November 2012 Altera Corporation
Chapter 2: Getting Started 2 11 Design Reference MegaCore Component Files Table 2 4. Generated Files Table 2 4 describes the generated files and other files that might be in your project directory. The names and types of files in the MegaWizard Plug-In Manager report vary depending on whether you create your design with VHDL or Verilog HDL. Extension <variation name>.v or.sv <variation name>.sdc <variation name>.qip <variation name>.tcl Description A MegaCore function variation file, which defines a Verilog HDL description of the custom MegaCore function. Instantiate the entity defined by this file inside your design. Include this file when compiling your design in the Quartus II software. Contains timing constraints for your SDI variation. Contains Quartus II project information for your MegaCore function variations. Tcl script file to run in Quartus II software. Video Pattern Generator Signals Table 2 5 lists the input signals of the video pattern generator. The listed signals are exported at the top level of the design example. Other signals that are not exported connects within the design example entity. Table 2 5. Video Pattern Generator Top Level Signals Signal Width Direction Description pattgen_tx_std 2 Input pattgen_tx_format 4 Input pattgen_dl_mapping 1 Input Transmit video standard. 00: SD-SDI 01: HD-SDI or HD-SDI dual link : 3G-SDI level B 11: 3G-SDI level A Transmit video format. 0000: SMPTE259M 525i 0001: SMPTE259M 625i 00: SMPTE274M 80i60 01: SMPTE274M 80i50 01: SMPTE274M 80p24 0111: SMPTE296M 720p60 00: SMPTE296M 720p50 01: SMPTE296M 720p30 : SMPTE296M 720p25 11: SMPTE296M 720p24 10: SMPTE274M 80p30 11: SMPTE274M 80p25 Others: Reserved for future use Dual link mapping. Set to 1 for HD-SDI dual link and 3Gb transmit video standard only. November 2012 Altera Corporation SDI II MegaCore Function
2 12 Chapter 2: Getting Started Design Reference Table 2 5. Video Pattern Generator Top Level Signals Signal Width Direction Description Transmit rate. Transceiver Reconfiguration Controller Signals 0: PAL (1) rate. For example, 80p30 1: NTSC (1/1.001) rate. For example, pattgen_ntsc_paln 1 Input 80p29.97 This input ignores all SD video formats (525i, 625i) and certain HD video formats that do not support NTSC rate (80i50, 720p50, 720p25, 80p25). pattgen_bar_0_75n 1 Input 0: 75% colorbars 1: 0% colorbars pattgen_patho 1 Input Set to 1 to generate pathological pattern. pattgen_blank 1 Input Set to 1 to generate black signal. pattgen_no_color 1 Input Set to 1 to generate bars with no color. Table 2 6 lists the input signals requirement of the transceiver reconfiguration controller. The listed signals are exported at the top level of the design example. Other signals that are not exported connects within the design example entity. Table 2 6. Transceiver Reconfiguration Controller Top Level Signals Signal Width Direction Description reconfig_clk 1 Input reconfig_rst 1 Input Clock signal for the transceiver reconfiguration controller and reconfiguration management/router. The frequency range is 0 125 MHz. Reset signal for the transceiver reconfiguration controller and reconfiguration management/router. This signal is active high and level sensitive. SDI II MegaCore Function November 2012 Altera Corporation
3. Functional Description The SDI II MegaCore function implements a transmitter, receiver, or full-duplex interface. The SDI II MegaCore function consists of the following components: Protocol block transmitter or receiver Transceiver blocks PHY management & adapter Hard transceiver In the MegaWizard Plug-In Manager, you can specify either protocol, transceiver, or combined blocks for your design. For example, if you have multiple protocol blocks in a design, you can multiplex them into one transceiver. The modular hierarchy design allows you to remove or reuse each submodule within the components across different video standards. The transmitter and receiver data paths are independent from each other. Protocol The protocol block handles the SDI-specific parts of the core and generally operates on a parallel domain data. Transmitter The transmitter performs the following functions: HD-SDI LN insertion HD-SDI CRC generation and insertion VPID insertion Matching TRS word Clock enable signal generation Scrambling and non-return-zero inverted (NRZI) coding The block diagrams below illustrate the SDI II MegaCore function transmitter (simplex) data path for each supported video standard. f For more information about the function of each submodules, refer to Submodules on page 3 8. November 2012 Altera Corporation SDI II MegaCore Function
3 2 Chapter 3: Functional Description Protocol Figure 3 1 shows the SD-SDI transmitter data path. Figure 3 1. SD-SDI Transmitter Data Path Block Diagram Match TRS TX Protocol TX PHY Management & PHY Adapter Transceiver Parallel Video In Insert VPID TX Scrambler Oversample 20 Altera XCVR Custom (Tx) SDI Out Transmit Generate Clock Enable Figure 3 2 shows the HD/3G-SDI transmitter data path. Figure 3 2. HD/3G-SDI Transmitter Data Path Block Diagram TX PHY Management & PHY Adapter Match TRS TX Protocol Transceiver Parallel Video In Demultiplexer Y 20 Insert Line Insert CRC C Insert Insert Line CRC Insert VPID Multiplexer 20 Scrambler 20 Altera XCVR Custom (Tx) SDI Out Transmit Figure 3 3 shows the dual rate SDI transmitter data path. Figure 3 3. Dual Rate SDI Transmitter Data Path Block Diagram Match TRS TX Protocol TX PHY Management & PHY Adapter Transceiver Parallel Video In Demultiplexer Multiplexer Y (HD) Insert Line Insert CRC Insert VPID 20 C (HD) or CY (SD) Insert Insert Insert 20 Line CRC VPID Transmit Scrambler TX 20 Oversample 20 Generate Clock Enable Altera XCVR Custom (Tx) SDI Out SDI II MegaCore Function November 2012 Altera Corporation
Chapter 3: Functional Description 3 3 Protocol Figure 3 4 shows the triple rate SDI transmitter data path. Figure 3 4. Triple Rate SDI Transmitter Data Path Block Diagram Parallel Video In Demultiplexer 20 Y or Y Link A (3 Gb) Match TRS Insert Line TX Protocol Insert CRC C Link B (3 Gb) Insert Insert Line CRC Insert VPID C or Y Link B (3 Gb) Insert Line Insert CRC Insert VPID C Link A (3 Gb) Insert Insert Line CRC Multiplexer 20 Scrambler TX PHY Management & PHY Adapter TX 20 Oversample 20 Generate Clock Enable Transceiver Altera XCVR Custom (Tx) SDI Out Match TRS Transmit Figure 3 5 shows the dual link HD-SDI transmitter data path. Figure 3 5. Dual Link HD-SDI Transmitter Data Path Block Diagram TX PHY Management & PHY Adapter Match TRS TX Protocol Transceiver Parallel Video In Link A Demultiplexer Y 20 Insert Line Insert CRC C Insert Insert Line CRC Insert VPID Multiplexer 20 Scrambler 20 Altera XCVR Custom (Tx) SDI Out Link A Transmit Match TRS TX Protocol Parallel Video In Link B Demultiplexer Y 20 Insert Line Insert CRC C Insert Insert Line CRC Insert VPID Multiplexer 20 Scrambler 20 Altera XCVR Custom (Tx) SDI Out Link B Transmit November 2012 Altera Corporation SDI II MegaCore Function
3 4 Chapter 3: Functional Description Protocol Receiver The receiver performs the following functions: Video standard detection Video rate detection NRZI decoding and descrambling Word alignment Demultiplex data links Video timing flags extraction HD-SDI LN extraction HD-SDI CRC VPID extraction Synchronizing data streams Accessing transceiver Identifying and tracking of ancillary data The block diagrams below illustrate the SDI II MegaCore function receiver (simplex) data path for each supported video standard. Figure 3 6 shows the SD-SDI receiver data path. Figure 3 6. SD-SDI Receiver Data Path Block Diagram RX Protocol RX PHY Management & PHY Adapter Transceiver Detect Format Parallel Video Out Extract Match TRS VPID TRS Aligner Descrambler Transceiver Control State Machine RX Oversample 20 Avalon-MM Altera XCVR Custom (Rx) SDI In Receive SDI II MegaCore Function November 2012 Altera Corporation
Chapter 3: Functional Description 3 5 Protocol Figure 3 7 shows the HD-SDI receiver data path. Figure 3 7. HD-SDI Receiver Data Path Block Diagram RX PHY Management & PHY Adapter Transceiver Detect Format Receive RX Protocol Parallel Y Extract Check Extract Match Video VPID CRC Line TRS Out TRS 20 C 20 Aligner 20 Check CRC Multiplexer Demultiplexer Descrambler Transceiver Control State Machine 20 Detect 1 & 1/1,001 Rate Avalon-MM Altera XCVR Custom (Rx) SDI In Figure 3 8 shows the 3G-SDI receiver data path. Figure 3 8. 3G-SDI Receiver Data Path Block Diagram RX PHY Management & PHY Adapter Transceiver Detect Format RX Protocol Y or Y Link A (3 Gb) C or C Link A (3 Gb) Parallel Video Out Y Link B (3 Gb) Extract VPID Extract Line Y Match TRS TRS 20 20 Aligner 20 Extract VPID Check CRC Check CRC Check CRC Extract Line C Match TRS Descrambler Transceiver Control State Machine 20 Detect 1 & 1/1,001 Rate Avalon-MM Altera XCVR Custom (Rx) SDI In C Link B (3 Gb) Check CRC Multiplexer Receive 3 Gb Demultiplexer November 2012 Altera Corporation SDI II MegaCore Function
3 6 Chapter 3: Functional Description Protocol Figure 3 9 shows the dual rate SDI receiver data path. Figure 3 9. Dual Rate SDI Receiver Data Path Block Diagram Detect Format Receive RX Protocol Parallel Y (HD) Extract Check Extract Match Video VPID CRC Line TRS Out TRS C (HD) 20 20 Aligner 20 Check or CY (SD) CRC Multiplexer Demultiplexer Descrambler RX PHY Management & PHY Adapter Transceiver Control State Machine RX 20 Oversample 20 Detect Video Standard Detect 1 & 1/1,001 Rate Transceiver Avalon-MM Altera XCVR Custom (Rx) SDI In Figure 3 shows the triple rate SDI receiver data path. Figure 3. Triple Rate SDI Receiver Data Path Block Diagram Y or Y Link A (3 Gb) C or C Link A (3 Gb) Parallel Video Out Y Link B (3 Gb) C Link B (3 Gb) Detect Format Extract VPID RX Protocol TRS 20 20 Aligner 20 Extract VPID Multiplexer Check CRC Check CRC Check CRC Extract Line Extract Line Y Match TRS Receive C Match TRS Check CRC 3 Gb Demultiplexer Descrambler RX PHY Management & PHY Adapter Transceiver Control State Machine RX 20 Oversample 20 Detect Video Standard Detect 1 & 1/1,001 Rate Transceiver Avalon-MM Altera XCVR Custom (Rx) SDI In SDI II MegaCore Function November 2012 Altera Corporation
Chapter 3: Functional Description 3 7 Protocol Figure 3 11 shows the dual link HD-SDI receiver data path. Figure 3 11. Dual Link HD-SDI Receiver Data Path Block Diagram RX Protocol RX PHY Management & PHY Adapter Transceiver 20 Parallel Video Out Sync 40 Streams Detect Format Extract VPID Multiplexer Check CRC Check CRC Extract Line Receive Y Match TRS C 20 TRS Aligner Demultiplexer 20 Descrambler Transceiver Control State Machine 20 Detect 1 & 1/1,001 Rate Avalon-MM Altera XCVR Custom (Rx) SDI In Detect Format Y Extract Check Extract Match VPID CRC Line TRS 20 TRS C 20 Aligner Check 20 CRC Multiplexer Demultiplexer Receive Descrambler Transceiver Control State Machine 20 Detect 1 & 1/1,001 Rate Avalon-MM Altera XCVR Custom (Rx) SDI In November 2012 Altera Corporation SDI II MegaCore Function
3 8 Chapter 3: Functional Description Transceiver For bidirectional or duplex mode, the protocol and PHY management & adapter blocks remain the same for each direction, except the hard transceiver, which is configured in duplex mode. Figure 3 12 illustrates the data path of a SD-SDI duplex mode. Figure 3 12. SD-SDI Duplex Data Path Block Diagram Match TRS TX Protocol TX PHY Management & PHY Adapter Transceiver Parallel Video In Insert VPID TX Scrambler Oversample 20 Transmit Generate Clock Enable Altera XCVR Custom (Duplex) SDI Out RX Protocol RX PHY Management & PHY Adapter Detect Format Parallel Video Out Extract VPID Match TRS TRS Aligner Descrambler Transceiver Control State Machine Avalon-MM RX Oversample 20 SDI In Receive Transceiver f Submodules The transceiver block consists of two components PHY management & adapter and hard transceiver. These two components handle the serial transport aspects of the SDI. The hard transceiver is the Altera Custom PHY IP Core. The SDI II MegaCore function instantiates the Custom PHY IP Core using a Tcl file, altera_xcvr_custom_hw.tcl. For more information about the Custom PHY IP Core, refer to the Altera Transceiver PHY IP Core. You can reuse the submodules in the protocol and transceiver components across different video standard. The SDI II MegaCore function contains the following submodules: Insert Line Insert/Check CRC Insert VPID Match TRS Scrambler SDI II MegaCore Function November 2012 Altera Corporation
Chapter 3: Functional Description 3 9 Submodules Insert Line Tx Oversample Rx Oversample Detect Video Standard Detect 1 & 1/1.001 Rates Transceiver Controller Descrambler TRS Aligner 3Gb Demux Extract Line Extract VPID Detect Format Sync Streams The HD-SDI has the option to include line numbers along with the video data. This information is in the EAV extension words of the data stream as defined in the SMPTE292M specification. The line number is 11 bits wide and spreads over two SDI words to utilize the SDI legal data space. This submodule takes the 11 bits line number data value, correctly encodes them, and inserts them into the -bit stream. The line number value is user-defined. The top level port signal is tx_ln[:0] and tx_ln_b[:0] for link B in 3G and HD dual link modes. You also have the option to enable or disable this feature using the tx_enable_ln signal on the top level port. The same line number value is inserted into both video channels. Two of these submodules are required for Y and C channels. The Match TRS submodule indicates to this submodule when to insert the values into the stream. Figure 3 13 illustrates the line number insertion and signal requirements. For correct line insertion, assert the tx_trs signal for the first word of both EAV and SAV TRS. Figure 3 13. Line Number Insertion and Signal Requirements INPUT DATA 3 FF 000 000 XYZ LN0 LN1 CRC0 CRC1 TX_LN XXX VALID XXX TX_TRS Insert/Check CRC The HD-SDI can optionally include a line-based CRC code, which makes up two of the EAV extension words as defined in the SMPTE292M specification. November 2012 Altera Corporation SDI II MegaCore Function