GHz Sampling Design Challenge

GHz Sampling Design Challenge 1 National Semiconductor Ghz Ultra High Speed ADCs Target Applications Test & Measurement Communications Transceivers Ranging Applications (Lidar/Radar) Set-top box direct RF down-conversion Highest Performance Highest Dynamic Performance Lowest Power Consumption Innovative Packaging technology Wide Bandwidth 2

8bit GSPS Family Single Channel ADC083000 3 GHz BW DDR, SBI ADC08B3000 4K Buffer w/cmos outputs Today http://www.national.com/appinfo/adc/ghz_adc.html Dual Channel ADC08D1500 ADC08D1520 2 GHz BW DES, DDS, SPI SPEED ADC081500 ADC081000 ADC08D1000 ADC08D1020 2 GHz BW DES, DDR, SPI ADC08500 ADC08D500 3 Digital Oscilloscope Block Diagram Key pad Ch 1 JFET Buff LMH6702 /3 Mux LMH6570 VGA LMH6515 /LMH6505 Diff LMH6555/6552 Display ADC08D1000/A DC08D1500 CPU VCM Ch 2 JFET DAC DAC DAC Trigger + _ + _ LMH7220/ LMH7322 PLL+VCO LMX2531 Memory FPGA Power DAC Trigger DAC124S101 4

The Clock Circuitry ADC08Dxxx Circuit Design Considerations 5 Clock Jitter Jitter: cycle-to-cycle variation in timing Input Signal Sample amplitude variation due to Jitter Result: Output noise Clock Jitter ADC clock 6

Effect of Jitter Sampled with clean Clock Sampled with Jittery Clock 7 High-Speed ADC Clock Considerations Maximum allowable jitter to prevent noise degradation: t j max = V IN(P-P) 2 (n+1) * V FS * π * f in ADC Resolution & Signal input frequency have directly effect upon jitter-induced noise 8

Data Converter ENOB Full Scale Input Bandwidth vs. Total Jitter 0.001 Full Scale Input Frequency (MHz) 10 100 1000 10000 Jitter (ps) 0.010 0.100 1.000 0.33 ps RMS Jitter 169 MHz Input to ADC 16-Bit 14-Bit 12-Bit 10-Bit To realize 12-bits of resolution for the ADC12DS065, the total aperture jitter must be less than 0.33 ps. 9 System Requirement to Clock Jitter 10

Spectral Considerations Spurs that extend to higher frequencies may be visible and directly impact system jitter 11 LMX2531LQ1500E Simplifies the PLL+VCO clock system Y1 CLK OSC C1 100pF Crystek R2 # CCHD-950-25-60 150 60 MHz SDATA SCLK PLL_LE PLL_CE R3 39 C150 100pF C166 100nF C2 100nF R4 150 3.3V R20 14.3k R23 2.2k C8 10nF 3.0V 1 2 3 4 5 6 7 8 9 3.3V C3 1uF R5 49.9 C25 C17 100nF 100nF C4 100nF C6 100nF 36 35 34 33 32 31 30 29 28 3.0V C9 0.47uF U3 LMX2531LQ1500E 10 11 12 13 14 15 16 17 18 C18 4.7uF R11 3.3k * R12 & R13 is populated only for the ADC083000 and the ADC08B3000 R15 is zero Ohms, R12 & R13 are open for others like ADC081500, ADC08D1500, ADC08D1520 R7 0.22 27 26 25 24 23 22 21 20 19 37 38 39 R13 * 100 C19 100nF 3.0V LD Control input from FPGA C10 100pF C11 0.47uF C7 100pF R15 * 71.5 R8 0.22 3.0V R9 12K C16 100pF R12 * 100 R10 1k C12 0.15uF 1:2 Impedance Ratio Balun C13 220pF C14 4.7nF C15 4.7nF To ADC to ADC CLK+ to ADC CLK- 12

LMX2531 Phase Noise and jitter Performance 13 Effects of Time Interleaving 14

Correct Relative Clock Phasing Samples are in the proper place. Sampled Signal CLOCK for ADC1 CLOCK for ADC2 15 Incorrect Relative Clock Phasing Incorrect timing results with incorrect relative clock phasing Sampled Signal CLOCK for ADC1 CLOCK for ADC2 16

Distortion is the Result We get distortion when combining the data from time interleaved converters. Reconstructed Signal Read CLOCK for ADC1 Data Read CLOCK for ADC2 Data 17 ADC08Dxxxx Block Diagram 18

Dual-Edge Sampling (Interleaving) 19 Offset Error Difference Spurs produced at f S /M M is 1 to one less than the number of converters Interleaved ADCs with 3 LSB offset spread (8 bit ADC) 20

Gain Error Difference Spurs at f s ± f IN Interleaved ADCs with 3 LSB Gain Error spread (8bit ADC) 21 DNL Error Differences DNL differences raises the noise floor Interleaved ADCs with DNL Error differences (8bit ADC) 22

Temperature Effect and On Command Calibration ENOB vs. Junction Temperature, 249 MHz Input in ADC08D1000 23 National s Ultra High Speed ADCs Interleaved with Calibration Calibrated ADC08D1500 DES (Dual Edge Sampling) Mode 24

ADC083000 / ADC08D1520/1020 The simplified 6GSPS sampling system Programmable Clock Phase Adjustment Circuitry for external clock is much simplified. 25 ADC083000 / ADC08D1520/1020 Programmable Clock Phase In SPI mode, the customer can program a delay on the ADC input clock to shift the sample clock phase relative to another ADC08B3000 so that two ADCs may be board-interleaved for a higher system sample rate. Ex. 1.25 GHz input clock: 2.5 GSPS per ADC (Auto DES), and now 5 GSPS through interleaving. The phase shift will only be in one direction, eg. increasing delay. The customer should determine which of two discrete ADCs is "ahead" and adjust its phase so that its sample edges are 180º between the other ADC's sample edges, as shown below: ADC1 Input Clock ADC1 Sample Edges ADC2 Input Clock ADC2 Sample Edges Interleaved samples (non-adjusted) Interleaved samples (adjusted) 26

Main Interleaving Challenges Sampling Clock phase adjustment Normally for 2X interleaving ADC clocks must be time shifted by ½ clock period. But because the ADC083000 is an interleaved architecture, the clock frequency is half the sample rate, 1.5 GHz for 3GSPS. Therefore ADC input clock must be time shifted by ¼ clock period. Gain and offset mismatching Gain & offset of each ADC input stage must be accurately matched. Synchronisation of digital outputs ADC digital outputs must be synchronised for data capture. 27 Interleaving Challenges Sampling Clock phase adjustment The clock phase can be adjusted manually through the Coarse & Fine registers (Eh and Dh). Coarse Adjust Magnitude. Each LSB results in approximately 70ps of clock adjust. Fine Adjust Magnitude. 9-bit, 512 steps gives 110ps adjustment so each LSB results gives approximately 0.2ps of non-linear clock adjust. See datasheet for more details 28

Interleaving Challenges : Gain and Offset Mismatching Gain & offset of each ADC input stage must be accurately matched. Up to 512 step adjustments in Full Scale Range over a nominal range of 560 mv to 840 mv. The input full-scale voltage or gain of the ADC can be adjusted linearly and monotonically with a 9-bit data value. The adjustment range is ±20% of the nominal 700 mvp-p differential value. Separate ±45 mv adjustments in 512 steps of offset adjustment range. The input offset of the ADC can be adjusted linearly and monotonically from a nominal zero offset to 45 mv of offset. Thus, each code step provides 0.176 mv of offset. 29 Interleaving Challenges : Synchronisation of Digital Outputs ADC digital outputs must be synchronised for data capture. National Giga-sample series ADCs have the capability to precisely reset its sampling clock input to DCLK output relationship as determined by the user-supplied DCLK_RST pulse. This allows multiple ADCs in a system to have their DCLK (and data) outputs transition at the same time with respect to the shared CLK input that they all use for sampling. 30

The Amplifier Front-End ADC08Dxxx Circuit Design Considerations 31 DC Coupled Design Single Ended Differential Conversion LMH6552, LMH6555 The Test & Measurement industry requires a DC coupled front-end design. The easiest approach is to use a differential amplifier with the appropriate gain bandwidth product and the ability to set the common mode output voltage (VCMO) from an external voltage. 32

More Gain Needed? Adding a Pre-Amplifier to the design Fixed Gain Two Stage Amplifier Input Stage Wide band differential Op-Amps usually have limited gain, so depending on the application it may be necessary to add a pre-amplifier to the design to meet the necessary gain requirement as shown in this slide. 33 LMH6555 1.2 GHz Fully Differential Amplifier Features Current Feedback Amplifier 1.2 GHz bandwidth 51 dbc THD at 750 MHz 15 db noise figure 13.7 db fixed gain DC-Coupled Operation 3.3V operation Ideal match for 8-bit ADCs up to 1.5 GSPS, such as the ADC081000/1500 family Applications High BW Instrumentation Differential ADC driver Single ended to differential converter Intermediate frequency (IF) amplifier Communication receivers Oscilloscope front end 34

LMH6552 1.5 GHz Fully Differential Amplifier 1.5 GHz SSBW (Av=1, RL=1kΩ, 0.2 Vpp) 1.25 GHz LSBW (Av=1, RL=1kΩ, 2Vpp) 450 MHz 0.1dB Flatness 500Ω load or lighter 3850 V/μs Slew Rate 10ns settling time to 0.1% 90 db THD @ 20 MHz -74 db THD @ 70 MHz 10 db Noise Figure Single 5V, +/-3V or +/-5V operation Ideal Driver for 8 to 14 bit High Speed ADCs SOIC-8 and LLP-8 Packages LMH6552 (RL=500Ω) Gain (V/V) SSBW LSBW 2 930 MHz 820 MHz 4 810 MHz 740 MHz 8 590 MHz 590 MHz 35 Trigger Solution : LMH7322 High Speed Comparator w/rspecl Output Separate supplies for level Target Specs / Feature shifting applications ---> RSPECL Output Prop Delay ( 100 mv OD) 750 ps Dispersion (10 mv OD) 75ps Dispersion (100 mv OD) 5ps Rise and Fall Times 150 ps Max Toggle Rate 4Gbps Supply Current ~17.8 ma/ch Adjustable hysteresis 1 mv to100 mv Rail-to-Rail Input Supply Voltage 2.7V to 12V Extended Temp Range -40ºC to +125ºC Package 24-LLP Ch. B Ch. A 36

The Digital Data Capture (into an FPGA) ADC08Dxxx Circuit Design Considerations 37 LVDS Signal Transmission NOTE: Advantages of LVDS LVDS allows for faster signals (smaller swing), Lower EMI and switching noise, Transmit data further 38

About Measurement Description in Specification LVDS Differential and Single Ended Signal measurements. So for example, 700 mv in differential means 350 mv each side. LVDS Data Output Voltage Differential Clock Input Level Measured differentially Defined measured differentially OutV=Va normal amplitude OutV=Gnd smaller amplitude Sine or Square Wave Clock 39 ADC08Dxxxx Block Diagram 40

DDR & SDR 41 FPGA Data Capture Implementation FPGA Internal Clock Manager Data Capture Implementation Block Diagram 42

ADC08D1020/1520 Block Diagram Provide LVDS test mode 1:1 or 1:2 selectable DEMUX FPGA 43 44