JRC ( JTAG Route Controller ) Data Sheet ATLAS TGC Electronics Group September 5, 2002 (version 1.1) Author : Takashi Takemoto Feature * JTAG signal router with two inputs and seven outputs. * Routing arbitration controlled by two auxilia ry JTAG ports. * Instruction and data registers with voting logic for SEU tolerance. * Ring oscillators and shift registers for radiation test purpose. 1. Overview The JRC (JTAG Route Controller) is a switching router, which has two JTAG input ports and seven JTAG output ports with two auxiliary JTAG signals for control as shown in Fig1. The control of two sets of JTAG signals (DA and DB) from Port-A and Port-B is performed by Control JTAG signals (CA and CB), and then the JTAG signals from Port-A and Port-B are connected with one of seven outputs (Q1 Q7) and NC (No Connect), respectively. Normally Control JTAG CA controls the signal route of the Port-A and the Port-B is by CB. Since the JRC does work as a simple passive switch for the signals from the input Port-A and Port-B, the signals pass through the JRC IC and output from one of the output ports as it is at the input ports. When NC or a route that is already occupied by another channel is selected, the JTAG signals (DA or DB) are not connected with any output port and are left at NC. All the JTAG ports consist of five signals: /TRST, TCK, TMS, TDI, TDO. Output ports (Q) that are not selected are keep at high-z states for output signals, i.e. /TRST, TCK, TMS, TDO. In addition to ordinary functions four ring oscillators and four shift registers are included in the IC for radiation test. The ring oscillator consists of 501 NAND gates. The shift register is a master -slave type and consists of 256 flip-flops. JRC 9/5/2002 (Version 1.1 ) 1
Fig 1 : JRC Diagram 2. The detail of JRC design 2.1 JTAG Part In the JRC, all operations and configurations are performed by only the command of CONTROL JTAGs from CA and CB ports. In order to enable independent operations from the both control ports, we implemented two sets of the JTAG protocol logic, which do not interface with each other at all. Boundary-Scan Registers (BSR) are a mandate of the JTAG protocol, however the Boundary-Scan Cell (BSC) is not implemented at any of I/O pins of the JRC chip. We satisfy proper JTAG instructions, i.e. SAMPLE/PRELOAD, EXTEST and INTEST, with a single BSC on the chip as a dummy. The BSC works a 1-bit register, which can be read and written without connection to any I/O pin, as shown in Fig 2. Only at the time of shift, the va lue of TDI is shifted in, and the value of BSC register is shifted out. Fig 2 : BSC Register JRC 9/5/2002 (Version 1.1 ) 2
Though ID_CODE Register (Fig 3) is supported in the JRC, the register is to be loaded by only ID_CODE instruction, not to be loaded in Test Logic Reset state of the Tap Controller (Fig 4). The instruction of ID_CODE is not selected in Test Logic Reset state of the tap controller in the JRC. That does not satisfy the JTAG specification, strictly speaking. Fig 3 : ID CODE Register of JRC Fig 4 : Tap Controller in JRC JRC 9/5/2002 (Version 1.1 ) 3
2.2 Instruction Register The instruction length of JRC is 8 bits, and the data is put in from LSB. Instruction MSB LSB Remarks Indispensable BYPASS 1111_1111 Supported SAMPLE/PRELOAD 0000_0001 Supported* EXTEST 0000_0000 Supported* Option ID_CODE 0000_0100 Supported INTEST 0000_0010 Supported* User Definition READ SELF ROUTE 0001_0000 Read the route of Port-A WRITE SELF ROUTE 0001_0001 Write the route of Port-A READ OTHER ROUTRE 0001_0100 Read the route of Port-B WRITE OTHER ROUTE 0001_0101 Write the route of Port-B READ SEU 0001_1000 Capture Code 0000_0001 (Shift out) Table 1: Instruction of CA Instruction Operation The value read READ SELF ROUTE Read the route of Port-A The route of the present Port-A WRITE SELF ROUTE Write the route of Port-A The route of Port-A before change READ OTHER ROUTE Read the route of Port-B The route of the present Port-B WRITE OTHER ROUTE Write the route of Port-B The route of Port-B before change READ SEU Investigate whether SEU The 1-bit SEU register happens High level : SEU happens Table 2: Description of User Definition in Port-A JRC 9/5/2002 (Version 1.1 ) 4
Instruction MSB LSB Remarks Indispensable BYPASS 1111_1111 Supported SAMPLE/PRELOAD 0000_0001 Supported* EXTEST 0000_0000 Supported* Option ID_CODE 0000_0100 Supported INTEST 0000_0010 Supported* User Definition READ SELF ROUTE 0001_0000 Read the route of Port-B WRITE SELF ROUTE 0001_0001 Write the route of Port-B READ OTHER ROUTRE 0001_0100 Read the route of Port-A WRITE OTHER ROUTE 0001_0101 Write the route of Port-A READ SEU 0001_1000 Capture Code 0000_0001 (Shift out) Table 3: Instruction of CB Instruction Operation The value read READ SELF ROUTE Read the route of Port -B The route of the present Port-B WRITE SELF ROUTE Write the route of Port-B The route of Port-B before change READ OTHER ROUTE Read the route of Port -A The route of the present Port-A WRITE OTHER ROUTE Write the route of Port-A The route of Port-A before change READ SEU Investigate whether SEU The 1-bit SEU register happens High level : SEU happens Table 4: Description of User Definition in Port-B Supported shows that the command is supported. Supported* shows that the command is valid, however the BSRs are not supported in the JRC chip. Capture Code is not an instruction command but a code that comes out from TDO when an instruction command is correctly fed to the instruction register. If the other code is received, the JRC 9/5/2002 (Version 1.1 ) 5
sequence to write the instruction command is wrong. When the JRC receives a command other than listed in the table, the JRC accepts the command although nothing happens. 2.3 JTAG Routing Register The JTAG Routing Regis ters of Port-A and Port-B are summarized in Table 3 and Table 4. The data is fed in from LSB. Route-A Selected Remarks [MSB:LSB] Route [000] NC No Connect [001] Q1 [010] Q2 [011] Q3 [100] Q4 [101] Q5 [110] Q6 [111] Q7 Table 5: Route of Port-A Route-B Selected Remarks [MSB:LSB] Route [000] NC No Connect [001] Q1 [010] Q2 [011] Q3 [100] Q4 [101] Q5 [110] Q6 [111] Q7 Table 6: Route of Port-B JRC 9/5/2002 (Version 1.1 ) 6
2.4 Control Sequence Examples of the control on JTAG signal routings are shown below. Write Self Route (a) The instruction Capture Code is captured in Capture-IR. (b) WRITE_SELF_ROUTE command is loaded in an instruction scan register from TDI using Shift-IR. At the same time, Capture Code is output from TDO. The data is fed in/out (LSB first and MSB last in that order). (c) The instruction in an instruction scan register is parallel-loaded into the instruction register in Update-IR. Then the instruction of WRITE_SELF_ROUTE becomes effective and JTAG Routing Register is chosen as the data register. (d) Current data in JTAG Routing Register is parallel-loaded into the scanning register in Capture -DR. (e) The data to be written in JTAG Routing Register is fed into the scanning register from TDI in Shift-DR. At the same time the data on the scanning register (current data of JTAG Routing Register) is output from TDO. The input from TDI and the output from TDO are shifted in/out from LSB to MSB. (f) The data on the scanning register is parallel-loaded into JTAG Routing Register in Update-DR. Then the JTAG route is selected in accordance with the new data. (g) When a route that is already occupied by another port is written, the data of JTAG Routing Register is set to be NC by force. Verification of the written data is recommended. Fig 5 : Timing of Write Self Route JRC 9/5/2002 (Version 1.1 ) 7
Read Self Route (a) The instruction Capture Code is captured in Capture-IR. (b) READ_SELF_ROUTE command is loaded in an instruction scan register from TDI using Shift-IR. At the same time, Capture Code is output from TDO. The data is fed in/out (LSB first and MSB last in that order). (c) The instruction in an instruction scan register is parallel-loaded into the instruction register in Update-IR. Then the instruction of READ_SELF_ROUTE becomes effective and JTAG Routing Register is chosen as the data register. (d) Current data in JTAG Routing Register is parallel-loaded into the scanning register in Capture -DR. (e) The data of the scanning register is shifted out by 3 bits from TDO in Shift-DR. At the same time, the arbitrary data can be fed to the scanning register from TDI. Fig 6 : Timing of Read Self Route JRC 9/5/2002 (Version 1.1 ) 8
Write Other Route (a) The instruction Capture Code is captured in Capture-IR. (b) WRITE_OTHER_ROUTE command is loaded in an instruction scan register from TDI using Shift-IR. At the same time, Capture Code is output from TDO. The data is fed in/out (LSB first and MSB last in that order). (c) The instruction in an instruction scan register is parallel-loaded into the instruction register in Update-IR. Then the instruction of WRITE_OTHER_ROUTE becomes effective and JTAG Routing Register for another JTAG port is chosen as the data register. (d) Current data in JTAG Routing Register for another JTAG port is parallel-loaded into the scanning register in Capture-DR. (e) The data to be written in JTAG Routing Register for another JTAG port is fed into the scanning register from TDI in Shift-DR. At the same time the data on the scanning register (current data of JTAG Routing Register for another JTAG port) is output from TDO. The input from TDI and the output from TDO are shifted in/out from LSB to MSB. (f) The data on the scanning register is parallel-loaded into JTAG Routing Register for another JTAG port in Update-DR. Then the JTAG route is selected in accordance with the new data. (g) When a route that is already occupied by another port is written, the data of JTAG Routing Register is set to be NC by force. Verification of the written data is recommended. Fig 7 : Timing of Write Other Route JRC 9/5/2002 (Version 1.1 ) 9
Read Other Route (a) The instruction Capture Code is captured in Capture-IR. (b) READ_OTHER_ROUTE command is loaded in an instruction scan register from TDI using Shift-IR. At the same time, Capture Code is output from TDO. The data is fed in/out (LSB first and MSB last in that order). (c) The instruction in an instruction scan register is parallel-loaded into the instruction register in Update-IR. Then the instruction of READ_OTHER_ROUTE becomes effective and JTAG Routing Register for another JTAG port is chosen as the data register. (d) Current data in JTAG Routing Register for another JTAG port is parallel-loaded into the scanning register in Capture-DR. (e) The data of the scanning register is shifted out by 3 bits from TDO in Shift-DR. At the same time, the arbitrary data can be fed to the scanning register from TDI. Fig 8 : Timing of Read Other Route JRC 9/5/2002 (Version 1.1 ) 10
2.4 Routing Arbitration The signal routes of JTAG signals (DA and DB) from Port-A and Port-B are controlled by two auxiliary control JTAG signals (CA and CB). Any of two channels does not have priority for the control. In normal operation, DA is controlled by CA and DB is by CB. The rule of "fast come, first served" is applied. When a rout e that is already assigned is requested by another port, the request is rejected and NC is selected as shown in Fig 9. CA (CB) can exceptionally control the route of DB (DA). The exceptional function is for recovery of troubles such as one of the control JTAG paths does not work. 2.5 Remarks about controlling route When both CA and CB JTAGs write the data of the same route within 4 nsec, the JRC assigns the same route to both DA and DB signals. In this case, the signals would not pass through the route properly. If one of control JTAG signals re-writes the same data, the congestion is solved and NC data is stored in the re-written register as shown in Fig 10. The simultaneous read cycles from both control ports don't make any trouble. 2.6 Initialization The JRC has the asynchronous system reset that is used at the time of POWER ON etc. When the system reset is driven to LOW (enable), the Tap state returns to Test Logic Reset, the instruction register is set to the ID_CODE, and the routing register is reset to 0 (NC). However when /TRST of CA or CB JTAG signals is driven to LOW (enable), Tap state returns to Test Logic Reset and neither the instruction register nor the routing register is reset. 2.7 Characteristics of JRC IC * The delay time from D Port-A or Port-B to an output port Q is 8.8nsec. * The power consumption of JRC IC Power Supply Power tcka tmsa tdia tckb tmsb tdib Voltage consumption 3.3V 20MHz 20MHz 20MHz 20MHz 20MHz 20MHz 12.0mW JRC 9/5/2002 (Version 1.1 ) 11
JRC 9/5/2002 (Version 1.1 ) 12
Fig 9 : Timing of Routing Arbitration JRC 9/5/2002 (Version 1.1 ) 13
Fig 10 : Timing of Violation of the rule JRC 9/5/2002 (Version 1.1 ) 14
3. The detail of the part for the radiation test 3.1 Ring Oscillator Fig 11 shows the ring oscillator to be designed. The ring is constituted from 501 NAND gates with two output loads. The ring oscillator can be enabled by ENABLE signal and monitored form MONITOR output. Fig 11 : The circuit diagram of Ring Oscillator Fig 12: The relation between power supply voltage and the period of Ring Oscillator Fig 12 shows the result of the measurements and the simulation using Verilog code. The difference between the measurement and the simulation at the supply voltage of 3.3V is approximately 25 nsec. The signal path length and their parasitic capacitance etc are not JRC 9/5/2002 (Version 1.1 ) 15
considered in the simulation. The delay per gate is 90ps in the typical power supply voltage (3.3V). 3.2 Shift Register The shift register is a master-slave type and consists of 256 flip-flops. The four shift registers are implemented and each has the same input and works at common clock. Fig 13 : The circuit diagram of Shift Register 4. Coding 4.1 Voting Logic The voting logic (Fig 14) is introduced to the instruction registers and the data registers in order to cope with the radiation immunity against SEU (Single Event Upset) which was induced by charged particle irradiation. One bit information is stored in three registers followed by the majority logic. The circuit if Fig 13 works as a 1-bit register. The possibility that more than one register of three registers flip the states is extremely low. Fig 14 : The circuit diagram of Voting Logic JRC 9/5/2002 (Version 1.1 ) 16
4.2 Layout The used soft lists * Verilog-XL * Design Analyzer * Milkyway / Apollo * DraculaDRC Layout Picture * Rohm 0.35 mm process * Core size : 4.5mm x 4.5mm JRC 9/5/2002 (Version 1.1 ) 17
Pin assignment JRC 9/5/2002 (Version 1.1 ) 18
Pin number Pin name Type Description 1 VDDO Power Supply (+3.3V) for IO buffer 2 GNDO Ground for IO buffer 3 RESERVED 4 NC No Connect 5 reset_ Asynchronous System Reset (negative logic) Instruction and Routing register is reset and Tap State returns to Test Logic Reset 6 ff_q4 Tri State Output Shift Register Output_4 (radiation test purpose) 7 ff_q3 Tri State Output Shift Register Output_3 (radiation test purpose) 8 ff_q2 T ri State Output Shift Register Output_2 (radiation test purpose) 9 ff_q1 Tri State Output Shift Register Output_1 (radiation test purpose) 10 ff_d Tri State Output Shift Register Common Input (radiation test purpose) 11 VDD Power Supply (+3.3V) 12 ff_clk Input Shift Register Common Clock (radiation test purpose) 13 GND Ground 14 ring4_en Enable Ring Oscillator_4 Enable Signal (radiation test purpose) HIGH level : Enable LOW level : Disable 15 ring4_mon Monitor Ring Oscillator_4 Monitor (radiation test purpose) Ring Oscillator_3 Enable Signal (radiation test 16 ring3_en Enable purpose) HIGH level : Enable LOW level : Disable 17 ring3_mon Monitor Ring Oscillator_3 Monitor (radiation test purpose) Ring Oscillator_2 Enable Signal (radiation test 18 ring2_en Enable purpose) HIGH level : Enable LOW level : Disable 19 ring2_mon Monitor Ring Oscillator_2 Monitor (radiation test purpose) 20 ring1_en Enable Ring Oscillator_1 Enable Signal (radiation test purpose) HIGH level : Enable LOW level : Disable 21 ring1_mon Monitor Ring Oscillator_1 Monitor (radiation test purpose) 22 NC No Connect JRC 9/5/2002 (Version 1.1 ) 19
23 GNDO Ground for IO buffer 24 NC No Connect 25 VDDO Power Supply (+3.3V) for IO buffer 26 q6_out[0] T ri State Output Q6 Signal (Q6-trst_) 27 q6_out[1] Tri State Output Q6 Signal (Q6-tck) 28 q6_out[2] Tri State Output Q6 Signal (Q6- tms) 29 q6_out[3] Tri State Output Q6 Signal (Q6-tdi) 30 q6_in Input Q6 Signal (Q6-tdo) 31 q4_out[0] Tri State Output Q4 Signal (Q4-trst_) 32 q4_out[1] Tri State Output Q4 Signal (Q4-tck) 33 q4_out[2] Tri State Output Q4 Signal (Q4-tms) 34 q4_out[3] Tri State Output Q4 Signal (Q4-tdi) 35 GND Ground 36 VDD Power Supply (3.3V) 37 VDDO Power Supply (3.3V) for IO buffer 38 GNDO Ground for IO buffer 39 q4_in Input Q4 Signal (Q4-tdo) 40 q2_out[0] Tri State Output Q2 Signal (Q2-trst_) 41 q2_out[1] Tri State Output Q2 Signal (Q 2-tck) 42 q2_out[2] Tri State Output Q2 Signal (Q2-tms) 43 q2_out[3] Tri State Output Q2 Signal (Q 2-tdi) 44 q2_in Input Q2 Signal (Q2-tdo) 45 q1_out[0] Tri State Output Q1 Signal (Q1-trst_) 46 q1_out[1] Tri State Output Q1 Signal (Q1-tck) 47 VDD Power Supply (+3.3V) 48 q1_out[2] Tri State Output Q1 Signal (Q1-tms) 49 GND Ground 50 q1_out[3] Tri State Output Q1 Signal (Q1-tdi) 51 q1_in Input Q1 Signal (Q1-tdo) 52 q3_out[0] Tri State Output Q3 Signal (Q3-trst_) 53 q3_out[1] Tri State Output Q3 Signal (Q3-tck) 54 q3_out[2] Tri State Output Q3 Signal (Q3-tms) 55 q3_out[3] Tri State Output Q3 Signal (Q3-tdi) 56 q3_in Input Q3 Signal (Q3-tdo) 57 q5_out[0] Tri State Output Q5 Signal (Q5-trst_) JRC 9/5/2002 (Version 1.1 ) 20
58 q5_out[1] Tri State Output Q5 Signal (Q5-tck) 59 VDDO Power Supply (+3.3V) for IO buffer 60 NC No Connect 61 GNDO Ground for IO buffer 62 NC No Connect 63 q5_out[2] Tri State Output Q5 Signal (Q5-tms) 64 q5_out[3] Tri State Output Q5 Signal (Q5-tdi)) 65 q5_in Input Q5 Signal (Q5-tdo) 66 q7_out[0] Tri State Output Q7 Signal (Q7-trst_) 67 q7_out[1] Tri State Output Q7 Signal (Q7-tck) 68 q7_out[2] Tri State Output Q7 Signal (Q7-tms) 69 q7_out[3] Tri State Output Q7 Signal (Q7-tdi) 70 q7_in Input Q7 Signal (Q7-tdo) 71 GND Ground 72 VDD Power Supply (+3.3V) 73 VDDO Power Supply (+3.3V) for IO buffer 74 GNDO Ground for IO buffer 75 routea[0] Monitor 78 routea[1] Monitor Route Monitor of Port-A 77 routea[2] Monitor 78 routeb[0] Monitor 79 routeb[1] Monitor Route Monitor of Port-B 80 routeb[2] Monitor 81 NC No Connect 82 NC No Connect 83 GND Ground 84 NC No Connect 85 VDD Power Supply (+3.3V) 86 tapa[0] Monitor 87 tapa[1] Monitor Tap State Monitor of Port-A 88 tapa[2] Monitor Refer to Fig 4 about the corresponding bits 89 tapa[3] Monitor 90 tapb[0] Monitor 91 tapb[1] Monitor Tap State Monitor of Port-B 92 tapb[2] Monitor Refer to Fig 4 about the corresponding bits JRC 9/5/2002 (Version 1.1 ) 21
93 tapb[3] Monitor 94 NC No Connect 95 VDDO Power Supply (+3.3V) for IO buffer 96 NC No Connect 97 GNDO Ground for IO buffer 98 NC No Connect 99 NC No Connect 100 NC No Connect 101 NC No Connect 102 NC No Connect 103 NC No Connect 104 NC No Connect 105 NC No Connect 106 NC No Connect 107 GND Ground 108 VDD Power Supply (+3.3V) 109 VDDO Power Supply (+3.3V) for IO buffer 110 GNDO Ground for IO buffer 111 NC No Connect 112 db_in[0] Input DB Signal (DB-trst_) 113 db_in[1] Input DB Signal (DB-tck) 114 db_in[2] Input DB Signal (DB-tms) 115 db_in[3] Input DB Signal (DB-tdi) 116 db_out Tri State Output DB Signal (DB-tdo) 117 NC No Connect 118 NC No Connect 119 VDD Power Supply (+3.3V) 120 NC No Connect 121 GND Ground 122 da_in[0] Input DA Signal (DA-trst_) 123 da_in[1] Input DA Signal (DA-tck) 124 da_in[2] Input DA Signal (DA-tms) 125 da_in[3] Input DA Signal (DA-tdi) 126 da_out Tri State Output DA Signal (DA-tdo) 127 NC No Connect JRC 9/5/2002 (Version 1.1 ) 22
128 NC No Connect 129 NC No Connect 130 trstb_ Input Control JTAG Signal of Port-B (CB) Tap State returns to Test Logic Reset Instruction and Routing register is not reset 131 GNDO Ground for IO buffer 132 NC No Connect 133 VDDO Power Supply (+3.3V) for IO buffer 134 tckb Input Control JTAG Signal of Port-B (CB) 135 tmsb Input Control JTAG Signal of Port-B (CB) 136 tdib Input Control JTAG Signal of Port-B (CB) 137 tdob Tri State Output Control JTAG Signal of Port-B (CB) 138 trsta_ Input Control JTAG Signal of Port-A (CA) Tap State of Port-A returns to Test Logic Reset Instruction and Routing register is not reset 139 tcka Input Control JTAG Signal of Port- A (CA) 140 tmsa Input Control JTAG Signal of Port- A (CA) 141 tdia Input Control JTAG Signal of Port- A (CA) 142 tdoa Tri State Output Control JTAG Signal of Port- A (CA) 143 GND Ground 144 VDD Power Supply (+3.3V) JRC 9/5/2002 (Version 1.1 ) 23
ATLAS TGC Electronics Group JRC ( JTAG Routing Controller ) Version 1.1 August 29, 2002 JRC 9/5/2002 (Version 1.1 ) 24