EE5780 Advanced VLSI CAD Lecture 11 SRAM and Yield Analysis Zhuo Feng 11.1
Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports Outline Serial Access Memories 11.2
Memory Arrays Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Read/Write Memory (RAM) (Volatile) Read Only Memory (ROM) (Nonvolatile) Shift Registers Queues Static RAM (SRAM) Dynamic RAM (DRAM) Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) First In First Out (FIFO) Last In First Out (LIFO) Mask ROM Programmable ROM (PROM) Erasable Programmable ROM (EPROM) Electrically Erasable Programmable ROM (EEPROM) Flash ROM 11.3
2 n words of 2 m bits each Array Architecture If n >> m, fold by 2 k into fewer rows of more columns wordlines bitline conditioning bitlines row decoder memory cells: 2 n-k rows x 2 m+k columns Good regularity easy to design Very high density if good cells are used 11.4 n-k n k column decoder 2 m bits column circuitry
12T SRAM Cell Basic building block: SRAM Cell Holds one bit of information, like a latch Must be read and written 12-transistor (12T) SRAM cell Use a simple latch connected to bitline 46 x 75 unit cell write bit write_b read read_b 11.5
6T SRAM Cell Cell size accounts for most of array size Reduce cell size at expense of complexity 6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters Read: bit Precharge bit, bit_b Raise wordline word Write: Drive data onto bit, bit_b Raise wordline bit_b 11.6
SRAM Read Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability A must not flip bit bit_b word 1.5 A_b bit_b N2 P1 P2 N4 1.0 word bit A N1 N3 A_b 0.5 0.0 A 0 100 200 300 400 500 600 time (ps) 11.7
word Precharge both bitlines high Then turn on wordline SRAM Read One of the two bitlines will be pulled down by the cell Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability A must not flip bit bit_b 1.5 N1 >> N2 N3 >> N4 A_b bit_b N2 P1 P2 N4 1.0 word bit A N1 N3 A_b 0.5 0.0 A 0 100 200 300 400 500 600 time (ps) 11.8
SRAM Write Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high Writability Must overpower feedback inverter A_b word bit N2 P1 P2 bit_b N4 1.5 1.0 bit_b A A N1 N3 A_b 0.5 word 0.0 0 100 200 300 400 500 600 700 time (ps) 11.9
SRAM Write Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high Writability Must overpower feedback inverter A_b N2 >> P1 N4 >> P2 word bit N2 P1 P2 bit_b N4 1.5 1.0 bit_b A A N1 N3 A_b 0.5 word 0.0 0 100 200 300 400 500 600 700 time (ps) 11.10
SRAM Sizing High bitlines must not overpower inverters during reads But low bitlines must write new value into cell bit bit_b word med weak med A A_b strong 11.11
SRAM Column Example Bitline Conditioning 2 More Cells Read bit_v1f bit_b_v1f Write word_q1 bit_v1f SRAM Cell bit_b_v1f write_q1 data_s1 11.12
SRAM Layout Cell size is critical: 26 x 45 (even smaller in industry) Tile cells sharing V DD, GND, bitline contacts GND BIT BIT_B GND VDD WORD Cell boundary 11.13
In nanometer CMOS Thin Cell Avoid bends in polysilicon and diffusion Orient all transistors in one direction Lithographically friendly or thin cel layout fixes this Also reduces length and capacitance of bitlines 11.14
Commercial SRAMs Five generations of Intel SRAM cell micrographs Transition to thin cell at 65 nm Steady scaling of cell area 11.15
Decoders n:2 n decoder consists of 2 n n-input AND gates One needed for each row of memory Build AND from NAND or NOR gates Static CMOS Pseudo-nMOS A1 A0 A1 1 1 1 8 4 word A1 A0 1/2 A0 A1 1 1 4 2 16 8 word A0 1 word0 word1 word2 word3 word0 word1 word2 word3 11.16
Decoder Layout Decoders must be pitch-matched to SRAM cell Requires very skinny gates A3 A3 A2 A2 A1 A1 A0 A0 VDD word GND NAND gate buffer inverter 11.17
Large Decoders For n > 4, NAND gates become slow Break large gates into multiple smaller gates A3 A2 A1 A0 word0 word1 word2 word3 word15 11.18
Column Circuitry Some circuitry is required for each column Bitline conditioning Sense amplifiers Column multiplexing 11.19
Bitline Conditioning Precharge bitlines high before reads bit bit_b Equalize bitlines to minimize voltage difference when using sense amplifiers bit bit_b 11.20
Sense Amplifiers Bitlines have many cells attached Ex: 32-kbit SRAM has 256 rows x 128 cols 128 cells on each bitline t pd (C/I) V Even with shared diffusion contacts, 64C of diffusion capacitance (big C) Discharged slowly through small transistors (small I) Sense amplifiers are triggered on small voltage swing (reduce V) 11.21
Differential Pair Amp Differential pair requires no clock But always dissipates static power sense_b bit P1 N1 N2 P2 sense bit_b N3 11.22
Clocked Sense Amp Clocked sense amp saves power Requires sense_clk after enough bitline swing Isolation transistors cut off large bitline capacitance bit bit_b sense_clk isolation transistors regenerative feedback sense sense_b 11.23
Twisted Bitlines Sense amplifiers also amplify noise Coupling noise is severe in modern processes Try to couple equally onto bit and bit_b Done by twisting bitlines b0 b0_b b1 b1_b b2 b2_b b3 b3_b 11.24
Column Multiplexing Recall that array may be folded for good aspect ratio Ex: 2k word x 16 folded into 256 rows x 128 columns Must select 16 output bits from the 128 columns Requires 16 8:1 column multiplexers 11.25
Tree Decoder Mux Column mux can use pass transistors Use nmos only, precharge outputs One design is to use k series transistors for 2 k :1 mux No external decoder logic needed A0 B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7 A0 A1 A1 A2 A2 Y to sense amps and write circuits Y 11.26
Single Pass-Gate Mux Or eliminate series transistors with separate decoder A1 A0 B0 B1 B2 B3 Y 11.27
Dual-Ported SRAM Simple dual-ported SRAM Two independent single-ended reads Or one differential write bit bit_b worda wordb Do two reads and one write by time multiplexing Read during ph1, write during ph2 11.28
Large SRAMs Large SRAMs are split into subarrays for speed Ex: UltraSparc 512KB cache 4 128 KB subarrays Each have 16 8KB banks 256 rows x 256 cols / bank 60% subarray area efficiency Also space for tags & control [Shin05] 11.29
Yield analysis of embedded memory modules Play a critical role in nanoscale and emerging nonvolatile memory designs for future microprocessor, 3D-IC, and mixed-signal system designs Challenged by a huge number (many millions) of Monte Carlo ICE simulations for relatively small circuit blocks considering parametric (process, voltage, and temperature) variations 3 rd Generation Intel Core Processor: 22nm Process Source: http://www.futurelooks.com/intel-core-i7-3770k-ivy-bridge-lga1155-processor-review/ 11.30
l1 TinyICE Simulator TinyICE: ICE-accurate, fast, massively parallel small nonlinear circuits simulator Accelerates entire ICE simulator on GPU Run independent ICE simulations concurrently Designs GPU-friendly data structures Develops efficient algorithm flow Optimizes GPU memory accesses Newton Raphson Iterations Shared Memory Shared Memory Shared Memory Shared Memory Shared Memory Shared Memory Shared Memory Shared Memory bit bit_b word bit bit_b word bit P1 P2 bit_b N2 N4 word bit P1 P2 bit_b N2 A A_b N4 word P1 P2 N1 N2 A N3 A_b N4 P1 P2 N1 N2 A N3 A_b N4 N1 A N3 A_b N1 N3 1v 1i i 2 i 3 v 2 k i ds gm v gs k k ids Gds v ds k a a a a a a a 1,1 1,4 1,5 a2,2 a2,3 a2,6 a3,2 a3,3 a3,8 4,1 a4,4 5,1 5,5 5,7 a6,2 a6,6 a6,8 a7,5 a7,7 a8,3 a8,6 a8,8 CKT Schematic Model Evaluation Matrix Stamping/Solve Converged? Return GPU Streaming Multiprocessors Massively Parallel ICE Simulations in GPU Shared Memory 11.31
Slide 31 l1 lengfei, 5/13/2013
TinyICE Flow Chart TinyICE algorithm flow have three key steps CPU-setup phase, GPU-setup phase and GPU-analysis phase CPU Setup TinyICE GPU Analysis Reset G Matrix & Update RHS Setup 3D LUTs Nonlinear Device Parse Netlist Excitation & MOS Terminal Map Index Setup Matrix for Linear Circuit Get Latest Solution Transistor Evaluation Nonlinear Stamp GPU Setup GPU LUT @Texture Mem. Map Index @Texture Mem. Map Index @Shared Mem. G Matrix & RHS @Texture Mem. G Matrix & RHS @Shared Mem. LU Solve Conv. Chec k Return 11.32
MNA Matrix Construction Linear element evaluation on CPU due to Corresponding entries are constant value throughout whole ICE simulation Nonlinear element evaluation on GPU due to Need to be re-evaluated in every NR step Nonlinear element evaluation by parametric 3D look-up tables (LUTs) BSIM4 too complicated for GPU Simplify control flow Can capture impact of process variations by introduce parametric LUTs 11.33
Parametric 3D LUTs 2 nd order Parametric 3D LUTs evaluation function LUT base LUT LUTV th and LUT Leff LUT LUT VthLeff and Vth LUT L 2 eff 2 LUT V base LUT th Vth 2 L LUT V eff V th 2 th LUT V th LUT VthLeff Leff LUT 2 L eff L 2 eff L : Base LUT based on transistor nominal parameters : First order coefficient LUT for transistor threshold voltage and effective channel length : Second order coefficient LUT for transistor threshold voltage and effective channel length : coefficient LUT derived from the partial derivatives of Vth and Leff eff V th : Variation of transistor threshold voltage L eff 11.34 : Variation of transistor effective channel length More input parameters and more accurate requirement More costly higher order LUTs
LUTs Trilinear Interpolation(1 st Order Demonstration) Parametric 3D LUTs extraction High resolution means high memory and runtime cost One time cost, multiple usage 0.6% of whole simulation time Trilinear interpolation p 0 Base LUT p x, y, z c c c c c c c c 000 100 010 001 101 011 110 111 (1 x)(1 y)(1 z) x(1 y)(1 z) (1 x) y(1 z) (1 x)(1 y) z x(1 y) z (1 x) yz xy(1 z) x y z LUT LUT P 0 p 1 Threshold Voltage LUT base LUT P V 1 th V th V th P L 2 eff p 2 Effective Channel Length LUT LUT L eff L eff 11.35
GPU Friendly Data Structure Design System Matrix Adopt dense structure due to Complicated memory access required by sparse matrix Affordable memory consumption (limited problem size) Store in GPU register due to Frequent read/write memory access Parametric 3D LUTs Store in texture memory due to Read only memory access Gmat Gmat vth Gmat Leff MOSFET 1 n MOSFET 1 n MOSFET 1 n 3D LUTs Texture Memory 11.36
GPU Friendly Data Structure Design (cont.) Index-mapping vectors & voltage sources vector Record stamping locations of nonlinear device and sources Record voltage sources value in all time points Store in Share memory due to All threads share this information Data size is affordable Idx Type d g s b Mos_map MOSFET 1 MOSFET n Pseudo PWL Node a Node b VS_map Node P Shared Memory Voltage Source 1 Voltage Source n V_t1 V_t2... V_tn VS_step Voltage Source 1 Voltage Source n 11.37
GPU Friendly Data Structure Design (cont.) Solution vector Record solution of each time point Need send back to CPU Store in Global memory due to Low access frequency Satisfy coalesced memory accesses X[0] X1.0 X2.0 Xn.0 X1.n X2.n Xn.n T1 T2 Tn X[n] Solution Global Memory 11.38
Newton-Raphson Algorithm on GPU Check convergence after several NR iterations Reduces the GPU thread divergence Leads some overhead Reset G Matrix & Update RHS Reset G Matrix & Update RHS Transistor Evaluation Transistor Evaluation Get Latest Solution Nonlinear Stamp Get Latest Solution Nonlinear Stamp LU Solve LU Solve Time to Check 11.39 Conv. Check Return Conv. Check Return
Linux computing system: C++ & CUDA CPU: Core 2 Quad 2.66GHz + 6GB DRAM GPU: GPU: NVIDIA GTX 480 + 1.5G Device memory Tested cases Experimental Setups Circuit NL_Num Node_Num Vs_Num Unk_Num 6T-SRAM 6 8 5 12 D-Latch 8 9 5 13 D-Flip-Flop 16 12 5 16 Invertor- 32 20 3 22 Chain 4:1 Mux 24 27 9 35 NL_Num : Number of nonlinear devices Node_Num : Number of nodes in the circuit Vs_Num : Number of independent voltage sources Unk_Num : number of unknowns of the nonlinear system 11.40
Run 1,536,000 simulations with different excitation and circuit design parameters Speedup LUTs GPU vs. LUTs CPU is up to 138X Speedup LUTs GPU vs. BSIM4 CPU is up to 264X 264 X 138 X DC Simulation Result 211 X 92X 189 X 92X 104 X 45 X 47 X 22 X Runtime (log) 11.41
Transient Simulation Result Speedup LUTs GPU vs. LUTs CPU is up to 57X Speedup LUTs GPU vs. BSIM4 CPU is up to 222X Runtime (log) 187 X 46X 222 X 57X 202X 53X 160 X 96 X 54 X 12 X 11.42
Memory Consumption vs. Speedup Runtime efficiency decrease with the increase of circuit size Memory usage increase dramatically due to dense MNA structure 11.43