ASSET InterTech, Inc. Validation: A Case Study Michael R. Johnson Sr. Applications Engineer ASSET InterTech, Inc. Agilent Boundary Scan User Group Meeting December 15, 2008
About The Presenter Michael R. Johnson presently serves as a Sr. Applications Engineer with ASSET InterTech and also Manager of ASSET InterTech s Training Department. As Manager, Michael is responsible for coordination of ASSET s Boundary Scan training activities within the United States. Michael has an extensive 10 year background as a hardware design engineer with Nortel Networks and Alcatel USA. While at Alcatel USA, Michael s emphasis was high-speed PCB design and layout for digital cross connect and fiber optic systems. Michael earned a Bachelors of Science Degree in Electrical Engineering from Southern University and A&M College located in Baton Rouge, Louisiana. ASSET InterTech, Inc. 2201 N. Central Expy. Ste. #105 Richardson, TX. 75080 (972) 664-3103 mjohnson@asset-intertech.com www.asset-intertech.com 2
Overview ASSET InterTech Who We Are & What We Do What Is IEEE 1149.1 (aka JTAG or Boundary Scan )? What Is A File? Validation Service Overview Industry Validation Process ASSET InterTech Validation Service Case Studies Summary 3
ASSET Who We Are & What We Do We provide open tools for embedded instrumentation for design validation, test, and debug Boundary Scan (ScanWorks ) #1 Globally JTAG Emulation (MicroMaster ) High-Speed I/O Validation (Intel IBIST) IJTAG (Core Silicon Instrumentation) Historical roots from Texas Instruments (TI) Technology leadership in Standards Committees IEEE 1149.1, 1149.6, 1532, JEDEC/STAPL, SVF, SJTAG, PICMG, P1149.7 (MIPI), P1687, inemi 4
What Is IEEE 1149.1 (aka JTAG or Boundary Scan)? A Silicon Embedded Access And Control Mechanism TDI TCK Input Scan Cell: Sensor (RX) Output Scan Cell: Driver (TX) TMS TDO 5
What Is A File? File entity ASSET Is generic (PHYSICAL_PIN_MAP : string := DW ); port ( Inx :linkage bit_vector (1 to 8); GPIO1, GPIO2 :inout bit; ); use STD_1149.1_2001.all; attribute COMPONENT_CONFORMANCE of ASSET : entity is STD_11491_1_2001. ; attribute PIN_MAP of ASSET : entity is PHYSICAL_PIN_MAP; Constant DW : PIN_MAP_STRING := INx:(3,4,5,6,7,8,9,10), & GPIO1:14, GPIO2:15 ; attribute TAP_SCAN_IN of TDI : signal is true; attribute TAP_SCAN_MODE of TMS : signal is true; Boundary Scan Description Language Describes only 100% IEEE 1149.1 compliant devices Describes device variables (register size, mandatory public, private, and custom instructions, number and type of Boundary Scan cells used, device port names, device package type) Subset of VHDL Adopted as part of the IEEE 1149.1 Standard in 1994 6
Industry JTAG Design/ Validation Process Electronic Design Automation Tools Pre-Tapeout Post-Tapeout Creation Simulation Testbench JTAG Insertion File PCF ATE Confidence that JTAG 1149.1 has been properly implemented Hand Created Syntax Check Pattern Generation ASSET / Agilent 7
Pre-Tapeout: JTAG Insertion Electronic Design Automation Tools JTAG Insertion File Challenges Many semiconductor companies don t use automation Hand-generation of files is difficult and error-prone Generated files *generally* need tweaking Automation tools may not be DFT-aware (e.g. ground bounce) Hand Created http://www.asset-intertech.com/pdfs/guidelines_for_device.pdf 8
Pre-Tapeout: JTAG Simulation File Simulation Testbench Pros and Cons Some test is better than no test at all! Verifies that the device works in simulation Does not verify that the silicon will work or that the matches the silicon Tools that insert the JTAG logic may be the same as those that generate the testbench (the fox in the henhouse ) 9
Pre-Tapeout: Validation File PCF Syntax Check Pattern Generation Simulation Testbench ASSET / Agilent Pros and Cons ASSET / Agilent service provides free, web-based syntax/semantic checking and pattern generation Supports1149.6 syntax and semantics checking Many semiconductor companies do not use third-party vectors in simulation 10
Post-Tapeout: ATE File PCF ATE Pros and Cons ATE provides post-tapeout validation Test time is expensive on ATE ATE environment is focused on validating devices rather than s Syntax Check Pattern Generation ASSET / Agilent 11
ASSET InterTech Validation Service Electronic Design Automation Tools Pre-Tapeout Post-Tapeout ScanWorks Design Logic JTAG Insertion Creation File ASSET Validation Test Fixture PCF Simulation Testbench Confirmation that JTAG 1149.1 has been properly implemented Hand Created Syntax Check Pattern Generation ASSET / Agilent 12
Post-Tapeout: ASSET InterTech Validation Service File This has been validated for syntax and semantics compliance to IEEE 1149.1. It also passed all hardware validation test using the ASSET InterTech validation process. Michael Johnson ASSET InterTech, Inc. Ph: 972-664-3103 ASSET Validation Process Most rigorous way of testing Used by many large semiconductor suppliers (e.g. Xilinx press release http://www.assetintertech.com/news_article.html?newsid=80) Device ID and Bypass DR Scan, IR Capture, BYPASS, IDCODE, BSR Length, USERCODE and TRST (If Applicable), and Interconnect (EXTEST) Test fixture supports 1149.1 and 1149.6 Captures and exposes design flaws: - Pin-To-Cell mapping errors - Compliance enables - Silicon implementation issues 13
Case Study One: ASSET InterTech Validation Service File X Observations / Device Failures: Control Cell safe value / Output Cell disable value mis-match Unable to place device into Boundary Scan operation mode Device appears non responsive when placed into EXTEST Bi-Directional Cells behaving as Input Cells 14
Case Study One: ASSET InterTech Validation Service BEFORE Validation Solution: Change Control Cells and/or disable values of Output Cells in the Boundary Scan Register so they agree AFTER 15
Case Study One: ASSET InterTech Validation Service ADDITION BEFORE Validation Solution: Add attribute COMPLIANCE_ENABLE to Properly arrange cell numbers in the Boundary Scan Register from TDO to TDI AFTER 16
Case Study One: ASSET InterTech Validation Service BEFORE Validation Solution: Change pins with declared OUTPUT3 and CONTROL functions to INTERNAL (required changes to Port section & Boundary Scan Register) AFTER Validation result: Device was re-fabricated to correct JTAG silicon implementation 17
Case Study Two: ASSET InterTech Validation Service File X Observations / Device Failures: Unable to place device in Boundary Scan operation mode Device appears non-responsive when placed into EXTEST Non-functional differential pins 18
Case Study Two: ASSET InterTech Validation Service Validation Solution: ADDITION Add attribute COMPLIANCE_ENABLE to and attribute DESIGN_WARNING informing users of voltage timing sequence and clock input for JTAG/functional device operation ADDITION 19
Case Study Two: ASSET InterTech Validation Service BEFORE Validation Solution: Properly arrange cell numbers in the Boundary Scan Register from TDO to TDI AFTER 20
Case Study Two: ASSET InterTech Validation Service Port Section Pin Map Section Validation Solution: Add missing differential Port names to Port section, assign Port names to pins in Pin_Mapping Section, add attribute Port_Grouping to designate differential groups ADDITION Validation result: Corrections to the were required to match JTAG silicon implementation 21
Case Study Three: ASSET InterTech Validation Service File X Observations / Device Failures: Device appears responsive when placed into EXTEST but expected vector values were inverted 22
Case Study Three: ASSET InterTech Validation Service BEFORE Validation Solution: Outputs of device are Open Drain Circuits. Change function OUTPUT2 Cells to Self Controlled Cells to further validate inverted Output Cells and also test the Input Cells for expected functionality AFTER 23
Case Study Three: ASSET InterTech Validation Service BEFORE BEFORE AFTER Validation Solution: Function OUTPUT 2 Cells were changed to function INTERNAL due to inverted outputs. Input Cells functioned as expected. No EXTEST coverage on ALERT, OVERT, OVERC, FAULT1, FAULT2, and RESET signals AFTER Validation result: Device was re-fabricated to correct JTAG Silicon Implementation 24
Summary More companies are realizing the importance of a compliant JTAG design within their silicon There are numerous solutions available for JTAG design and silicon verification and validation Encourage your device suppliers to provide you with VALIDATED 1149.1 compliant silicon At ASSET InterTech: We drive embedded instrumentation solutions for design validation, test and debug 25
Summary Questions? 26
One more shot! Take the Poll at the right hand side of the screen and be entered to win a lucky draw for a $25 Amazon.com giftcard to be awarded during this meeting. 27
Answer What Boundary Scan Products does Agilent sell? ANSWER: All listed! In-circuit BSCAN included in the base software Interconnect BSCAN -1149.1 optional software 1149.6 - optional software 28
Thank you! We hope this was time well spent today. Please do take the time to fill out the survey that pops up when the interface closes. Join us in January for our next online i3070 Webex Tutorial: www.agilent.com/find/i3070events Join the ICT test forum discussion today: www.agilent.com/find/ictforum 29