FINAL COM L: H-7//5/2 IND: H-/5/2 PALCE26V2 Family 28-Pin EE CMOS Versatile PAL Device DISTINCTIVE CHACTERISTICS 28-pin versatile PAL programmable logic device architecture Electrically erasable CMOS technology provides half power (only 5 ma) at high speed (7.5 ns propagation delay) 4 dedicated inputs and 2 input/output macrocells for architectural flexibility Macrocells can be registered or combinatorial, and active high or active low Varied product term distribution allows up to 6 product terms per output Two clock inputs for independent functions Global asynchronous reset and synchronous preset for initialization Register preload for testability and built-in register reset on power-up Space-efficient 28-pin SKINNYDIP and PLCC packages Center VCC and GND pins to improve signal characteristics Extensive third-party software and programmer support through FusionPLD partners GENERAL DESCRIPTION The PALCE26V2 is a 28-pin version of the popular PAL22V architecture. Built with low-power, highspeed, electrically-erasable CMOS technology, the PALCE26V2 offers many unique advantages. Device logic is automatically configured according to the user s design specification. Design is simplified by design software, allowing automatic creation of a programming file based on Boolean or state equations. The software can also be used to verify the design and can provide test vectors for the programmed device. The PALCE26V2 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The functions are programmed into the device through electrically-erasable floating-gate cells in the AND logic array and the macrocells. In the unprogrammed state, all AND product terms float HIGH. If both true and complement of any input are connected, the term will be permanently LOW. The product terms are connected to the fixed OR array with a varied distribution from 8 to 6 across the outputs (see Block Diagram). The OR sum of the products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial, active high or active low, with registered possible. The flip-flop can be clocked by one of two clock inputs. The output configuration is determined by four bits controlling three multiplexers in each macrocell. AMD s FusionPLD program allows PALCE26V2 designs to be implemented using a wide variety of popular industry-standard design tools. By working closely with the FusionPLD partners, AMD certifies that the tools provide accurate, quality support. By ensuring that third-party tools are available, costs are lowered because a designer does not have to buy a complete set of new tools for each device. The FusionPLD program also greatly reduces design time since a designer can use a tool that is already installed and familiar. Please refer to the PLD Software Reference Guide for certified development systems and the Programmer Reference Guide for approved programmers. 2-36 Publication# 672 Rev. E Amendment / Issue Date: February 996
BLOCK DIAGRAM CLK/I I 2 2 SYNC. PRESET PROGRAMMABLE AND RAY (52x5) ASYNC. RESET 8 8 2 4 6 6 4 2 8 8 2 3 4 5 6 7 8 9 672E- CONNECTION DIAGRAMS Top View DIP PLCC CLK/I I 2 28 27 I3 CLK 2 /I3 I2 I CLK/I I3 I2 3 26 CLK2/I3 4 25 9 4 3 2 28 27 26 I4 5 24 8 I 4 5 25 9 I5 VCC I6 I7 I8 I9 I I 6 7 8 9 2 3 23 22 2 2 9 8 7 6 7 6 GND 5 4 3 2 I 5 V CC I 6 I 7 I 8 I 9 6 7 8 9 2 3 4 5 6 7 24 23 22 2 2 9 8 8 7 6 GND 5 4 I2 4 5 I I I2 2 3 Note: Pin is marked for orientation. 672E-2 672E-3 PIN DESCRIPTION CLK = Clock GND = Ground I = Input = Input/Output VCC = Supply Voltage PALCE26V2 Family 2 37
ORDERING INFORMATION Commercial and Industrial Products AMD commercial and industrial programmable logic products are available with several ordering options. The order number (Valid Combination) is formed by a combination of: PAL CE 26 V 2 H -7 P C /4 FAMILY TYPE PAL = Programmable Array Logic TECHNOLOGY CE = CMOS Electrically Erasable NUMBER OF RAY INPUTS OUTPUT TYPE V = Versatile NUMBER OF OUTPUTS POWER H= Half Power (5 ma ICC) OPTIONAL PROCESSING Blank = Standard Processing PROGRAMMING DESIGNATOR /4 = First Revision (May require programmer update) OPERATING CONDITIONS C = Commercial ( C to +75 C) I = Industrial ( 4 C to +85 C) PACKAGE TYPE P = 28-Pin 3 mil Plastic SKINNYDIP (PD328) J = 28-Pin Plastic Leaded Chip Carrier (PL 28) SPEED -7 = 7.5 ns tpd - = ns tpd -5 = 5 ns tpd -2 = 2 ns tpd Valid Combinations PALCE26V2H-7 JC PALCE26V2H- PALCE26V2H-5 PC, JC, PI, JI PALCE26V2H-2 /4 Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. 2 38 PALCE26V2H-7//5/2 (Com l), H-/5/2 (Ind)
FUNCTIONAL DESCRIPTION The PALCE26V2 has fourteen dedicated input lines, two of which can be used as clock inputs. Unused inputs should be tied directly to ground or VCC. Buffers for device inputs and feedbacks have both true and complementary outputs to provide user-selectable signal polarity. The inputs drive a programmable AND logic array, which feeds a fixed OR logic array. The OR gates feed the twelve macrocells (see Figure ). The macrocell allows one of eight potential output configurations; registered or combinatorial, active high or active low, with register or pin feedback (see Figure 2). In addition, registered configurations can be clocked by either of the two clock inputs. The configuration choice is made according to the user s design specification and corresponding programming of the configuration bits S S3 (see Table ). Multiplexer controls initially float to VCC () through a programmable cell, selecting the path through the multiplexer. Programming the cell connects the control line to GND (), selecting the path. Table. Macrocell Configuration Table S3 S S Output Configuration Registered Output and Feedback, Active Low Registered Output and Feedback, Active High Combinatorial, Active Low Combinatorial, Active High Registered, Active Low Registered, Active High Combinatorial Output, Registered Feedback, Active Low Combinatorial Output, Registered Feedback, Active High = Unprogrammed EE bit = Programmed EE bit OE P Pn n = 8,8,,2,4,6 CLK SP CLK 2 D Q S 2 Q SP S 3 * * When S 3 = (unprogrammed) the feedback is selected by S. When S 3 = (programmed), the feedback is the opposite of that selected by S. 672E-4 Figure. PALCE26V2 Macrocell Registered or Combinatorial Each macrocell of the PALCE26V2 includes a D-type flip-flop for data storage and synchronization. The flip-flop is loaded on the LOW-to-HIGH edge of the selected clock input. Any macrocell can be configured as combinatorial by selecting a multiplexer path that bypasses the flip-flop. Bypass is controlled by bit S. Programmable Clock The clock input for any flip-flop can be selected to be from either pin or pin 4. A 2: multiplexer controlled by bit determines the clock input. Programmable Feedback A 2: multiplexer allows the user to determine whether the macrocell feedback comes from the flip-flop or from the pin, independent of whether the output is registered or combinatorial. Thus, registered outputs may have internal register feedback for higher speed (fmax internal), or feedback for use of the pin as a direct input (fmax external). Combinatorial outputs may have feedback, either for use of the signal in other equations or for use as another direct input, or register feedback. S S Clock Input CLK/I CLK2/I3 PALCE26V2 Family 2 39
The feedback multiplexer is controlled by the same bit (S) that controls whether the output is registered or combinatorial, as on the 22V, with an additional control bit (S3) that allows the alternative feedback path to be selected. When S3 =, S selects register feedback for registered outputs (S = ) and feedback for combinatorial outputs (S = ). When S3 =, the opposite is selected: feedback for registered outputs and register feedback for combinatorial outputs. Programmable Enable and Each macrocell has a three-state output buffer controlled by an individual product term. Enable and disable can be a function of any combination of device inputs or feedback. The macrocell provides a bidirectional pin if feedback is selected, and may be configured as a dedicated input if the buffer is always disabled. This is accomplished by connecting all inputs to the enable term, forcing the AND of the complemented inputs to be always LOW. To permanently enable the outputs, all inputs are left disconnected from the term (the unprogrammed state). Programmable Output Polarity The polarity of each macrocell output can be active high or active low, either to match output signal needs or to reduce product terms. Programmable polarity allows Boolean expressions to be written in their most compact form (true or inverted), and the output can still be of the desired polarity. It can also save DeMorganizing efforts. Selection is controlled by programmable bit S in the output macrocell, and affects both registered and combinatorial outputs. Selection is automatic, based on the design specification and pin definitions. If the pin definition and output equation have the same polarity, the output is programmed to be active high. Preset/Reset For initialization, the PALCE26V2 has additional Preset and Reset product terms. These terms are connected to all registered outputs. When the Synchronous Preset (SP) product term is asserted high, the output registers will be loaded with a HIGH or the next LOW-to-HIGH clock transition. When the Asynchronous Reset () product term is asserted high, the output registers will be immediately loaded with a LOW independent of the clock. Note that preset and reset control the flip-flop, not the output pin. The output level is determined by the output polarity selected. Power-Up Reset All flip-flops power up to a logic LOW for predictable system initialization. Outputs of the PALCE26V2 will be HIGH or LOW depending on whether the output is active low or active high, respectively. The VCC rise must be monotonic, and the reset delay time is ns maximum. Register Preload The register on the PALCE26V2 can be preloaded from the output pins to facilitate functional testing of complex state machine designs. This feature allows direct loading of arbitrary states, thereby making it unnecessary to cycle through long test vector sequences to reach a desired state. In addition, transitions from illegal states can be verified by loading illegal states and observing proper recovery. Security Bit After programming and verification, a PALCE26V2 design can be secured by programming the security bit. Once programmed, this bit defeats readback of the internal programmed pattern by a device programmer, securing proprietary designs from competitors. Programming the security bit disables preload, and the array will read as if every bit is disconnected. The security bit can only be erased in conjunction with erasure of the entire pattern. Programming and Erasing The PALCE26V2 can be programmed on standard logic programmers. It also may be erased to reset a previously configured device back to its virgin state. Erasure is automatically performed by the programming hardware. No special erase operation is required. Quality and Testability The PALCE26V2 offers a very high level of built-in quality. The erasability of the device provides a means of verifying performance of all AC and DC parameters. In addition, this verifies complete programmability and functionality of the device to provide the highest programming yields and post-programming functional yields in the industry. Technology The high-speed PALCE26V2 is fabricated with AMD s advanced electrically erasable (EE) CMOS process. The array connections are formed with proven EE cells. Inputs and outputs are designed to be compatible with TTL devices. This technology provides strong input clamp diodes, output slew-rate control, and a grounded substrate for clean switching. 2 3 PALCE26V2 Family
D Q D Q CLK SP Q CLK SP Q Registered Active-Low Output, Register Feedback Registered Active-High Output, Register Feedback D Q D Q CLK SP Q CLK SP Q Registered Active-Low Registered Active-High Registered Outputs Combinatorial Active-Low Combinatorial Active-High D Q D Q CLK SP Q CLK SP Q Combinatorial Active-Low Output, Register Feedback Combinatorial Active-High Output, Register Feedback Combinatorial Outputs 672E-5 Figure 2. PALCE26V2 Macrocell Configuration Options PALCE26V2 Family 2 3
LOGIC DIAGRAM PALCE26V2 CLK /I 9 4 8 2 6 2 24 28 32 36 4 44 48 ASYNCH. RESET D Q Q SP S S 28 I3 27 2 I R S3 * 3 I 2 8 D Q Q SP S S R S3 * 26 9 4 CLK /I 29 2 3 D Q Q SP S S R 9 S3* 25 9 3 5 I 4 42 DQ Q SP S R S 8 S3* 24 8 43 6 I 5 57 DQ Q SP S R S 7 S3 * 23 7 58 DQ Q SP S S 22 6 8 I 6 74 4 8 2 6 2 24 28 32 36 4 44 48 CLK SP CLK 2 * When S 3 = (unprogrammed) the feedback is selected by S. When S 3 = (programmed), the feedback is the opposite of that selected by S. R6 S3* 672E-6 2 GND 2 32 PALCE26V2 Family
LOGIC DIAGRAM (continued) PALCE26V2 4 2 8 6 2 24 28 32 36 4 44 48 CLK SP CLK2 75 9 I 7 9 DQ Q SP S S R5 S3* 2 5 92 I8 6 DQ Q SP S R 4 S S3* 9 4 7 I 9 9 D Q Q SP S R 3 S S3* 8 3 2 2 I 3 D Q Q SP S R 2 S S3* 7 2 3 3 I 39 D Q Q SP S R S S3 * 6 4 4 I 2 48 49 4 2 8 6 2 24 28 32 36 4 44 48 SYNCH PRESET D Q Q SP S R S S3 * 5 * When S 3 = (unprogrammed) the feedback is selected by S. When S 3 = (programmed), the feedback is the opposite of that selected by S. 672E-6 (concluded) PALCE26V2 Family 2 33
ABSOLUTE MAXIMUM RATINGS Storage Temperature........... 65 C to +5 C Ambient Temperature with Power Applied................. 55 C to +25 C Supply Voltage with Respect to Ground..............5 V to +7. V DC Input Voltage................6 V to +7. V DC Output or Pin Voltage................5 V to VCC +.5 V Static Discharge Voltage................. 2 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air.............. C to +75 C Supply Voltage (VCC) with Respect to Ground........ +4.75 V to +5.25 V Industrial (I) Devices Ambient Temperature (TA) Operating in Free Air............ 4 C to +85 C Supply Voltage (VCC) with Respect to Ground.......... +4.5 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max Unit VOH Output HIGH Voltage IOH = 3.2 ma VIN = VIH or VIL 2.4 V VCC = Min VOL Output LOW Voltage IOL = 6 ma VIN = VIH or VIL.4 V VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2. V Voltage for all Inputs (Note ) VIL Input LOW Voltage Guaranteed Input Logical LOW.8 V Voltage for all Inputs (Note ) IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) µa IIL Input LOW Leakage Current VIN = V, VCC = Max (Note 2) µa IOZH Off-State Output Leakage VOUT = 5.25 V, VCC = Max µa Current HIGH VIN = VIH or VIL (Note 2) IOZL Off-State Output Leakage VOUT = V, VCC = Max µa Current LOW VIN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT =.5 V, VCC = Max (Note 3) 3 7 ma ICC VIN = V, Outputs Open (IOUT = ma) H-7/ 5 ma (Static) Commercial Supply Current VCC = Max, f = MHz ICC H-7/ 4 ma (Dynamic) VIN = V, Outputs Open (IOUT = ma) ICC Industrial Supply Current VCC = Max, f = 5 MHz H- 5 ma (Dynamic) Notes:. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT =.5 V has been chosen to avoid test problems caused by tester ground degradation. 2 34 PALCE26V2H-7/ (Com l), H- (Ind)
CAPACITANCE (Note ) AMD Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input Capacitance VIN = V VCC = 5. V 5 TA = +25 C COUT Output Capacitance VOUT = V f = MHz 8 Note:. These parameters are not % tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges (Note 2) Parameter -7 - Symbol Parameter Description Min Max Min Max Unit tpd Input or Feedback to Combinatorial Output 7.5 ns ts Setup Time from Input or Feedback 3.5 5 ns t Setup Time from SP to Clock 4.5 5 ns th Hold Time ns tco Clock to Output 6 9 ns t Asynchronous Reset to Registered Output 3 ns tw Asynchronous Reset Width 6 8 ns tr Asynchronous Reset Recovery Time 5 8 ns tspr Synchronous Preset Recovery Time 5 8 ns twl Clock Width LOW 3.5 4 ns twh HIGH 3.5 4 ns fmax Maximum Frequency External Feedback /(ts + tco) 5.3 7.4 MHz (Notes 3 and 4) Internal Feedback (fcnt) /(ts + tcf) 25 5 MHz tea Input to Output Enable Using Product Term Control 8 ns ter Input to Output Disable Using Product Term Control 7.5 ns Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not % tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 4. tcf is a calculated value and is not guaranteed. tcf can be found using the following equation: tcf = /fmax (internal feedback) ts. pf PALCE26V2H-7/ (Com l), H- (Ind) 2 35
ABSOLUTE MAXIMUM RATINGS Storage Temperature........... 65 C to +5 C Ambient Temperature with Power Applied................. 55 C to +25 C Supply Voltage with Respect to Ground..............5 V to +7. V DC Input Voltage................6 V to +7. V DC Output or Pin Voltage................5 V to VCC +.5 V Static Discharge Voltage................. 2 V Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. Programming conditions may differ. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air.............. C to +75 C Supply Voltage (VCC) with Respect to Ground........ +4.75 V to +5.25 V lndustrial (I) Devices Ambient Temperature (TA) Operating in Free Air............ 4 C to +85 C Supply Voltage (VCC) with Respect to Ground.......... +4.5 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges unless otherwise specified Parameter Symbol Parameter Description Test Conditions Min Max Unit VOH Output HIGH Voltage IOH = 3.2 ma VIN = VIH or VIL 2.4 V VCC = Min VOL Output LOW Voltage IOL = 6 ma VIN = VIH or VIL.4 V VCC = Min VIH Input HIGH Voltage Guaranteed Input Logical HIGH 2. V Voltage for all Inputs (Note ) VIL Input LOW Voltage Guaranteed Input Logical LOW.8 V Voltage for all Inputs (Note ) IIH Input HIGH Leakage Current VIN = 5.25 V, VCC = Max (Note 2) µa IIL Input LOW Leakage Current VIN = V, VCC = Max (Note 2) µa IOZH Off-State Output Leakage VOUT = 5.25 V, VCC = Max µa Current HIGH VIN = VIH or VIL (Note 2) IOZL Off-State Output Leakage VOUT = V, VCC = Max µa Current LOW VIN = VIH or VIL (Note 2) ISC Output Short-Circuit Current VOUT =.5 V, VCC = Max (Note 3) 3 6 ma ICC Commerical Supply Current VIN = V, Outputs Open (IOUT = ma) H-5/2 5 ma (Static) VCC = Max, f = MHz ICC VIN = V, Outputs Open (IOUT = ma) H-5 5 ma (Dynamic) VCC = Max, f = 5 MHz ICC VIN = V, Outputs Open (IOUT = ma) H-2 3 ma Industrial Supply Current (Static) VCC = Max ICC VIN = V, Outputs Open (IOUT = ma) H-2 5 ma (Dynamic) VCC = Max, f = 5 MHz Notes:. These are absolute values with respect to device ground and all overshoots due to system and/or tester noise are included. 2. pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be tested at a time. Duration of the short-circuit should not exceed one second. VOUT =.5 V has been chosen to avoid test problems caused by tester ground degradation. 2 36 PALCE26V2H-5/2 (Com l, Ind)
CAPACITANCE (Note ) AMD Parameter Symbol Parameter Description Test Conditions Typ Unit CIN Input Capacitance VIN = V VCC = 5. V 5 TA = +25 C pf COUT Output Capacitance VOUT = V f = MHz 8 Note:. These parameters are not % tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be affected. SWITCHING CHACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges (Note 2) Parameter -5-2 Symbol Parameter Description Min Max Min Max Unit tpd Input or Feedback to Combinatorial Output 5 2 ns ts Setup Time from Input, Feedback, or SP to Clock 3 ns th Hold Time ns tco Clock to Output 2 ns t Asynchronous Reset to Registered Output 2 25 ns tw Asynchronous Reset Width 5 2 ns tr Asynchronous Reset Recovery Time 5 2 ns tspr Synchronous Preset Recovery Time 3 ns twl Clock Width LOW 8 ns twh HIGH 8 ns fmax Maximum Frequency External Feedback /(ts + tco) 5 4 MHz (Notes 3 and 4) Internal Feedback (fcnt) /(ts + tcf) 58.8 43 MHz tea Input to Output Enable Using Product Term Control 5 2 ns ter Input to Output Disable Using Product Term Control 5 2 ns Notes: 2. See Switching Test Circuit for test conditions. 3. These parameters are not % tested, but are calculated at initial characterization and at any time the design is modified where frequency may be affected. 6. tcf is a calculated value and is not guaranteed. tcf can be found using the following equation: tcf = /fmax (internal feedback) ts. PALCE26V2H-5/2 (Com l, Ind) 2 37
SWITCHING WAVEFORMS Input or Feedback ts th Input or Feedback tpd Clock tco Combinatorial Output Registered Output 672E-7 Combinatorial Output Registered Output 672E-8 Input Clock twh twl Output ter VOH -.5V VOL +.5V tea 672E- Clock Width 672E-9 Input to Output Disable/Enable Input Asserting Asynchronous Reset tw Input Asserting Synchronous Preset t ts th tspr Registered Outputs Clock tr tco Clock Registered Outputs Asynchronous Reset 672E- Synchronous Preset 672E-2 Notes:. =.5 V 2. Input pulse amplitude V to 3. V. 3. Input rise and fall times 2 ns 5 ns typical. 2 38 PALCE26V2 Family
KEY TO SWITCHING WAVEFORMS WAVEFORM INPUTS OUTPUTS Must be Steady Will be Steady May Change from H to L Will be Changing from H to L May Change from L to H Will be Changing from L to H Don t Care, Any Change Permitted Changing, State Unknown Does Not Apply Center Line is High- Impedance Off State KS-PAL SWITCHING TEST CIRCUIT 5 V S R Output Test Point R2 CL 672E-3 Measured Specification S CL R R2 Output Value tpd, tco Closed.5 V Com l: H-5/2 tea Z H: Open 5 pf Ind: H-2.5 V 39 Ω Z L: Closed 3 Ω ter H Z: Open 5 pf Com l: H-7/ H Z: VOH.5 V Ind: H-/5 L Z: Closed 3 Ω L Z: VOL +.5 V PALCE26V2 Family 2 39
TYPICAL ICC CHACTERISTICS FOR THE PALCE26V2H-7/ VCC = 5. V, TA = 25 C 5 25 ICC (ma) 75 5 25 2 3 4 5 Frequency (MHz) 672E-4 The selected typical pattern utilized 5% of the device resources. Half of the macrocells were programmed as registered, and the other half were programmed as combinatorial. Half of the available product terms were used for each macrocell. On any vector, half of the outputs were switching. By utilizing 5% of the device, a midpoint is defined for ICC. From this midpoint, a designer may scale the ICC graphs up or down to estimate the ICC requirements for a particular design. 2 32 PALCE26V2 Family
ENDURANCE CHACTERISTICS The PALCE26V2 is manufactured using AMD s advanced Electrically Erasable process. This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the device can be erased and reprogrammed a feature which allows % testing at the factory. Symbol Parameter Test Conditions Min Unit tdr Min Pattern Data Retention Time Max Storage Temperature Years Max Operating Temperature 2 Years N Min Reprogramming Cycles Normal Programming Conditions Cycles PALCE26V2 Family 2 32
Bus-Friendly Inputs The PALCE26V2H-7/ (Com l) and H-/5 (Ind) inputs and loop back to the input after the second stage of the input buffer. This configuration reinforces the state of the input and pulls the voltage away from the input threshold voltage where noise can cause oscillations. For an illustration of this configuration, see below. INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR REV. C VERSION* VCC kω VCC ESD Protection Input VCC VCC VCC kω * Device PALCE26V2H-7 PALCE26V2H- PALCE26V2H-5 Rev. Letter C Preload Circuitry Feedback Input Output 672E-5 Topside Marking: AMD CMOS PLD s are marked on top of the package in the following manner: PALCE xxxx Datecode (4 numbers) LOT ID (3 characters) (Rev. Letter) The Lot ID and Rev. letter are separated by two spaces. 2 322 PALCE26V2 Family
ROBUSTNESS FEATURES The PALCE26V2 has some unique features that make it extremely robust, especially when operating in high speed design environments. Input clamping circuitry limits negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing. A special noise filter makes the programming circuitry completely insensitive to any positive overshoot that has a pulse width of less than about ns. INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR REV. B VERSION* VCC VCC > 5 kω ESD Protection and Clamping Programming Pins only Programming Voltage Detection Positive Overshoot Filter Programming Circuitry Typical Input VCC VCC > 5 kω Provides ESD Protection and Clamping Preload Circuitry Feedback Input Typical Output 672E-6 * Device PALCE26V2-5 PALCE26V2-2 Rev. Letter B Topside Marking: AMD CMOS PLD s are marked on top of the package in the following manner: PALCE xxxx Datecode (4 numbers) LOT ID (3 characters) (Rev. Letter) The Lot ID and Rev. letter are separated by two spaces. PALCE26V2 Family 2 323
POWER-UP RESET The power-up reset feature ensures that all flip-flops will be reset to LOW after the device has been powered up. The output state will depend on the programmed configuration. This feature is valuable in simplifying state machine initialization. A timing diagram and parameter table are shown below. Due to the synchronous operation of the power-up reset and the wide range of ways VCC can rise to its steady state, two conditions are required to ensure a valid power-up reset. These conditions are: The VCC rise must be monotonic. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met. Parameter Symbol Parameter Description Max Unit tpr Power-Up Reset Time ns ts Input or Feedback Setup Time twl Clock Width LOW See Switching Characteristics Power 4 V VCC tpr Registered Active-Low Output ts Clock twl 672E-7 Power-Up Reset Waveform 2 324 PALCE26V2 Family
TYPICAL THERMAL CHACTERISTICS Measured at 25 C ambient. These parameters are not tested. PALCE26V2 AMD Parameter Typ Symbol Parameter Description SKINNYDIP PLCC Unit θjc Thermal impedance, junction to case 9 8 C/W θja Thermal impedance, junction to ambient 65 55 C/W θjma Thermal impedance, junction to ambient with air flow 2 lfpm air 59 48 C/W 4 lfpm air 54 44 C/W 6 lfpm air 5 39 C/W 8 lfpm air 5 37 C/W Plastic θjc Considerations The data listed for plastic θjc are for reference only and are not recommended for use in calculating junction temperatures. The heat-flow paths in plastic-encapsulated devices are complex, making the θjc measurement relative to a specific location on the package surface. Tests indicate this measurement reference point is directly below the die-attach area on the bottom center of the package. Furthermore, θjc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. PALCE26V2H-5/2 2 325
fmax Parameters The parameter fmax is the maximum clock rate at which the device is guaranteed to operate. Because the flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fmax is specified for three types of synchronous designs. The first type of design is a state machine with feedback signals sent off-chip. This external feedback could go back to the device inputs, or to a second device in a multi-chip state machine. The slowest path defining the period is the sum of the clock-to-output time and the input setup time for the external signals (ts + tco). The reciprocal, fmax, is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fmax is designated fmax external. The second type of design is a single-chip state machine with internal feedback only. In this case, flip-flop inputs are defined by the device inputs and flip-flop outputs. Under these conditions, the period is limited by the internal delay from the flip-flop outputs through the internal feedback and logic to the flip-flop inputs. This fmax is designated fmax internal. A simple internal counter is a good example of this type of design, therefore, this parameter is sometimes called fcnt. The third type of design is a simple data path application. In this case, input data is presented to the flip-flop and clocked through; no feedback is employed. Under these conditions, the period is limited by the sum of the data setup time and the data hold time (ts + th). However, a lower limit for the period of each fmax type is the minimum clock period (twh + twl). Usually, this minimum clock period determines the period for the third fmax, designated fmax no feedback. fmax external and fmax no feedback are calculated parameters. fmax external is calculated from ts and tco, and fmax no feedback is calculated from twl and twh. fmax internal is measured. CLK LOGIC REGISTER (SECOND CHIP) ts tco t S fmax External; /(ts + tco) CLK CLK LOGIC REGISTER LOGIC REGISTER fmax Internal (fcnt) t S fmax No Feedback; /(ts + th) or /(twh + twl) 672E-8 2 326 PALCE26V2 Family