White Paper Using SignalTap II in the Quartus II Software Introduction The SignalTap II embedded logic analyzer, available exclusively in the Altera Quartus II software version 2.1, helps reduce verification times by allowing you to conduct real-time board level tests of Altera devices. Traditional verification methods could be challenging for internal nodes, as they need to be routed to available I/O pins for data capture with an external logic analyzer. The SignalTap II analyzer provides access to an FPGA s internal signals. This white paper gives an overview of the many new features in the SignalTap II logic analyzer and explains how to use its various new options. Figure 1 shows a diagram of the SignalTap II analyzer. 1 To see an example of how to incorporate the SignalTap II Logic Analyzer in your design, refer to Implementation Example on page 3. Figure 1. SignalTap II Embedded Logic Analyzer Diagram The SignalTap II Logic Analyzer The SignalTap II logic analyzer is a second-generation system-level debugging tool that captures and displays real-time signal behavior in a system-on-a-programmable-chip (SOPC), providing the ability to observe interactions between hardware and software in system designs. Comprised of soft intellectual property (IP) cores, programming hardware, and analysis software, the SignalTap II logic analyzer allows you to inspect the FPGA s internal signals while they are running at system speeds, as well as view the captured data as waveforms on your PC or workstation. To use the SignalTap II logic analyzer, you must first create a SignalTap (.stp) file. The.stp file includes all of the configuration settings and stores the captured data. During Quartus II software compilation, the logic analyzer is automatically placed with the rest of the design. The resulting programming file is then used to configure the target FPGA. When the target FPGA is properly configured, the SignalTap II logic analyzer will begin data capture as soon as all trigger conditions are satisfied. WP-SIGNTAPQII-1.0 July 2002, ver. 1.0 1
Hardware Requirements A MasterBlaster or ByteBlasterMV communication cable is required to download configuration data to the FPGA. These download cables also upload captured signal data from the FPGA s dedicated memory to the SignalTap II interface. Captured data is then displayed as logical waveforms in the SignalTap II interface. See the MasterBlaster Serial/USB Communications Cable Data Sheet and the ByteBlasterMV Parallel Port Download Cable Data Sheet for more information. Software Requirements The SignalTap II logic analyzer is available in the Quartus II software version 2.1 and the Quartus II Web Edition version 2.1. Table 1 shows the device support for the SignalTap II logic analyzer. Table 1. SignalTap II Device Support Device Support Stratix devices Full Support in the Quartus II software version 2.1 service pack 1 (SP1). (1) Excalibur devices APEX II devices APEX 20KE devices APEX 20KC devices APEX 20K devices Mercury devices ACEX 1K devices Not supported FLEX 10KE devices Not supported FLEX 6000 devices Not supported MAX 7000B devices Not supported Note to Table 1: (1) Dependant on programming file generation for each device. SignalTap II Analyzer Configuration The SignalTap II logic analyzer can be configured in two ways. The first method uses the FPGA s internal memory to store captured data. The captured data is then transferred from internal memory to the SignalTap II interface via an Altera download cable. With this method, the percentage of resources used in a device is a function of the sample depth, number of channels, and the number of trigger levels specified in the.stp file. For detailed information on resource utilization, refer to Tables 2 through 5 on page 5. The secondconfiguration method uses the FPGA s available I/O pins. This requires the use of an external logic analyzer or oscilloscope and is used when you would like to preserve the on-chip memory resources. Signals are routed from the inside of the device to available I/O pins. For more information on using this method, refer to Debug Ports in the Quartus II Help. 2
Implementation Example The following steps are required to use the SignalTap II logic analyzer to perform board-level verification. 1. To open a new.stp file, choose New (File menu), then click the Other Files tab and select SignalTap II File. Click OK. The SignalTap II window (shown in Figure 2 on page 4) appears. 2. Launch the Node Finder by double-clicking anywhere in the Setup tab of the SignalTap II window. 3. Select the signals that are to be captured and copy them to the Selected Nodes list by clicking the red arrow icon in the SignalTap II window. Click OK. 4. Select a clock signal by clicking the Browse button (...) under Clock in the Signal Configuration panel. 5. Specify the sample depth in the Sample Depth list in the Signal Configuration panel. 6. Save the.stp file. 7. Choose Compiler Settings (Processing menu). Click the SignalTap II Logic Analyzer tab, and turn on Enable SignalTap II Logic Analyzer. In the SignalTap II File name box, type the name of the.stp file you want to compile, or select a file name by clicking the Browse button (...). 8. Compile the design. 9. In the JTAG Chain Configuration panel, select your programming hardware from the Hardware drop-down list, then type the path or browse to the download file. 10. Verify that the programming cable is connecting the Quartus II software to the device on the board, then download the file to the device by clicking the Download File icon. 11. Click the Run Analyzer button (red arrow) to start the analysis. To view the results, click the Data tab in the SignalTap II window. Figure 2 shows the SignalTap II window, and Figure 3 illustrates an example design flow process using the SignalTap II feature. For detailed information on setting up the SignalTap II logic analyzer, go to Overview: Using the SignalTap II Logic Analyzer in the Quartus II Help. 3
Figure 2. SignalTap II User Interface Figure 3. SignalTap II Flow Diagram Your HDL Design Setup Your Design Synthesis, Place & Route Program Device under Test Use Node Finder to Select Signals Setup SignalTap II Embedded Logic Analyzer Set up Signals, Trigger Conditions, and Trigger Levels Synthesis, Place & Route Program Device under Test Capture Samples and Analyze View Samples in Quartus II Software Identify Source of Problem 4
Resource Utilization Tables 2 through 5 show the SignalTap II resource utilization. The number of channels, triggers, and samples that a design can support is limited by the available device resources. Table 2. SignalTap II Logic Element (LE) Utilization Number of Stratix LEs APEX II LEs APEX 20K LEs Channels Number of Trigger Levels 1 2 3 1 2 3 1 2 3 8 219 266 317 244 308 372 216 264 312 16 243 373 466 329 449 573 288 372 462 32 422 596 773 494 732 970 414 588 762 64 689 1,033 1,383 824 1,295 1,768 636 960 1,284 128 2,295 3,662 5,034 2,803 4,670 6,543 3,802 4,669 6,542 1,024 8,696 14,158 19,626 10,704 18,171 26,037 9,174 16,128 23,082 Table 3. M4K Memory Block Utilization in Stratix Devices Number of Number of Samples Channels 256 512 1,024 2,048 32,768 8 1 2 4 64 16 1 2 4 8 128 32 2 4 8 16 256 64 4 8 16 32 512 512 32 64 128 256 Table 4. APEX II Embedded System Block (ESB) Utilization Number of Number of Samples Channels 256 512 1,024 2,048 32,768 8 1 2 4 64 16 1 2 4 8 128 32 2 4 8 16 256 64 4 8 16 32 512 512 32 64 128 256 Table 5. APEX 20K, APEX 20KE & APEX 20KC ESB Utilization Number of Number of Samples Channels 256 512 1,024 2,048 32,768 4 1 1 2 4 64 8 1 2 4 8 128 16 2 4 8 16 256 32 4 8 16 32 512 64 8 16 32 64 1,024 256 32 64 128 5
SignalTap II Features & Benefits Table 6 lists the features and benefits associated with the SignalTap II logic analyzer. The sections that follow describe each feature. Table 6. SignalTap II Features & Benefits Feature Multiple Instances Multi-Level Triggering Multiple Trigger Positions Up to 1,024 channels in each instance Up to 128 K for each channel Mnemonic Table Auto-Detect Devices in JTAG Chain Trigger Input/Trigger Output Signal List File Data Log Benefit Supports multiple clock domains in a single device Allows you to apply complex filters, thereby capturing only the data that you really want to analyze Each trigger can be setup to sample at different ranges relative to the triggering event, allowing more accurate data collection You can sample many signals, allowing for a great deal of data collection to locate the problem Allows a large sample set of data to be acquired for a given signal Labels a bit pattern with a pre-defined value created by the engineer Confirms the connection to a device before attempting to initiate data capture SignalTap II logic analyzer can use an external event to trigger data capture Allows you to view waveforms in a textual format Allows you to recall captured data from previous runs of SignalTap II Multiple Instances The SignalTap II logic analyzer includes support for multiple instances of the logic analyzer in each device. This feature allows the user to create a unique logic analyzer for each clock domain that is present in the FPGA. In the top portion of the SignalTap II window, there is a new panel called the Instance Manager, shown in Figure 4. Selecting an instance from within the Instance Manager displays the set of signals that belong to the selected instance. To add an instance, right click in the Instance Manager panel and select Add Instance. To remove an instance from the Instance Manager, first select the instance to be removed, then right click and select Remove Instance. Figure 4. Instance Manager Multi-Level Triggering You can configure the SignalTap II tool with up to ten trigger levels. This capability offers a great deal of flexibility and allows you to set complex triggering conditions, making it easier to isolate the conditions that cause a functional failure. Multi-level triggering also allows you to view only the most relevant signal data, thus reducing the number of samples and making it easier to locate the source of the problem. The multiple trigger levels are logically ANDED together, and once all of the trigger conditions are satisfied, data capture will commence. To setup multiple trigger levels, use the Signal Configuration panel (shown in Figure 5). 6
Figure 5. Signal Configuration Panel. Multiple Trigger Positions The SignalTap II logic analyzer supports four separate trigger positions: pre-, center, post, and continuous. Acquired data is placed in a circular buffer with the newest samples replacing the oldest. The pre-trigger position tells the software to report 12% of the samples that occurred before the trigger condition was met, and 88% of the samples that occurred after the trigger condition was met. The center trigger position tells the software to report 50% of the samples that occurred before the trigger condition was met, and 50% of the samples that occurred after the trigger condition was met. The post trigger position tells the software to report 88% of the samples that occurred before the trigger condition was met, and 12% of the samples that occurred after the trigger condition was met. The continuous trigger position tells the software to save and report samples continuously even when the trigger condition is met, until terminated by the user. 7
Up to 1,024 Channels in Each Device The number of channels that can be supported in a specific design is largely a function of the available device resources, i.e., logic elements (LEs) and RAM (for more information, see Tables 2 through 5 on page 5). The SignalTap II logic analyzer is capable of managing up to 1,024 channels for each instance. Up to 128 K Samples in Each Device The number of samples that can be stored in the embedded memory of an Altera device is a function of the surplus memory resources on the device that are not consumed by the design under test. However, the SignalTap II logic analyzer can support up to 128 K samples for each channel that is analyzed. Mnemonic Table You can configure the SignalTap II logic analyzer to create mnemonic tables for a group of signals. The mnemonic table feature allows you to assign a set of bit patterns to a name that you define, making captured data easier to locate and utilize. To create a mnemonic table, right click in the Setup view of a SignalTap II window and select Mnemonic Table Setup. Figure 6 shows the Mnemonic Setup dialog box. To assign a group of signals to a mnemonic value, right click on the group and select Bus Display Setup. Figure 6. Mnemonic Setup 8
Auto-detect Devices in a JTAG Chain The SignalTap II JTAG Chain Configuration panel (shown in Figure 7) will automatically scan the hardware to determine that the devices that are physically in the JTAG chain. You can then select the device for verification by selecting the appropriate FPGA in the Device drop-down menu. To configure the SignalTap II logic analyzer to automatically detect devices in the JTAG chain, select the Altera Programming Cable from the Hardware drop-down box and click Scan Chain. Figure 7. JTAG Chain Configuration Dialog Box Trigger Input/Trigger Output The SignalTap II logic analyzer can be configured to capture data when an event external to the FPGA occurs. The external signal is input to a user-defined input pin. Data capture will commence once the external signal matches the user-defined trigger-in input pattern. To use the trigger in functionality, turn on the Trigger In check box in the Signal Configuration panel. Then browse to an input pin in the design using the Node Finder in the Signal Configuration panel. (To launch the Node Finder, double-click anywhere in the Setup tab of the SignalTap II window.) The SignalTap II logic analyzer can output a trigger out signal when a trigger event has occurred. To utilize the trigger out functionality, turn on the trigger out option in the Signal Configuration panel and select an output pin that can be used as the trigger out. The trigger out output level can be selected from either active high or active low. 9
Signal List File The SignalTap II logic analyzer can create a text list file that contains the values of each signal at each sample point. This data mirrors that of the Data view in the SignalTap II window. To create the list file, right click while in the Data view panel and select Create List File. The default name for the list file is <stp file name>.txt. Data Log The data log shows a history of captured data previously acquired with the SignalTap II logic analyzer. If the Data Log check box is turned on in the Data Log panel, then signal data will be saved on each run. The default name for the Data Log entry is log:<date><time><#sample number>. Conclusion As FPGAs decrease in size and increase in complexity, verification engineers will find it increasingly difficult to access device I/O pins for debugging. With the aid of the SignalTap II logic analyzer, this problem becomes virtually non-existent. The SignalTap II logic analyzer offers an easy-to-use and intuitive interface that can capture real-time data at system speeds without the use of an external logic analyzer. Signal capture is accomplished by allocating device resources within the device to embed the SignalTap II logic analyzer. Captured data is then stored in the embedded memory blocks of the FPGA and transferred to the SignalTap II interface via an Altera download cable. The SignalTap II logic analyzer offers a variety of configurations, making it the ideal tool for FPGA verification. Available exclusively in the Quartus II design software, the SignalTap II tool supports the highest number of channels, sample depth, and clock speeds of any logic analyzer in the programmable logic market. 10