APPLICATION NOTE DATE : 28/04/99 Design Considerations when using a Hitachi Medium Resolution Dot Matrix Graphics LCD Introduction Hitachi produces a wide range of monochrome medium resolution dot matrix liquid crystal displays. A number of these displays require the use of an external display controller. This application note will discuss some of the design implications that should be considered when using a dot matrix graphics LCD panel. General Characteristics LCD panels are categorised as non-emissive displays, in that they do not produce any form of light. LCDs manipulate light by either passing or blocking light that is either reflected from an external source or produced by an integrated backlighting system. Display Types Hitachi manufactures a wide range of LCD panels with the following industry standard resolutions: Format Resolution Part Number 1/8 VGA 240 x 160 SP10Q002, LMG7480PMFR, LMG7482PMFE 1/4 VGA 240 x 320 SP10Q005-T 1/4 VGA 320 x 240 LMG7520RPFC, LMG7525RPFF, SP14Q001, SP14Q002 1/2 VGA 640 x 240 SX16H003, SP16H001-T, SR16H005-R VGA 640 x 480 SX19V001-Z1, SX21V001, LMG5278XUFC, LMG7550XUFC SVGA 800 x 600 SX25S003 (Full data and specifications for these displays can be found in the Hitachi Liquid Crystal Graphic Display module data book Reference 06-006C) Typical Applications Applications for LCD panels are many and varied: EPOS, Process Control, Instrumentation, Man Machine Interfaces, Security systems, Hand-held devices, Factory automation, Office automation, Mobile Communications, Handheld devices and many others. Dot Matrix LCD - Principle of Operation Passive dot matrix displays have rows (horizontal) and columns (vertical) of 'optical' electrodes. The electrodes are produced using a semi-transparent metal oxide, Indium Tin Oxide (ITO). The intersection of a row and column forms a dot or pixel element. If an electrical pulse is applied to a pixel, an electric field is established which changes the physical state of liquid crystal from allowing light pass to blocking it. By repeatedly applying a series of pulses in a raster scanning technique an image can be formed on the display. Generating a display image in this way requires display data and three synchronisation clocks: a frame sync, a line sync and a pixel data clock. 1 of 9
Figure 1. Schematic circuit diagram for the Hitachi SP10Q002 1/8 VGA LCD Dot Matrix LCD - Control Signals Frame (FLM - First Line Marker) A frame synchronisation pulse is required at the start of each frame of display data. The FLM signal indicates the start of a new display frame. FLM becomes active after the first Line Pulse of the frame and remains active until the next Line Pulse, at which point it de-asserts and remains inactive until the next frame. The frame rate or refresh rate for a medium resolution monochrome LCD panel is typically between 60 to 140 Hz. (If the LCD is operating with a frame frequency higher or lower than specified maximum or minimum then a rippling or flicker effect may occur). Load (LP - Line Pulse) 2 of 9
A line synchronisation pulse latches a line of display data into the column drivers (IC1, IC2, and IC3). Line Pulse becomes active when a line of pixel data is clocked into the LCD panel and stays asserted for a duration equal to the number of pixel clock periods. CP (Pixel Data Clock) A pixel data shift clock signal is synchronised to the LCD panel output data. The pixel clock is a 50% duty cycle square wave. D0, D1, D2, D3 (4-bit LCD data bus) The LCD data bus transfers pixel data to the panel for display. Data might be arranged differently on the bus depending on the LCD data bus width of the chosen display. Most monochrome medium resolution Hitachi dot matrix panels use a 4-bit LCD data bus. M (alternate LC driving signal) In order to prevent a build up of charge and hence a polarisation of the liquid crystal, the M signal applies a positive and then an equal and opposite negative signal to the LC cell every other frame. This ensures that the liquid crystal changes twist direction every other frame and the resultant DC charge applied to the LC cell is zero. In many LCD modules the M signal is generated internally by the row and column drivers. The M signal is applied directly from the row and column drivers to the pixel element. Vee (LC drive voltage) The contrast of the LCD is adjusted by means of varying a negative bias LC drive voltage. Vee can be controlled using a variable resistor. This will allow the user to adjust the voltage to achieve the maximum contrast in relationship to the users viewing angle relative to the LCD. Thermistors can be used in temperature compensation circuits to control Vee adjustment in a temperature variable environment. Disp Off (Display Off) Disp Off is an active high logic level control signal. Display Off is used in a power on/off sequence to switch the display ON or OFF. This signal is internally applied to all Row and Column drivers. Vdd (Logic Power supply) Typically 3.3v or 5v. Vss (Logic Ground) Logic Ground 3 of 9
Figure 2. Interface timing for the Hitachi SP10Q002 1/8VGA LCD module. Dot Matrix LCD Control - using a microcontroller and on-chip peripherals A basic LCD controller can be implemented using discrete on-chip peripherals of a microcontroller. The following section gives an overview of how this may be done using the on-chip peripherals found on the Hitachi H8 family and SH family of microcontrollers. 4 of 9
Typically, to control a Monochrome, Single Scan, Dot Matrix LCD with a 4-bit LCD data bus (where X = number of rows, Y = number of columns) requires the following peripherals to be used: Integrated Timer Unit (ITU) The integrated timer unit consists of a number of separate 16-bit timer channels, each of which can be clocked from an internal derivative of the system clock. The ITU can therefore be configured to generate the LCD control signals required to control the display. Channel 0 can be configured to produce a CP pulse (Pixel Data Clock). This takes the form of a 50% duty square wave. Channel 1 can be configured to produce a Load signal (Line Pulse). This takes the form of a 1/(X/4) duty square wave. This can be clocked by the output from channel 0 (where X = number of columns, 4 = LCD data bus width) Channel 2 can be configured to produce a Frame pulse (First Line Marker). This takes the form of a 1/Y duty square wave. This can be clocked by the output of channel 1 (where Y = number of rows) Channel 3 can be configured to produce the M signal. Direct Memory Access Controller (DMAC) The DMA controller allows an external or internal interrupt to initiate a data transfer without any CPU intervention. This dramatically reduces the CPU overhead required for interrupt handling. This allows repetitive but important data transfers to be done without reducing overall system performance. The DMAC can perform high-speed transfers between external memory, memory-mapped external devices, on-chip memory and other on-chip peripherals. The DMAC can be configured to transfer a byte of data from display memory to the timer pattern controller next data register (TPC NDR) on each ITU Channel 0 compare match. The DMAC source display memory address is then incremented after each data transfer. The destination for the display data is fixed hence the destination address for the DMA transfer is remains the same. A CPU interrupt is generated after (X x Y)/4 transfers to reset the DMA source display memory address at the end of each frame of display data. (where X= number of columns, Y = number of rows) The timer pattern controller then transfers the display data byte to an 8-bit I/O port from the next data register on each ITU Channel 0 compare match. The I/O port can be connected directly to the LCD data bus. Discrete LCD Controllers A typical LCD controller should be: easy to use in embedded applications support a variety of CPU interfaces have low power consumption offer flexible LCD module support Monochrome and Colour, Single Scan, Dual Scan The LCD controller continuously transfers pixel data into the LCD panel via the LCD data bus. The LCD data bus is timed by the Pixel Data Clock, Line Pulse and FLM signals. The pixel data clock clocks the pixel data into the display drivers internal shift register. The line pulse latches the shifted pixel data into a wide latch at the end of a line while FLM marks the first line of the displayed page. The line pulse signifies the end of the current line of serial data. The line pulse enclosed by the FLM signal marks the end of the first line of the current display frame. Mid-range LCD controllers are designed to support most standard monochrome LCD panels. The end user can configure the display image or text entirely to suit his chosen application. The user can control configuration of character or language fonts, bitmaps, icons and graphics software routines. 5 of 9
Many embedded 16/32-bit microcontrollers and processors have built in LCD controller peripherals enabling simple and quick implementations with full software configuration. LCD controllers are available from the following manufacturers: Epson OKI Yamaha C&T(Intel) www.epson-electronics.de www.oki.co.jp www.yamaha.co.jp www.chips.com (Please note that this is by no means a comprehensive listing of LCD controller manufacturers. A further application note is planned to discuss LCD Controllers in more detail). Figure 3. Epson Electronics SED1300 Series LCD Controllers Part No. B/W Gray Scales Max Colours Max Resolution SED1330 B/W n/a 640 x 256 SED1335/6 B/W n/a 640 x 256 SED1351 2,4 n/a 1024 x 1024 SED1352 4,16 n/a 640 x 480 (4gs) 640 x 400 (16gs) SED1353 4,16 256 640 x 480 (4gs) 640 x 400 (16gs) 320 x 240 (256c) SED1373 4,16 256 640 x 480 (B/W) 640 x 400 (16gs) 320 x 240 (16c) SED1354 4,16 4095 1024 x 768 (4096c) SED1355 4,16 4095 1024 x 768 (4096c) Gray Scale Generation A monochrome LCD panel is physically only able to display black and white levels (on or off). It is not inherently able to display gray shades or gray scales. Therefore, drive methods have been developed to create the appearance of gray shades. There are two methods that can be used to create gray shades. Dithering Dithering is achieved by alternately driving some pixels black and some white in a checkerboard type pattern. When using this method, the pattern should be produced in a random order to create the perception of a gray shade. If dithering is performed using a regular or repeating pattern it can be detected by the human eye. FRC - Frame Rate Control This technique involves increasing the frame rate of the display to allow pixels to be switched on and off quickly, which the human eye will perceive as gray shades. Gray scale generation 6 of 9
In gray scale mode, the number of data words required for displaying gray levels increases as opposed to black/white mode. Also, the line buffer needs to be loaded before the next line is displayed. Therefore, the LCD pixel clock, LCD frame refresh rate, line buffer fill and line to line interval are affected by gray scale generation. Display timing characteristics should be checked to ensure that the display is capable of displaying gray shades or levels. Display Data Mapping Most monochrome displays will support 1, 2 or 4 bits per pixel. In normal (non-gray scale) mode 1 bit per pixel is used. Each bit in the display memory corresponds to a single pixel on the LCD panel. In gray scale mode 2 or 4 bits per pixel are used to generate intermediate gray scales on the LCD panel by adjusting the densities of 1 s and 0 s over many display frames. Figure 3. shows how each pixel is mapped to the display. The total number of columns (X) and the total number of rows (Y) determines display size in pixels. Figure 4. Display Data Mapping LCD Column Drivers (X-1) LCD Row Drivers (Y-1) Display Memory Map The following display memory maps show how 1, 2 and 4 bits per pixel would map to byte wide memory (bits 7-0). As the number of bits per pixel increases the corresponding display memory requirement also increases. Figure 5. Memory map for 1-bit per pixel 7 6 5 4 3 2 1 0 0,0 1,0 2,0 3,0 4,0 5,0 6,0 7,0 8,0 9,0 10,0 11,0 12,0 13,0 14,0 15,0 x-8,y-1 x-7,y-1 x-6,y-1 x-5,y-1 x-4,y-1 x-3,y-1 x-2,y-1 x-1,y-1 7 of 9
Figure 6. Memory map for 2-bits per pixel (memory requirement increases x 2) 7,6 5,4 3,2 1,0 0,0 1,0 2,0 3,0 4,0 5,0 6,0 7,0 8,0 9,0 10,0 11,0 12,0 13,0 14,0 15,0 x-4,y-1 x-3,y-1 x-2,y-1 x-1,y-1 Figure 7. Memory map for 4-bits per pixel (memory requirement increases x 4) 7,6,5,4 3,2,1,0 0,0 1,0 2,0 3,0 4,0 5,0 6,0 7,0 8,0 9,0 10,0 11,0 12,0 13,0 14,0 15,0 x-2,y-1 x-1,y-1 Frequently Asked Questions What is Contrast Ratio? Contrast is defined as the ratio of black to white, or more simply put, how black is black when compared with a white or clear pixel. Passive dot matrix LCD panels usually range from 8:1 (blues,greys) to 25:1 (blacks/whites) What is Shadowing? Shadowing is caused by crosstalk which is best described as the effect when a dark image (box or window shape) is placed in the middle of a white background. Faint vertical and horizontal lines will be seen from the edge of the window proceeding to the edges of the screen. The off selected pixels are not completely off and some charge, very strong at the edge of a window, has leaked into the adjacent pixels creating the effect. This is a common problem and is due to the nature of the LCD technology employed. With higher pixel density, the electrode size must be reduced and the amount of voltage necessary to drive the display rapidly increases. Higher driving voltages create a secondary problem: charging effects. Even though only one row and column are selected, the pulse affects the liquid crystal material near the row and column being charged. The net result is the pixel selected is active (dark), but the areas surrounding the addressed point are also partially active The partially active pixels reduce the display contrast and degrade image quality. What is Ghosting? Ghosting is an issue caused by the speed of the STN material; a display must be able to react in less than 50 milliseconds for performance similar to a CRT. Most monochrome STN materials are between 250 and 600 8 of 9
milliseconds and can not switch from black to a white image that quickly. This problem results in disappearing cursors and blurred images when high speed graphics are utilised. When using this document, keep the following in mind, 1, This document may, wholly or partially, be subject to change without notice. 2, All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi s permission. 3, Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during the operation of the user s unit according to this document. 4, Circuitry and other examples described herein are meant only to indicate the characteristics and performance of Hitachi s semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples therein. 5, No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6, MEDICAL APPLICATIONS: Hitachi s products are not authorised for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi s sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi s products are requested to notify the relevant sales office when planning to use the products in MEDICAL APPLICATIONS. Copyright Hitachi, Ltd.,1999. All rights reserved 9 of 9