LCD MODULE SPECIFICATION

MULTIINNO TECHNOLOGY CO., LTD. LCD MODULE SPECIFICATION Model : MI0350D1T2 Revision Engineering Date Our Reference

MODULE NO.: MI0350D1T2 DOCUMENT REVISION HISTORY DOCUMENT REVISION DATE FROM TO DESCRIPTION CHANGED BY A 2007.09.04 First Release. ZHANG YAN FANG CHECKED BY MOON WU MULTIINNO TECHNOLOGY CO.,LTD. P.2

MODULE NO.: MI0350D1T2 CONTENTS Page No. 1. GENERAL DESCRIPTION 4 2. MECHANICAL SPECIFICATIONS 4 3. INTERFACE SIGNALS 7 4. ABSOLUTE MAXIMUM RATINGS 8 4.1 ELECTRICAL MAXIMUM RATINGS FOR IC ONLY 8 4.2 ENVIRONMENTAL CONDITION 8 5. ELECTRICAL SPECIFICATIONS 9 5.1 TYPICAL ELECTRICAL CHARACTERISTICS 9 5.2 TIMING SPECIFICATIONS 10 5.3 POWER UP SEQUENCE 13 5.4 POWER DOWN SEQUENCE 14 6. OPTICAL CHARACTERISTICS 15 7. RELIABILITY SPECIFICATION 17 8. TFT PANEL INSPECTION SPECIFICATION 18 9. REMARK 20 MULTIINNO TECHNOLOGY CO.,LTD. P.3

MODULE NO.: MI0350D1T2 Preliminary Specification of LCD Module Type Model No.: MI0350D1T2 1. General Description 3.5", 320 x RGB x 240 dots, 262K colors, transmissive, positive, dot matrix LCD module. Amorphous Silicon TFT active matrix. Viewing angle: 12 o clock. Driving scheme: 1/240 duty. Driving IC: HIMAX HX8238A (COG) 960x240 TFT LCD Single Chip Digital driver or equivalent. 24bits parallel RGB input mode. Logic voltage: 2.8V. White LED backlight. FPC connection. RoHS compliance. 2. Mechanical Specifications The mechanical detail is shown in Fig. 1 and summarized in Table 1 below. Table 1 Parameter Specifications Unit Outline dimensions 76.9(W) x 63.9(H) x 3.25(D) (Excluded component area, FPC, terminals mm of backlight) LCD active area 70.08(W) x 52.56(H) mm TFT Display format 320 x RGB x 240 dots 320xRGBx240 Color configuration R.G.B. stripe Dot pitch 0.219(RGB)(W) x 0.219(H) mm Weight Approx: TBD gram MULTIINNO TECHNOLOGY CO.,LTD. P.4

MODULE NO.: MI0350D1T2 MI0350D1T2 Figure 1: Module Specification MULTIINNO TECHNOLOGY CO.,LTD. P.5

MODULE NO.: MI0350D1T2 GND VCC DEN VSYNC HSYNC DOTCLK /RESET /CS SDI SCL POL DE 'HIMAX' HX8238A (COG) 960 x 240 TFT LCD Single Chip Digital Driver or equivalent 240 3.5" TFT LCD DISPLAY 320 x RGB x 240 DOTS 320xRGB D0~D23 24 VBL VBL+ WHITE LED BACKLIGHT Figure 2: Block Diagram MULTIINNO TECHNOLOGY CO.,LTD. P.6

MODULE NO.: MI0350D1T2 3. Interface signals Table 2: Pin assignment Pin No. Symbol Description 1 VBL Cathode of LED backlight. 2 VBL Cathode of LED backlight. 3 VBL+ Anode of LED backlight. 4 VBL+ Anode of LED backlight. 5~6 NC No connection. 7 POL Polarity signal to monitor VCOM signal 8 /RESET (RESB) System reset pin. 9 /CS Chip select pin for serial interface. 10 SCL Clock input pin for serial interface. 11 SDI Data input pin for serial mode. 12~35 D0~D23 Graphic data input pins. 36 HSYNC Line synchronization signal pin. 37 VSYNC Frame synchronization signal pin. 38 DOTCLK Dotclock signal and oscillator source. A nonstop external clock must be provided to that pin even at front or black porch nondisplay period. 39~40 NC No connection. 41~42 VCC Power supply to logic circuit. 43~51 NC No connection. 52 DEN Display enable signal pin. 53~54 GND Ground. MULTIINNO TECHNOLOGY CO.,LTD. P.7

MODULE NO.: MI0350D1T2 4. Absolute Maximum Ratings 4.1 Electrical Maximum Ratings for IC Only Table 3 Parameter Symbol Min. Max. Unit Supply voltage VDD 0.3 +2.7 V VDDIO 0.3 +4.0 V Input voltage VCI VSS0.3 5.0 V Note: 1. The modules may be destroyed if they are used beyond the absolute maximum ratings. 4.2 Environmental Condition Table 4 Item Operating temperature (Topr) Storage temperature (Tstg) (note 1) Min. Max. Min. Max. Ambient temperature (Ta) 20 C +70 C 30 C +80 C Dry 90% max. RH for Ta 40 C Humidity (note 1) < 50% RH for 40 C < Ta Maximum operating temperature Vibration (IEC 6826) cells must be mounted on a suitable connector Shock (IEC 68227) Halfsine pulse shape Frequency: 10 55 Hz Amplitude: 0.75 mm Duration: 20 cycles in each direction. Pulse duration: 11 ms Peak acceleration: 981 m/s 2 = 100g Number of shocks: 3 shocks in 3 mutually perpendicular axes. Remark No condensation 3 directions 3 directions Note 1: Product cannot sustain at extreme storage conditions for long time. MULTIINNO TECHNOLOGY CO.,LTD. P.8

MODULE NO.: MI0350D1T2 5. Electrical Specifications 5.1 Typical Electrical Characteristics At Ta = 25 C, VCC=2.8V, GND=0V. Table 5 Parameter Symbol Conditions Min. Typ. Max. Unit System power supply pin of the logic block VCC 2.8 V TFT Gate ON Voltage VGH(Note 1) 15 V TFT Gate OFF Voltage VGL(Note 2) At Ta=25±5 C 10 V TFT Common VcomH (Note 3) 2.5 4.5 V Electrode Voltage VcomL 3 0 V Low level input voltage V IL 0 0.1VDD V High level input voltage V IH 0.8VDD VDD V Supply current ICC+I VCI VCC=2.8V TBD ma Supply voltage of VLED white LED backlight 18.0 19.2 20.8 V Luminance (on the backlight surface) Forward current =20mA Number of LED dice = 3 x 2 = 6 3200 3600 cd/m 2 Note (1): VGH is TFT Gate operating voltage. Note (2): VGL is TFT Gate operating voltage. The low voltage level VGL signal must be fluctuates with same phase as Vcom, in case of Storage on Gate structure. Note (3): Vcom must be adjusted to optimize display quality. MULTIINNO TECHNOLOGY CO.,LTD. P.9

MODULE NO.: MI0350D1T2 5.2 Timing Specifications 5.2.1 Pixel timing (for reference only) Table 6 Characteristics Symbol Min. Typ. Max. 18 bit 18 bit 18 bit Unit DOTCLK Frequency fdotclk MHz DOTCLK Period tdotclk ns Vertical Sync Setup Time tvsys 20 ns Vertical Sync Hold Time tvsyh 20 ns Horizontal Sync Setup Time thsys 20 ns Horizontal Sync Hold Time thsyh 20 ns Phase difference of Sync Signal Falling Edge thv 1 240 tdotclk DOTCLK Low Period tckl 50 ns DOTCLK High Period tckh 50 ns Data Setup Time tds 12 ns Data hold Time tdh 12 ns Data pulse width tres 10 ns Figure 3: Pixel timing MULTIINNO TECHNOLOGY CO.,LTD. P.10

MODULE NO.: MI0350D1T2 5.2.2 Data transaction timing in normal operating mode (for reference only) Table 7 Characteristics Symbol Min. Typ. Max. 18 bit 18 bit 18 bit Unit DOTCLK Frequency fdotclk MHz DOTCLK Period tdotclk ns Horizontal Frequency (Line) fh KHz Vertical Frequency (Refresh) fv Hz Horizontal Back Porch thbp tdotclk Horizontal Front Porch thfp tdotclk Horizontal Data Start Point thbp tdotclk Horizontal Blanking Period thbp+thfp tdotclk Horizontal Display Area HDISP tdotclk Horizontal Cycle Hcycle 450 tdotclk Vertical Back Porch tvbp Lines Vertical Front Porch tvfp Lines Vertical Data Start Point tvbp Lines Vertical Blanking Period tvbp+tvfp Lines Vertical Display Area VDISP Lines Vertical Cycle Vcycle Lines MULTIINNO TECHNOLOGY CO.,LTD. P.11

MODULE NO.: MI0350D1T2 Figure 4: Data transaction timing in parallel RGB interface (SYNC mode) Figure 5: Signal timing in DE mode MULTIINNO TECHNOLOGY CO.,LTD. P.12

MODULE NO.: MI0350D1T2 5.3 Power up sequence Table 8 Figure 6: Power up sequence MULTIINNO TECHNOLOGY CO.,LTD. P.13

MODULE NO.: MI0350D1T2 5.4 Power down sequence Table 9 Figure 7: Power down sequence MULTIINNO TECHNOLOGY CO.,LTD. P.14

MODULE NO.: MI0350D1T2 6. Optical Characteristics (for TFT panel only) Table 10 7.5 0.64 0.34 0.30 0.58 0.13 0.14 0.31 0.35 All left side data are based on following conditiont6 NTSC:60% LC:5091 Light: C light (Machine: BM5A) Normal Polarizer without DBEF ereference only MULTIINNO TECHNOLOGY CO.,LTD. P.15

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MODULE NO.: MI0350D1T2 7. Reliability specification (for TFT panel only) MULTIINNO TECHNOLOGY CO.,LTD. P.17

MODULE NO.: MI0350D1T2 8. TFT panel inspection specification MULTIINNO TECHNOLOGY CO.,LTD. P.18

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MODULE NO.: MI0350D1T2 9. Remark MULTIINNO MULTIINNO MULTIINNO MULTIINNO MULTIINNO MULTIINNO MULTIINNO MULTIINNO MULTIINNO MULTIINNO MULTIINNO END MULTIINNO TECHNOLOGY CO.,LTD. P.20