September 21, 2005 MagnaChip HV7161SP 1.3 Megapixel Process Review For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.
MEMS Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Major Findings 2 Package and Die 2.1 Package 2.2 Die 2.3 Die Features 3 Process 3.1 General Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 MOS Transistors and Poly 3.7 Isolation 3.8 Wells and Epi 4 Pixel Array Analysis 4.1 Pixel Schematic 4.2 Pixel Array Plan-View Analysis 4.3 Pixel Array Cross-Sectional Analysis
MEMS Process Review 5 Embedded SRAM Analysis 5.1 Cell Overview 5.2 6T SRAM Plan-View Analysis 6 Critical Dimensions 6.1 Package and Die 6.2 Vertical Dimensions 6.3 Horizontal Dimensions Report Evaluation
Overview 1 Overview 1.1 List of Figures 2.1.1 Samsung SPH-M4300 Cell Phone Front 2.1.2 Samsung SPH-M4300 Cell Phone Back 2.1.3 Identification Markings on Samsung SPH-M4300 Cell Phone 2.1.4 CIS Assembly on a Board Inside the Samsung SPH-M4300 Cell Phone 2.1.5 CIS Assembly on a Board Detail 2.1.6 CIS Assembly Tilt-View 2.1.7 CIS Assembly Top-View 2.1.8 CIS Assembly Back-View 2.1.9 CIS Assembly Partially Disassembled 2.1.10 CIS Assembly X-Ray Top-View 2.1.11 CIS Assembly X-Ray Side-View 2.2.1 Die Photograph 2.2.2 Die Markings a 2.2.3 Die Markings b 2.2.4 Annotated Die Photograph 2.3.1 Typical Die Corner 2.3.2 Die Corner a 2.3.3 Die Corner b 2.3.4 Die Corner c 2.3.5 Die Corner d 2.3.6 Minimum Pitch Bond Pads 2.3.7 Single Bond Pad Detail 3.1.1 General Structure 3.1.2 Die Edge 3.1.3 Die Edge Seal 3.2.1 Bond Pad 3.2.2 Bond Pad Edge 3.2.3 Bond Pad Edge Detail 3.3.1 Passivation 3.3.2 ILD 3 3.3.3 ILD 2 3.3.4 ILD 1 3.3.5 PMD and STI 3.4.1 Minimum Metal 4 3.4.2 Minimum Metal 3 1-1
Overview 3.4.3 Minimum Metal 2 3.4.4 Minimum Metal 1 3.5.1 Minimum Pitch Via 3s 3.5.2 Minimum Pitch Via 2s 3.5.3 Minimum Pitch Via 1s and Contacts to Substrate 3.5.4 Minimum Space Contacts to Poly 3.6.1 Peripheral CMOS 3.6.2 Peripheral NMOS 3.6.3 Peripheral pmos 3.6.4 Peripheral MOS Transistors 3.7.1 Minimum Width STI 3.7.2 Poly over STI 3.8.1 SRP of P-Well 3.8.2 SRM of N-Well 3.8.3 SRP in Pixel Array 3.8.4 Pixel Array Epi and Substrate SCM 4.1.1 Pixel Schematic Circuit 4.2.1 Pixel Array Corner Optical 4.2.2 Pixel Array Detail Optical 4.2.3 Pixel Array Lenses 4.2.4 Pixel Array Lenses and Color Filters 4.2.5 Pixel Array at Metal 2 4.2.6 Pixel Array at Metal 1 4.2.7 Pixel Array at Poly 4.2.8 Pixel Array at Substrate 4.2.9 Pixel Array at Substrate SCM 4.2.10 Pixel Array at Substrate SCM 4.3.1 Pixel at Poly Showing Cross-Sectional Planes Plan-View 4.3.2 Pixel Array General Structure (Cross-Section A) 4.3.3 Pixel Array Edge General Struc ture (Cross-Section B) 4.3.4 Lenses and Blue and Green Color FIlters (Cross-Section B) 4.3.5 Lenses and Red-Green Color Filters (Cross-Section B) 4.3.6 Pixel Structure Through T1 Transistor (Cross-Section B) 4.3.7 T1 Transistor (Cross-Section B) 4.3.8 T1 Transistor Gate Contact (Cross-Section B) 4.3.9 Pixel Through Transfer Transistor SCM (Cross-Section B) 4.3.10 T1 Transfer Transistor Width (Cross-Section C) 1-2
Overview 4.3.11 T2 Reset TransistorLength (Cross-Section D) 4.3.12 T2 Reset Transistor Width (Cross-Section E) 4.3.13 T3 Source Follower and T4 Row Select Transistors (Cross-Section F) 4.3.14 T3 Source Follower and T4 Row Select Transistors Detail (Cross-Section F) 5.1.1 Die Photo Showing SRAM Location 5.1.2 6T SRAM Cell 5.2.1 SRAM at Metal 1 5.2.2 SRAM at Poly 5.2.3 SRAM at Poly Detail 5.2.4 SRAM at Diffusion 1.2 List of Tables 1.5.1 Image Sensor Device Summary 1.6.1 Summary of Major Findings 2.3.1 Package and Die Dimensions 3.3.1 Dielectric Composition and Thicknesses 3.4.1 Metallization Comosition and Thicknesses 3.4.2 Minimum Metal Horizontal Dimensions 3.5.1 Via and Contact Horizontal Dimensions 3.6.1 Transistor and Polysilicon Horizontal Dimensions 3.6.2 Transistor and Polysilicon Vertical Dimensions 3.7.1 Isolation Horizontal Dimension 3.8.1 Wells and Epi Vertical Dimensions 4.2.1 Pixel Horizontal Dimensions 4.3.1 Pixel Vertical Dimensions 4.3.2 Transistor Dimensions in Pixel Array 5.2.1 SRAM Transistor Sizes 6.1.1 Package and Die 6.2.1 Dielectrics 6.2.2 Metals 6.2.3 Transistors 6.2.4 Wells 6.3.1 Metals 6.3.2 Contacts 6.3.3 Transistors 6.3.4 Isolation 1-3
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